Merge tag 'for-6.2-rc2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave...
[platform/kernel/linux-starfive.git] / drivers / pwm / pwm-keembay.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Intel Keem Bay PWM driver
4  *
5  * Copyright (C) 2020 Intel Corporation
6  * Authors: Lai Poey Seng <poey.seng.lai@intel.com>
7  *          Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
8  *
9  * Limitations:
10  * - Upon disabling a channel, the currently running
11  *   period will not be completed. However, upon
12  *   reconfiguration of the duty cycle/period, the
13  *   currently running period will be completed first.
14  */
15
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pwm.h>
23 #include <linux/regmap.h>
24
25 #define KMB_TOTAL_PWM_CHANNELS          6
26 #define KMB_PWM_COUNT_MAX               U16_MAX
27 #define KMB_PWM_EN_BIT                  BIT(31)
28
29 /* Mask */
30 #define KMB_PWM_HIGH_MASK               GENMASK(31, 16)
31 #define KMB_PWM_LOW_MASK                GENMASK(15, 0)
32 #define KMB_PWM_LEADIN_MASK             GENMASK(30, 0)
33
34 /* PWM Register offset */
35 #define KMB_PWM_LEADIN_OFFSET(ch)       (0x00 + 4 * (ch))
36 #define KMB_PWM_HIGHLOW_OFFSET(ch)      (0x20 + 4 * (ch))
37
38 struct keembay_pwm {
39         struct pwm_chip chip;
40         struct device *dev;
41         struct clk *clk;
42         void __iomem *base;
43 };
44
45 static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip)
46 {
47         return container_of(chip, struct keembay_pwm, chip);
48 }
49
50 static void keembay_clk_unprepare(void *data)
51 {
52         clk_disable_unprepare(data);
53 }
54
55 static int keembay_clk_enable(struct device *dev, struct clk *clk)
56 {
57         int ret;
58
59         ret = clk_prepare_enable(clk);
60         if (ret)
61                 return ret;
62
63         return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk);
64 }
65
66 /*
67  * With gcc 10, CONFIG_CC_OPTIMIZE_FOR_SIZE and only "inline" instead of
68  * "__always_inline" this fails to compile because the compiler doesn't notice
69  * for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
70  */
71 static __always_inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,
72                                            u32 val, u32 offset)
73 {
74         u32 buff = readl(priv->base + offset);
75
76         buff = u32_replace_bits(buff, val, mask);
77         writel(buff, priv->base + offset);
78 }
79
80 static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)
81 {
82         keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,
83                                 KMB_PWM_LEADIN_OFFSET(ch));
84 }
85
86 static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
87 {
88         keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,
89                                 KMB_PWM_LEADIN_OFFSET(ch));
90 }
91
92 static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
93                                  struct pwm_state *state)
94 {
95         struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
96         unsigned long long high, low;
97         unsigned long clk_rate;
98         u32 highlow;
99
100         clk_rate = clk_get_rate(priv->clk);
101
102         /* Read channel enabled status */
103         highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
104         if (highlow & KMB_PWM_EN_BIT)
105                 state->enabled = true;
106         else
107                 state->enabled = false;
108
109         /* Read period and duty cycle */
110         highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
111         low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;
112         high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC;
113         state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
114         state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
115         state->polarity = PWM_POLARITY_NORMAL;
116
117         return 0;
118 }
119
120 static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
121                              const struct pwm_state *state)
122 {
123         struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
124         struct pwm_state current_state;
125         unsigned long long div;
126         unsigned long clk_rate;
127         u32 pwm_count = 0;
128         u16 high, low;
129
130         if (state->polarity != PWM_POLARITY_NORMAL)
131                 return -EINVAL;
132
133         /*
134          * Configure the pwm repeat count as infinite at (15:0) and leadin
135          * low time as 0 at (30:16), which is in terms of clock cycles.
136          */
137         keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,
138                                 KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
139
140         keembay_pwm_get_state(chip, pwm, &current_state);
141
142         if (!state->enabled) {
143                 if (current_state.enabled)
144                         keembay_pwm_disable(priv, pwm->hwpwm);
145                 return 0;
146         }
147
148         /*
149          * The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET
150          * register contain the high time and low time of waveform accordingly.
151          * All the values are in terms of clock cycles.
152          */
153
154         clk_rate = clk_get_rate(priv->clk);
155         div = clk_rate * state->duty_cycle;
156         div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
157         if (div > KMB_PWM_COUNT_MAX)
158                 return -ERANGE;
159
160         high = div;
161         div = clk_rate * state->period;
162         div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
163         div = div - high;
164         if (div > KMB_PWM_COUNT_MAX)
165                 return -ERANGE;
166
167         low = div;
168
169         pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) |
170                     FIELD_PREP(KMB_PWM_LOW_MASK, low);
171
172         writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
173
174         if (state->enabled && !current_state.enabled)
175                 keembay_pwm_enable(priv, pwm->hwpwm);
176
177         return 0;
178 }
179
180 static const struct pwm_ops keembay_pwm_ops = {
181         .owner = THIS_MODULE,
182         .apply = keembay_pwm_apply,
183         .get_state = keembay_pwm_get_state,
184 };
185
186 static int keembay_pwm_probe(struct platform_device *pdev)
187 {
188         struct device *dev = &pdev->dev;
189         struct keembay_pwm *priv;
190         int ret;
191
192         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
193         if (!priv)
194                 return -ENOMEM;
195
196         priv->clk = devm_clk_get(dev, NULL);
197         if (IS_ERR(priv->clk))
198                 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");
199
200         priv->base = devm_platform_ioremap_resource(pdev, 0);
201         if (IS_ERR(priv->base))
202                 return PTR_ERR(priv->base);
203
204         ret = keembay_clk_enable(dev, priv->clk);
205         if (ret)
206                 return ret;
207
208         priv->chip.dev = dev;
209         priv->chip.ops = &keembay_pwm_ops;
210         priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;
211
212         ret = devm_pwmchip_add(dev, &priv->chip);
213         if (ret)
214                 return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
215
216         return 0;
217 }
218
219 static const struct of_device_id keembay_pwm_of_match[] = {
220         { .compatible = "intel,keembay-pwm" },
221         { }
222 };
223 MODULE_DEVICE_TABLE(of, keembay_pwm_of_match);
224
225 static struct platform_driver keembay_pwm_driver = {
226         .probe  = keembay_pwm_probe,
227         .driver = {
228                 .name = "pwm-keembay",
229                 .of_match_table = keembay_pwm_of_match,
230         },
231 };
232 module_platform_driver(keembay_pwm_driver);
233
234 MODULE_ALIAS("platform:pwm-keembay");
235 MODULE_DESCRIPTION("Intel Keem Bay PWM driver");
236 MODULE_LICENSE("GPL v2");