drivers/pwm/pwm-jz4740.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
   4  *  JZ4740 platform PWM support
   5  *
   6  * Limitations:
   7  * - The .apply callback doesn't complete the currently running period before
   8  *   reconfiguring the hardware.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/err.h>
  13 #include <linux/gpio.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mfd/ingenic-tcu.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pwm.h>
  21 #include <linux/regmap.h>
  22
  23 struct soc_info {
  24         unsigned int num_pwms;
  25 };
  26
  27 struct jz4740_pwm_chip {
  28         struct pwm_chip chip;
  29         struct regmap *map;
  30 };
  31
  32 static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
  33 {
  34         return container_of(chip, struct jz4740_pwm_chip, chip);
  35 }
  36
  37 static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
  38                                    unsigned int channel)
  39 {
  40         /* Enable all TCU channels for PWM use by default except channels 0/1 */
  41         u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
  42
  43         device_property_read_u32(jz->chip.dev->parent,
  44                                  "ingenic,pwm-channels-mask",
  45                                  &pwm_channels_mask);
  46
  47         return !!(pwm_channels_mask & BIT(channel));
  48 }
  49
  50 static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  51 {
  52         struct jz4740_pwm_chip *jz = to_jz4740(chip);
  53         struct clk *clk;
  54         char name[16];
  55         int err;
  56
  57         if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm))
  58                 return -EBUSY;
  59
  60         snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
  61
  62         clk = clk_get(chip->dev, name);
  63         if (IS_ERR(clk)) {
  64                 dev_err(chip->dev, "error %pe: Failed to get clock\n", clk);
  65                 return PTR_ERR(clk);
  66         }
  67
  68         err = clk_prepare_enable(clk);
  69         if (err < 0) {
  70                 clk_put(clk);
  71                 return err;
  72         }
  73
  74         pwm_set_chip_data(pwm, clk);
  75
  76         return 0;
  77 }
  78
  79 static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  80 {
  81         struct clk *clk = pwm_get_chip_data(pwm);
  82
  83         clk_disable_unprepare(clk);
  84         clk_put(clk);
  85 }
  86
  87 static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  88 {
  89         struct jz4740_pwm_chip *jz = to_jz4740(chip);
  90
  91         /* Enable PWM output */
  92         regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
  93
  94         /* Start counter */
  95         regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
  96
  97         return 0;
  98 }
  99
 100 static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 101 {
 102         struct jz4740_pwm_chip *jz = to_jz4740(chip);
 103
 104         /*
 105          * Set duty > period. This trick allows the TCU channels in TCU2 mode to
 106          * properly return to their init level.
 107          */
 108         regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
 109         regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
 110
 111         /*
 112          * Disable PWM output.
 113          * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
 114          * counter is stopped, while in TCU1 mode the order does not matter.
 115          */
 116         regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
 117
 118         /* Stop counter */
 119         regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
 120 }
 121
 122 static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 123                             const struct pwm_state *state)
 124 {
 125         struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
 126         unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
 127         struct clk *clk = pwm_get_chip_data(pwm);
 128         unsigned long period, duty;
 129         long rate;
 130         int err;
 131
 132         /*
 133          * Limit the clock to a maximum rate that still gives us a period value
 134          * which fits in 16 bits.
 135          */
 136         do_div(tmp, state->period);
 137
 138         /*
 139          * /!\ IMPORTANT NOTE:
 140          * -------------------
 141          * This code relies on the fact that clk_round_rate() will always round
 142          * down, which is not a valid assumption given by the clk API, but only
 143          * happens to be true with the clk drivers used for Ingenic SoCs.
 144          *
 145          * Right now, there is no alternative as the clk API does not have a
 146          * round-down function (and won't have one for a while), but if it ever
 147          * comes to light, a round-down function should be used instead.
 148          */
 149         rate = clk_round_rate(clk, tmp);
 150         if (rate < 0) {
 151                 dev_err(chip->dev, "Unable to round rate: %ld", rate);
 152                 return rate;
 153         }
 154
 155         /* Calculate period value */
 156         tmp = (unsigned long long)rate * state->period;
 157         do_div(tmp, NSEC_PER_SEC);
 158         period = tmp;
 159
 160         /* Calculate duty value */
 161         tmp = (unsigned long long)rate * state->duty_cycle;
 162         do_div(tmp, NSEC_PER_SEC);
 163         duty = tmp;
 164
 165         if (duty >= period)
 166                 duty = period - 1;
 167
 168         jz4740_pwm_disable(chip, pwm);
 169
 170         err = clk_set_rate(clk, rate);
 171         if (err) {
 172                 dev_err(chip->dev, "Unable to set rate: %d", err);
 173                 return err;
 174         }
 175
 176         /* Reset counter to 0 */
 177         regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
 178
 179         /* Set duty */
 180         regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
 181
 182         /* Set period */
 183         regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period);
 184
 185         /* Set abrupt shutdown */
 186         regmap_set_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
 187                         TCU_TCSR_PWM_SD);
 188
 189         /*
 190          * Set polarity.
 191          *
 192          * The PWM starts in inactive state until the internal timer reaches the
 193          * duty value, then becomes active until the timer reaches the period
 194          * value. In theory, we should then use (period - duty) as the real duty
 195          * value, as a high duty value would otherwise result in the PWM pin
 196          * being inactive most of the time.
 197          *
 198          * Here, we don't do that, and instead invert the polarity of the PWM
 199          * when it is active. This trick makes the PWM start with its active
 200          * state instead of its inactive state.
 201          */
 202         if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
 203                 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
 204                                    TCU_TCSR_PWM_INITL_HIGH, 0);
 205         else
 206                 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
 207                                    TCU_TCSR_PWM_INITL_HIGH,
 208                                    TCU_TCSR_PWM_INITL_HIGH);
 209
 210         if (state->enabled)
 211                 jz4740_pwm_enable(chip, pwm);
 212
 213         return 0;
 214 }
 215
 216 static const struct pwm_ops jz4740_pwm_ops = {
 217         .request = jz4740_pwm_request,
 218         .free = jz4740_pwm_free,
 219         .apply = jz4740_pwm_apply,
 220         .owner = THIS_MODULE,
 221 };
 222
 223 static int jz4740_pwm_probe(struct platform_device *pdev)
 224 {
 225         struct device *dev = &pdev->dev;
 226         struct jz4740_pwm_chip *jz4740;
 227         const struct soc_info *info;
 228
 229         info = device_get_match_data(dev);
 230         if (!info)
 231                 return -EINVAL;
 232
 233         jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL);
 234         if (!jz4740)
 235                 return -ENOMEM;
 236
 237         jz4740->map = device_node_to_regmap(dev->parent->of_node);
 238         if (IS_ERR(jz4740->map)) {
 239                 dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz4740->map));
 240                 return PTR_ERR(jz4740->map);
 241         }
 242
 243         jz4740->chip.dev = dev;
 244         jz4740->chip.ops = &jz4740_pwm_ops;
 245         jz4740->chip.npwm = info->num_pwms;
 246
 247         return devm_pwmchip_add(dev, &jz4740->chip);
 248 }
 249
 250 static const struct soc_info jz4740_soc_info = {
 251         .num_pwms = 8,
 252 };
 253
 254 static const struct soc_info jz4725b_soc_info = {
 255         .num_pwms = 6,
 256 };
 257
 258 static const struct soc_info x1000_soc_info = {
 259         .num_pwms = 5,
 260 };
 261
 262 static const struct of_device_id jz4740_pwm_dt_ids[] = {
 263         { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
 264         { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
 265         { .compatible = "ingenic,x1000-pwm", .data = &x1000_soc_info },
 266         {},
 267 };
 268 MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
 269
 270 static struct platform_driver jz4740_pwm_driver = {
 271         .driver = {
 272                 .name = "jz4740-pwm",
 273                 .of_match_table = jz4740_pwm_dt_ids,
 274         },
 275         .probe = jz4740_pwm_probe,
 276 };
 277 module_platform_driver(jz4740_pwm_driver);
 278
 279 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 280 MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
 281 MODULE_ALIAS("platform:jz4740-pwm");
 282 MODULE_LICENSE("GPL");