1 // SPDX-License-Identifier: GPL-2.0+
3 * Azoteq IQS620A PWM Generator
5 * Copyright (C) 2019 Jeff LaBundy <jeff@labundy.com>
8 * - The period is fixed to 1 ms and is generated continuously despite changes
9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
11 * and may result in a glitch during the period in which the change is made.
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
13 * ms, the output is disabled and relies upon an external pull-down resistor
14 * to hold the GPIO3/LTX pin low.
17 #include <linux/device.h>
18 #include <linux/kernel.h>
19 #include <linux/mfd/iqs62x.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/notifier.h>
23 #include <linux/platform_device.h>
24 #include <linux/pwm.h>
25 #include <linux/regmap.h>
26 #include <linux/slab.h>
28 #define IQS620_PWR_SETTINGS 0xd2
29 #define IQS620_PWR_SETTINGS_PWM_OUT BIT(7)
31 #define IQS620_PWM_DUTY_CYCLE 0xd8
33 #define IQS620_PWM_PERIOD_NS 1000000
35 struct iqs620_pwm_private {
36 struct iqs62x_core *iqs62x;
38 struct notifier_block notifier;
40 unsigned int duty_scale;
43 static int iqs620_pwm_init(struct iqs620_pwm_private *iqs620_pwm,
44 unsigned int duty_scale)
46 struct iqs62x_core *iqs62x = iqs620_pwm->iqs62x;
50 return regmap_clear_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,
51 IQS620_PWR_SETTINGS_PWM_OUT);
53 ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
58 return regmap_set_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,
59 IQS620_PWR_SETTINGS_PWM_OUT);
62 static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
63 const struct pwm_state *state)
65 struct iqs620_pwm_private *iqs620_pwm;
66 unsigned int duty_cycle;
67 unsigned int duty_scale;
70 if (state->polarity != PWM_POLARITY_NORMAL)
73 if (state->period < IQS620_PWM_PERIOD_NS)
76 iqs620_pwm = container_of(chip, struct iqs620_pwm_private, chip);
79 * The duty cycle generated by the device is calculated as follows:
81 * duty_cycle = (IQS620_PWM_DUTY_CYCLE + 1) / 256 * 1 ms
83 * ...where IQS620_PWM_DUTY_CYCLE is a register value between 0 and 255
84 * (inclusive). Therefore the lowest duty cycle the device can generate
85 * while the output is enabled is 1 / 256 ms.
87 * For lower duty cycles (e.g. 0), the PWM output is simply disabled to
88 * allow an external pull-down resistor to hold the GPIO3/LTX pin low.
90 duty_cycle = min_t(u64, state->duty_cycle, IQS620_PWM_PERIOD_NS);
91 duty_scale = duty_cycle * 256 / IQS620_PWM_PERIOD_NS;
96 mutex_lock(&iqs620_pwm->lock);
98 ret = iqs620_pwm_init(iqs620_pwm, duty_scale);
100 iqs620_pwm->duty_scale = duty_scale;
102 mutex_unlock(&iqs620_pwm->lock);
107 static int iqs620_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
108 struct pwm_state *state)
110 struct iqs620_pwm_private *iqs620_pwm;
112 iqs620_pwm = container_of(chip, struct iqs620_pwm_private, chip);
114 mutex_lock(&iqs620_pwm->lock);
117 * Since the device cannot generate a 0% duty cycle, requests to do so
118 * cause subsequent calls to iqs620_pwm_get_state to report the output
119 * as disabled. This is not ideal, but is the best compromise based on
120 * the capabilities of the device.
122 state->enabled = iqs620_pwm->duty_scale > 0;
123 state->duty_cycle = DIV_ROUND_UP(iqs620_pwm->duty_scale *
124 IQS620_PWM_PERIOD_NS, 256);
126 mutex_unlock(&iqs620_pwm->lock);
128 state->period = IQS620_PWM_PERIOD_NS;
129 state->polarity = PWM_POLARITY_NORMAL;
134 static int iqs620_pwm_notifier(struct notifier_block *notifier,
135 unsigned long event_flags, void *context)
137 struct iqs620_pwm_private *iqs620_pwm;
140 if (!(event_flags & BIT(IQS62X_EVENT_SYS_RESET)))
143 iqs620_pwm = container_of(notifier, struct iqs620_pwm_private,
146 mutex_lock(&iqs620_pwm->lock);
149 * The parent MFD driver already prints an error message in the event
150 * of a device reset, so nothing else is printed here unless there is
151 * an additional failure.
153 ret = iqs620_pwm_init(iqs620_pwm, iqs620_pwm->duty_scale);
155 mutex_unlock(&iqs620_pwm->lock);
158 dev_err(iqs620_pwm->chip.dev,
159 "Failed to re-initialize device: %d\n", ret);
166 static const struct pwm_ops iqs620_pwm_ops = {
167 .apply = iqs620_pwm_apply,
168 .get_state = iqs620_pwm_get_state,
169 .owner = THIS_MODULE,
172 static void iqs620_pwm_notifier_unregister(void *context)
174 struct iqs620_pwm_private *iqs620_pwm = context;
177 ret = blocking_notifier_chain_unregister(&iqs620_pwm->iqs62x->nh,
178 &iqs620_pwm->notifier);
180 dev_err(iqs620_pwm->chip.dev,
181 "Failed to unregister notifier: %d\n", ret);
184 static int iqs620_pwm_probe(struct platform_device *pdev)
186 struct iqs62x_core *iqs62x = dev_get_drvdata(pdev->dev.parent);
187 struct iqs620_pwm_private *iqs620_pwm;
191 iqs620_pwm = devm_kzalloc(&pdev->dev, sizeof(*iqs620_pwm), GFP_KERNEL);
195 iqs620_pwm->iqs62x = iqs62x;
197 ret = regmap_read(iqs62x->regmap, IQS620_PWR_SETTINGS, &val);
201 if (val & IQS620_PWR_SETTINGS_PWM_OUT) {
202 ret = regmap_read(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE, &val);
206 iqs620_pwm->duty_scale = val + 1;
209 iqs620_pwm->chip.dev = &pdev->dev;
210 iqs620_pwm->chip.ops = &iqs620_pwm_ops;
211 iqs620_pwm->chip.npwm = 1;
213 mutex_init(&iqs620_pwm->lock);
215 iqs620_pwm->notifier.notifier_call = iqs620_pwm_notifier;
216 ret = blocking_notifier_chain_register(&iqs620_pwm->iqs62x->nh,
217 &iqs620_pwm->notifier);
219 dev_err(&pdev->dev, "Failed to register notifier: %d\n", ret);
223 ret = devm_add_action_or_reset(&pdev->dev,
224 iqs620_pwm_notifier_unregister,
229 ret = devm_pwmchip_add(&pdev->dev, &iqs620_pwm->chip);
231 dev_err(&pdev->dev, "Failed to add device: %d\n", ret);
236 static struct platform_driver iqs620_pwm_platform_driver = {
238 .name = "iqs620a-pwm",
240 .probe = iqs620_pwm_probe,
242 module_platform_driver(iqs620_pwm_platform_driver);
244 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
245 MODULE_DESCRIPTION("Azoteq IQS620A PWM Generator");
246 MODULE_LICENSE("GPL");
247 MODULE_ALIAS("platform:iqs620a-pwm");