1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Basic support for the pwm module on imx6.
14 #include <asm/arch/imx-regs.h>
18 int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
19 unsigned long duty_cycles, unsigned long prescale)
24 cr = PWMCR_PRESCALER(prescale) |
25 PWMCR_DOZEEN | PWMCR_WAITEN |
26 PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH;
30 writel(duty_cycles, &pwm->sar);
31 /* set period cycles */
32 writel(period_cycles, &pwm->pr);
37 /* pwm_id from 0..7 */
38 struct pwm_regs *pwm_id_to_reg(int pwm_id)
43 return (struct pwm_regs *)PWM1_BASE_ADDR;
45 return (struct pwm_regs *)PWM2_BASE_ADDR;
48 return (struct pwm_regs *)PWM3_BASE_ADDR;
50 return (struct pwm_regs *)PWM4_BASE_ADDR;
54 return (struct pwm_regs *)PWM5_BASE_ADDR;
56 return (struct pwm_regs *)PWM6_BASE_ADDR;
58 return (struct pwm_regs *)PWM7_BASE_ADDR;
60 return (struct pwm_regs *)PWM8_BASE_ADDR;
63 printf("unknown pwm_id: %d\n", pwm_id);
69 int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
70 unsigned long *duty_c, unsigned long *prescale)
75 * we have not yet a clock framework for imx6, so add the clock
76 * value here as a define. Replace it when we have the clock
79 c = CFG_IMX6_PWM_PER_CLK;
81 do_div(c, 1000000000);
84 *prescale = *period_c / 0x10000 + 1;
86 *period_c /= *prescale;
87 c = *period_c * (unsigned long long)duty_ns;
92 * according to imx pwm RM, the real period value should be
93 * PERIOD value in PWMPR plus 2.
103 int pwm_init(int pwm_id, int div, int invert)
105 struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
114 int pwm_config(int pwm_id, int duty_ns, int period_ns)
116 struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
117 unsigned long period_cycles, duty_cycles, prescale;
122 pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
125 return pwm_config_internal(pwm, period_cycles, duty_cycles, prescale);
128 int pwm_enable(int pwm_id)
130 struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
135 setbits_le32(&pwm->cr, PWMCR_EN);
139 void pwm_disable(int pwm_id)
141 struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
146 clrbits_le32(&pwm->cr, PWMCR_EN);
150 struct imx_pwm_priv {
151 struct pwm_regs *regs;
157 int pwm_dm_imx_get_parms(struct imx_pwm_priv *priv, int period_ns,
158 int duty_ns, unsigned long *period_c, unsigned long *duty_c,
159 unsigned long *prescale)
161 unsigned long long c;
163 c = clk_get_rate(&priv->per_clk);
165 do_div(c, 1000000000);
168 *prescale = *period_c / 0x10000 + 1;
170 *period_c /= *prescale;
171 c = *period_c * (unsigned long long)duty_ns;
172 do_div(c, period_ns);
176 * according to imx pwm RM, the real period value should be
177 * PERIOD value in PWMPR plus 2.
187 static int imx_pwm_set_invert(struct udevice *dev, uint channel,
190 struct imx_pwm_priv *priv = dev_get_priv(dev);
192 debug("%s: polarity=%u\n", __func__, polarity);
193 priv->invert = polarity;
198 static int imx_pwm_set_config(struct udevice *dev, uint channel,
199 uint period_ns, uint duty_ns)
201 struct imx_pwm_priv *priv = dev_get_priv(dev);
202 struct pwm_regs *regs = priv->regs;
203 unsigned long period_cycles, duty_cycles, prescale;
205 debug("%s: Config '%s' channel: %d\n", __func__, dev->name, channel);
207 pwm_dm_imx_get_parms(priv, period_ns, duty_ns, &period_cycles, &duty_cycles,
210 return pwm_config_internal(regs, period_cycles, duty_cycles, prescale);
213 static int imx_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
215 struct imx_pwm_priv *priv = dev_get_priv(dev);
216 struct pwm_regs *regs = priv->regs;
218 debug("%s: Enable '%s' state: %d\n", __func__, dev->name, enable);
221 setbits_le32(®s->cr, PWMCR_EN);
223 clrbits_le32(®s->cr, PWMCR_EN);
228 static int imx_pwm_of_to_plat(struct udevice *dev)
231 struct imx_pwm_priv *priv = dev_get_priv(dev);
233 priv->regs = dev_read_addr_ptr(dev);
235 ret = clk_get_by_name(dev, "per", &priv->per_clk);
237 printf("Failed to get per_clk\n");
241 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
243 printf("Failed to get ipg_clk\n");
250 static int imx_pwm_probe(struct udevice *dev)
253 struct imx_pwm_priv *priv = dev_get_priv(dev);
255 ret = clk_enable(&priv->per_clk);
257 printf("Failed to enable per_clk\n");
261 ret = clk_enable(&priv->ipg_clk);
263 printf("Failed to enable ipg_clk\n");
270 static const struct pwm_ops imx_pwm_ops = {
271 .set_invert = imx_pwm_set_invert,
272 .set_config = imx_pwm_set_config,
273 .set_enable = imx_pwm_set_enable,
276 static const struct udevice_id imx_pwm_ids[] = {
277 { .compatible = "fsl,imx27-pwm" },
281 U_BOOT_DRIVER(imx_pwm) = {
284 .of_match = imx_pwm_ids,
286 .of_to_plat = imx_pwm_of_to_plat,
287 .probe = imx_pwm_probe,
288 .priv_auto = sizeof(struct imx_pwm_priv),