drivers/pwm/pwm-img.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Imagination Technologies Pulse Width Modulator driver
   4  *
   5  * Copyright (c) 2014-2015, Imagination Technologies
   6  *
   7  * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/pwm.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22
  23 /* PWM registers */
  24 #define PWM_CTRL_CFG                            0x0000
  25 #define PWM_CTRL_CFG_NO_SUB_DIV                 0
  26 #define PWM_CTRL_CFG_SUB_DIV0                   1
  27 #define PWM_CTRL_CFG_SUB_DIV1                   2
  28 #define PWM_CTRL_CFG_SUB_DIV0_DIV1              3
  29 #define PWM_CTRL_CFG_DIV_SHIFT(ch)              ((ch) * 2 + 4)
  30 #define PWM_CTRL_CFG_DIV_MASK                   0x3
  31
  32 #define PWM_CH_CFG(ch)                          (0x4 + (ch) * 4)
  33 #define PWM_CH_CFG_TMBASE_SHIFT                 0
  34 #define PWM_CH_CFG_DUTY_SHIFT                   16
  35
  36 #define PERIP_PWM_PDM_CONTROL                   0x0140
  37 #define PERIP_PWM_PDM_CONTROL_CH_MASK           0x1
  38 #define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch)      ((ch) * 4)
  39
  40 #define IMG_PWM_PM_TIMEOUT                      1000 /* ms */
  41
  42 /*
  43  * PWM period is specified with a timebase register,
  44  * in number of step periods. The PWM duty cycle is also
  45  * specified in step periods, in the [0, $timebase] range.
  46  * In other words, the timebase imposes the duty cycle
  47  * resolution. Therefore, let's constraint the timebase to
  48  * a minimum value to allow a sane range of duty cycle values.
  49  * Imposing a minimum timebase, will impose a maximum PWM frequency.
  50  *
  51  * The value chosen is completely arbitrary.
  52  */
  53 #define MIN_TMBASE_STEPS                        16
  54
  55 #define IMG_PWM_NPWM                            4
  56
  57 struct img_pwm_soc_data {
  58         u32 max_timebase;
  59 };
  60
  61 struct img_pwm_chip {
  62         struct device   *dev;
  63         struct pwm_chip chip;
  64         struct clk      *pwm_clk;
  65         struct clk      *sys_clk;
  66         void __iomem    *base;
  67         struct regmap   *periph_regs;
  68         int             max_period_ns;
  69         int             min_period_ns;
  70         const struct img_pwm_soc_data   *data;
  71         u32             suspend_ctrl_cfg;
  72         u32             suspend_ch_cfg[IMG_PWM_NPWM];
  73 };
  74
  75 static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
  76 {
  77         return container_of(chip, struct img_pwm_chip, chip);
  78 }
  79
  80 static inline void img_pwm_writel(struct img_pwm_chip *imgchip,
  81                                   u32 reg, u32 val)
  82 {
  83         writel(val, imgchip->base + reg);
  84 }
  85
  86 static inline u32 img_pwm_readl(struct img_pwm_chip *imgchip, u32 reg)
  87 {
  88         return readl(imgchip->base + reg);
  89 }
  90
  91 static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  92                           int duty_ns, int period_ns)
  93 {
  94         u32 val, div, duty, timebase;
  95         unsigned long mul, output_clk_hz, input_clk_hz;
  96         struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
  97         unsigned int max_timebase = imgchip->data->max_timebase;
  98         int ret;
  99
 100         if (period_ns < imgchip->min_period_ns ||
 101             period_ns > imgchip->max_period_ns) {
 102                 dev_err(chip->dev, "configured period not in range\n");
 103                 return -ERANGE;
 104         }
 105
 106         input_clk_hz = clk_get_rate(imgchip->pwm_clk);
 107         output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
 108
 109         mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
 110         if (mul <= max_timebase) {
 111                 div = PWM_CTRL_CFG_NO_SUB_DIV;
 112                 timebase = DIV_ROUND_UP(mul, 1);
 113         } else if (mul <= max_timebase * 8) {
 114                 div = PWM_CTRL_CFG_SUB_DIV0;
 115                 timebase = DIV_ROUND_UP(mul, 8);
 116         } else if (mul <= max_timebase * 64) {
 117                 div = PWM_CTRL_CFG_SUB_DIV1;
 118                 timebase = DIV_ROUND_UP(mul, 64);
 119         } else if (mul <= max_timebase * 512) {
 120                 div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
 121                 timebase = DIV_ROUND_UP(mul, 512);
 122         } else {
 123                 dev_err(chip->dev,
 124                         "failed to configure timebase steps/divider value\n");
 125                 return -EINVAL;
 126         }
 127
 128         duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
 129
 130         ret = pm_runtime_resume_and_get(chip->dev);
 131         if (ret < 0)
 132                 return ret;
 133
 134         val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
 135         val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
 136         val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
 137                 PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
 138         img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
 139
 140         val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
 141               (timebase << PWM_CH_CFG_TMBASE_SHIFT);
 142         img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);
 143
 144         pm_runtime_mark_last_busy(chip->dev);
 145         pm_runtime_put_autosuspend(chip->dev);
 146
 147         return 0;
 148 }
 149
 150 static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 151 {
 152         u32 val;
 153         struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
 154         int ret;
 155
 156         ret = pm_runtime_resume_and_get(chip->dev);
 157         if (ret < 0)
 158                 return ret;
 159
 160         val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
 161         val |= BIT(pwm->hwpwm);
 162         img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
 163
 164         regmap_update_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
 165                            PERIP_PWM_PDM_CONTROL_CH_MASK <<
 166                            PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
 167
 168         return 0;
 169 }
 170
 171 static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 172 {
 173         u32 val;
 174         struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
 175
 176         val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
 177         val &= ~BIT(pwm->hwpwm);
 178         img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
 179
 180         pm_runtime_mark_last_busy(chip->dev);
 181         pm_runtime_put_autosuspend(chip->dev);
 182 }
 183
 184 static int img_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 185                          const struct pwm_state *state)
 186 {
 187         int err;
 188
 189         if (state->polarity != PWM_POLARITY_NORMAL)
 190                 return -EINVAL;
 191
 192         if (!state->enabled) {
 193                 if (pwm->state.enabled)
 194                         img_pwm_disable(chip, pwm);
 195
 196                 return 0;
 197         }
 198
 199         err = img_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
 200         if (err)
 201                 return err;
 202
 203         if (!pwm->state.enabled)
 204                 err = img_pwm_enable(chip, pwm);
 205
 206         return err;
 207 }
 208
 209 static const struct pwm_ops img_pwm_ops = {
 210         .apply = img_pwm_apply,
 211         .owner = THIS_MODULE,
 212 };
 213
 214 static const struct img_pwm_soc_data pistachio_pwm = {
 215         .max_timebase = 255,
 216 };
 217
 218 static const struct of_device_id img_pwm_of_match[] = {
 219         {
 220                 .compatible = "img,pistachio-pwm",
 221                 .data = &pistachio_pwm,
 222         },
 223         { }
 224 };
 225 MODULE_DEVICE_TABLE(of, img_pwm_of_match);
 226
 227 static int img_pwm_runtime_suspend(struct device *dev)
 228 {
 229         struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
 230
 231         clk_disable_unprepare(imgchip->pwm_clk);
 232         clk_disable_unprepare(imgchip->sys_clk);
 233
 234         return 0;
 235 }
 236
 237 static int img_pwm_runtime_resume(struct device *dev)
 238 {
 239         struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
 240         int ret;
 241
 242         ret = clk_prepare_enable(imgchip->sys_clk);
 243         if (ret < 0) {
 244                 dev_err(dev, "could not prepare or enable sys clock\n");
 245                 return ret;
 246         }
 247
 248         ret = clk_prepare_enable(imgchip->pwm_clk);
 249         if (ret < 0) {
 250                 dev_err(dev, "could not prepare or enable pwm clock\n");
 251                 clk_disable_unprepare(imgchip->sys_clk);
 252                 return ret;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int img_pwm_probe(struct platform_device *pdev)
 259 {
 260         int ret;
 261         u64 val;
 262         unsigned long clk_rate;
 263         struct img_pwm_chip *imgchip;
 264         const struct of_device_id *of_dev_id;
 265
 266         imgchip = devm_kzalloc(&pdev->dev, sizeof(*imgchip), GFP_KERNEL);
 267         if (!imgchip)
 268                 return -ENOMEM;
 269
 270         imgchip->dev = &pdev->dev;
 271
 272         imgchip->base = devm_platform_ioremap_resource(pdev, 0);
 273         if (IS_ERR(imgchip->base))
 274                 return PTR_ERR(imgchip->base);
 275
 276         of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
 277         if (!of_dev_id)
 278                 return -ENODEV;
 279         imgchip->data = of_dev_id->data;
 280
 281         imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 282                                                                "img,cr-periph");
 283         if (IS_ERR(imgchip->periph_regs))
 284                 return PTR_ERR(imgchip->periph_regs);
 285
 286         imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");
 287         if (IS_ERR(imgchip->sys_clk)) {
 288                 dev_err(&pdev->dev, "failed to get system clock\n");
 289                 return PTR_ERR(imgchip->sys_clk);
 290         }
 291
 292         imgchip->pwm_clk = devm_clk_get(&pdev->dev, "imgchip");
 293         if (IS_ERR(imgchip->pwm_clk)) {
 294                 dev_err(&pdev->dev, "failed to get imgchip clock\n");
 295                 return PTR_ERR(imgchip->pwm_clk);
 296         }
 297
 298         platform_set_drvdata(pdev, imgchip);
 299
 300         pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
 301         pm_runtime_use_autosuspend(&pdev->dev);
 302         pm_runtime_enable(&pdev->dev);
 303         if (!pm_runtime_enabled(&pdev->dev)) {
 304                 ret = img_pwm_runtime_resume(&pdev->dev);
 305                 if (ret)
 306                         goto err_pm_disable;
 307         }
 308
 309         clk_rate = clk_get_rate(imgchip->pwm_clk);
 310         if (!clk_rate) {
 311                 dev_err(&pdev->dev, "imgchip clock has no frequency\n");
 312                 ret = -EINVAL;
 313                 goto err_suspend;
 314         }
 315
 316         /* The maximum input clock divider is 512 */
 317         val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;
 318         do_div(val, clk_rate);
 319         imgchip->max_period_ns = val;
 320
 321         val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
 322         do_div(val, clk_rate);
 323         imgchip->min_period_ns = val;
 324
 325         imgchip->chip.dev = &pdev->dev;
 326         imgchip->chip.ops = &img_pwm_ops;
 327         imgchip->chip.npwm = IMG_PWM_NPWM;
 328
 329         ret = pwmchip_add(&imgchip->chip);
 330         if (ret < 0) {
 331                 dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
 332                 goto err_suspend;
 333         }
 334
 335         return 0;
 336
 337 err_suspend:
 338         if (!pm_runtime_enabled(&pdev->dev))
 339                 img_pwm_runtime_suspend(&pdev->dev);
 340 err_pm_disable:
 341         pm_runtime_disable(&pdev->dev);
 342         pm_runtime_dont_use_autosuspend(&pdev->dev);
 343         return ret;
 344 }
 345
 346 static int img_pwm_remove(struct platform_device *pdev)
 347 {
 348         struct img_pwm_chip *imgchip = platform_get_drvdata(pdev);
 349
 350         pm_runtime_disable(&pdev->dev);
 351         if (!pm_runtime_status_suspended(&pdev->dev))
 352                 img_pwm_runtime_suspend(&pdev->dev);
 353
 354         pwmchip_remove(&imgchip->chip);
 355
 356         return 0;
 357 }
 358
 359 #ifdef CONFIG_PM_SLEEP
 360 static int img_pwm_suspend(struct device *dev)
 361 {
 362         struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
 363         int i, ret;
 364
 365         if (pm_runtime_status_suspended(dev)) {
 366                 ret = img_pwm_runtime_resume(dev);
 367                 if (ret)
 368                         return ret;
 369         }
 370
 371         for (i = 0; i < imgchip->chip.npwm; i++)
 372                 imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,
 373                                                            PWM_CH_CFG(i));
 374
 375         imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);
 376
 377         img_pwm_runtime_suspend(dev);
 378
 379         return 0;
 380 }
 381
 382 static int img_pwm_resume(struct device *dev)
 383 {
 384         struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
 385         int ret;
 386         int i;
 387
 388         ret = img_pwm_runtime_resume(dev);
 389         if (ret)
 390                 return ret;
 391
 392         for (i = 0; i < imgchip->chip.npwm; i++)
 393                 img_pwm_writel(imgchip, PWM_CH_CFG(i),
 394                                imgchip->suspend_ch_cfg[i]);
 395
 396         img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);
 397
 398         for (i = 0; i < imgchip->chip.npwm; i++)
 399                 if (imgchip->suspend_ctrl_cfg & BIT(i))
 400                         regmap_update_bits(imgchip->periph_regs,
 401                                            PERIP_PWM_PDM_CONTROL,
 402                                            PERIP_PWM_PDM_CONTROL_CH_MASK <<
 403                                            PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
 404                                            0);
 405
 406         if (pm_runtime_status_suspended(dev))
 407                 img_pwm_runtime_suspend(dev);
 408
 409         return 0;
 410 }
 411 #endif /* CONFIG_PM */
 412
 413 static const struct dev_pm_ops img_pwm_pm_ops = {
 414         SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
 415                            img_pwm_runtime_resume,
 416                            NULL)
 417         SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
 418 };
 419
 420 static struct platform_driver img_pwm_driver = {
 421         .driver = {
 422                 .name = "img-pwm",
 423                 .pm = &img_pwm_pm_ops,
 424                 .of_match_table = img_pwm_of_match,
 425         },
 426         .probe = img_pwm_probe,
 427         .remove = img_pwm_remove,
 428 };
 429 module_platform_driver(img_pwm_driver);
 430
 431 MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
 432 MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
 433 MODULE_LICENSE("GPL v2");