drivers/pwm/pwm-hibvt.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * PWM Controller Driver for HiSilicon BVT SoCs
   4  *
   5  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pwm.h>
  16 #include <linux/reset.h>
  17
  18 #define PWM_CFG0_ADDR(x)    (((x) * 0x20) + 0x0)
  19 #define PWM_CFG1_ADDR(x)    (((x) * 0x20) + 0x4)
  20 #define PWM_CFG2_ADDR(x)    (((x) * 0x20) + 0x8)
  21 #define PWM_CTRL_ADDR(x)    (((x) * 0x20) + 0xC)
  22
  23 #define PWM_ENABLE_SHIFT    0
  24 #define PWM_ENABLE_MASK     BIT(0)
  25
  26 #define PWM_POLARITY_SHIFT  1
  27 #define PWM_POLARITY_MASK   BIT(1)
  28
  29 #define PWM_KEEP_SHIFT      2
  30 #define PWM_KEEP_MASK       BIT(2)
  31
  32 #define PWM_PERIOD_MASK     GENMASK(31, 0)
  33 #define PWM_DUTY_MASK       GENMASK(31, 0)
  34
  35 struct hibvt_pwm_chip {
  36         struct pwm_chip chip;
  37         struct clk *clk;
  38         void __iomem *base;
  39         struct reset_control *rstc;
  40         const struct hibvt_pwm_soc *soc;
  41 };
  42
  43 struct hibvt_pwm_soc {
  44         u32 num_pwms;
  45         bool quirk_force_enable;
  46 };
  47
  48 static const struct hibvt_pwm_soc hi3516cv300_soc_info = {
  49         .num_pwms = 4,
  50 };
  51
  52 static const struct hibvt_pwm_soc hi3519v100_soc_info = {
  53         .num_pwms = 8,
  54 };
  55
  56 static const struct hibvt_pwm_soc hi3559v100_shub_soc_info = {
  57         .num_pwms = 8,
  58         .quirk_force_enable = true,
  59 };
  60
  61 static const struct hibvt_pwm_soc hi3559v100_soc_info = {
  62         .num_pwms = 2,
  63         .quirk_force_enable = true,
  64 };
  65
  66 static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip)
  67 {
  68         return container_of(chip, struct hibvt_pwm_chip, chip);
  69 }
  70
  71 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,
  72                                         u32 mask, u32 data)
  73 {
  74         void __iomem *address = base + offset;
  75         u32 value;
  76
  77         value = readl(address);
  78         value &= ~mask;
  79         value |= (data & mask);
  80         writel(value, address);
  81 }
  82
  83 static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  84 {
  85         struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
  86
  87         hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
  88                         PWM_ENABLE_MASK, 0x1);
  89 }
  90
  91 static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  92 {
  93         struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
  94
  95         hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
  96                         PWM_ENABLE_MASK, 0x0);
  97 }
  98
  99 static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 100                                         int duty_cycle_ns, int period_ns)
 101 {
 102         struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
 103         u32 freq, period, duty;
 104
 105         freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
 106
 107         period = div_u64(freq * period_ns, 1000);
 108         duty = div_u64(period * duty_cycle_ns, period_ns);
 109
 110         hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
 111                         PWM_PERIOD_MASK, period);
 112
 113         hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
 114                         PWM_DUTY_MASK, duty);
 115 }
 116
 117 static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
 118                                         struct pwm_device *pwm,
 119                                         enum pwm_polarity polarity)
 120 {
 121         struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
 122
 123         if (polarity == PWM_POLARITY_INVERSED)
 124                 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
 125                                 PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT));
 126         else
 127                 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
 128                                 PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
 129 }
 130
 131 static int hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 132                                struct pwm_state *state)
 133 {
 134         struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
 135         void __iomem *base;
 136         u32 freq, value;
 137
 138         freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
 139         base = hi_pwm_chip->base;
 140
 141         value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
 142         state->period = div_u64(value * 1000, freq);
 143
 144         value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
 145         state->duty_cycle = div_u64(value * 1000, freq);
 146
 147         value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
 148         state->enabled = (PWM_ENABLE_MASK & value);
 149         state->polarity = (PWM_POLARITY_MASK & value) ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
 150
 151         return 0;
 152 }
 153
 154 static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 155                            const struct pwm_state *state)
 156 {
 157         struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
 158
 159         if (state->polarity != pwm->state.polarity)
 160                 hibvt_pwm_set_polarity(chip, pwm, state->polarity);
 161
 162         if (state->period != pwm->state.period ||
 163             state->duty_cycle != pwm->state.duty_cycle) {
 164                 hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
 165
 166                 /*
 167                  * Some implementations require the PWM to be enabled twice
 168                  * each time the duty cycle is refreshed.
 169                  */
 170                 if (hi_pwm_chip->soc->quirk_force_enable && state->enabled)
 171                         hibvt_pwm_enable(chip, pwm);
 172         }
 173
 174         if (state->enabled != pwm->state.enabled) {
 175                 if (state->enabled)
 176                         hibvt_pwm_enable(chip, pwm);
 177                 else
 178                         hibvt_pwm_disable(chip, pwm);
 179         }
 180
 181         return 0;
 182 }
 183
 184 static const struct pwm_ops hibvt_pwm_ops = {
 185         .get_state = hibvt_pwm_get_state,
 186         .apply = hibvt_pwm_apply,
 187
 188         .owner = THIS_MODULE,
 189 };
 190
 191 static int hibvt_pwm_probe(struct platform_device *pdev)
 192 {
 193         const struct hibvt_pwm_soc *soc =
 194                                 of_device_get_match_data(&pdev->dev);
 195         struct hibvt_pwm_chip *pwm_chip;
 196         int ret, i;
 197
 198         pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);
 199         if (pwm_chip == NULL)
 200                 return -ENOMEM;
 201
 202         pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);
 203         if (IS_ERR(pwm_chip->clk)) {
 204                 dev_err(&pdev->dev, "getting clock failed with %ld\n",
 205                                 PTR_ERR(pwm_chip->clk));
 206                 return PTR_ERR(pwm_chip->clk);
 207         }
 208
 209         pwm_chip->chip.ops = &hibvt_pwm_ops;
 210         pwm_chip->chip.dev = &pdev->dev;
 211         pwm_chip->chip.npwm = soc->num_pwms;
 212         pwm_chip->soc = soc;
 213
 214         pwm_chip->base = devm_platform_ioremap_resource(pdev, 0);
 215         if (IS_ERR(pwm_chip->base))
 216                 return PTR_ERR(pwm_chip->base);
 217
 218         ret = clk_prepare_enable(pwm_chip->clk);
 219         if (ret < 0)
 220                 return ret;
 221
 222         pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 223         if (IS_ERR(pwm_chip->rstc)) {
 224                 clk_disable_unprepare(pwm_chip->clk);
 225                 return PTR_ERR(pwm_chip->rstc);
 226         }
 227
 228         reset_control_assert(pwm_chip->rstc);
 229         msleep(30);
 230         reset_control_deassert(pwm_chip->rstc);
 231
 232         ret = pwmchip_add(&pwm_chip->chip);
 233         if (ret < 0) {
 234                 clk_disable_unprepare(pwm_chip->clk);
 235                 return ret;
 236         }
 237
 238         for (i = 0; i < pwm_chip->chip.npwm; i++) {
 239                 hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),
 240                                 PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT));
 241         }
 242
 243         platform_set_drvdata(pdev, pwm_chip);
 244
 245         return 0;
 246 }
 247
 248 static void hibvt_pwm_remove(struct platform_device *pdev)
 249 {
 250         struct hibvt_pwm_chip *pwm_chip;
 251
 252         pwm_chip = platform_get_drvdata(pdev);
 253
 254         pwmchip_remove(&pwm_chip->chip);
 255
 256         reset_control_assert(pwm_chip->rstc);
 257         msleep(30);
 258         reset_control_deassert(pwm_chip->rstc);
 259
 260         clk_disable_unprepare(pwm_chip->clk);
 261 }
 262
 263 static const struct of_device_id hibvt_pwm_of_match[] = {
 264         { .compatible = "hisilicon,hi3516cv300-pwm",
 265           .data = &hi3516cv300_soc_info },
 266         { .compatible = "hisilicon,hi3519v100-pwm",
 267           .data = &hi3519v100_soc_info },
 268         { .compatible = "hisilicon,hi3559v100-shub-pwm",
 269           .data = &hi3559v100_shub_soc_info },
 270         { .compatible = "hisilicon,hi3559v100-pwm",
 271           .data = &hi3559v100_soc_info },
 272         {  }
 273 };
 274 MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match);
 275
 276 static struct platform_driver hibvt_pwm_driver = {
 277         .driver = {
 278                 .name = "hibvt-pwm",
 279                 .of_match_table = hibvt_pwm_of_match,
 280         },
 281         .probe = hibvt_pwm_probe,
 282         .remove_new = hibvt_pwm_remove,
 283 };
 284 module_platform_driver(hibvt_pwm_driver);
 285
 286 MODULE_AUTHOR("Jian Yuan");
 287 MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
 288 MODULE_LICENSE("GPL");