drivers/pwm/pwm-atmel.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Atmel Pulse Width Modulation Controller
   4  *
   5  * Copyright (C) 2013 Atmel Corporation
   6  *               Bo Shen <voice.shen@atmel.com>
   7  *
   8  * Links to reference manuals for the supported PWM chips can be found in
   9  * Documentation/arm/microchip.rst.
  10  *
  11  * Limitations:
  12  * - Periods start with the inactive level.
  13  * - Hardware has to be stopped in general to update settings.
  14  *
  15  * Software bugs/possible improvements:
  16  * - When atmel_pwm_apply() is called with state->enabled=false a change in
  17  *   state->polarity isn't honored.
  18  * - Instead of sleeping to wait for a completed period, the interrupt
  19  *   functionality could be used.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/module.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pwm.h>
  31 #include <linux/slab.h>
  32
  33 /* The following is global registers for PWM controller */
  34 #define PWM_ENA                 0x04
  35 #define PWM_DIS                 0x08
  36 #define PWM_SR                  0x0C
  37 #define PWM_ISR                 0x1C
  38 /* Bit field in SR */
  39 #define PWM_SR_ALL_CH_ON        0x0F
  40
  41 /* The following register is PWM channel related registers */
  42 #define PWM_CH_REG_OFFSET       0x200
  43 #define PWM_CH_REG_SIZE         0x20
  44
  45 #define PWM_CMR                 0x0
  46 /* Bit field in CMR */
  47 #define PWM_CMR_CPOL            (1 << 9)
  48 #define PWM_CMR_UPD_CDTY        (1 << 10)
  49 #define PWM_CMR_CPRE_MSK        0xF
  50
  51 /* The following registers for PWM v1 */
  52 #define PWMV1_CDTY              0x04
  53 #define PWMV1_CPRD              0x08
  54 #define PWMV1_CUPD              0x10
  55
  56 /* The following registers for PWM v2 */
  57 #define PWMV2_CDTY              0x04
  58 #define PWMV2_CDTYUPD           0x08
  59 #define PWMV2_CPRD              0x0C
  60 #define PWMV2_CPRDUPD           0x10
  61
  62 #define PWM_MAX_PRES            10
  63
  64 struct atmel_pwm_registers {
  65         u8 period;
  66         u8 period_upd;
  67         u8 duty;
  68         u8 duty_upd;
  69 };
  70
  71 struct atmel_pwm_config {
  72         u32 period_bits;
  73 };
  74
  75 struct atmel_pwm_data {
  76         struct atmel_pwm_registers regs;
  77         struct atmel_pwm_config cfg;
  78 };
  79
  80 struct atmel_pwm_chip {
  81         struct pwm_chip chip;
  82         struct clk *clk;
  83         void __iomem *base;
  84         const struct atmel_pwm_data *data;
  85
  86         /*
  87          * The hardware supports a mechanism to update a channel's duty cycle at
  88          * the end of the currently running period. When such an update is
  89          * pending we delay disabling the PWM until the new configuration is
  90          * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
  91          * might not result in an inactive output.
  92          * This bitmask tracks for which channels an update is pending in
  93          * hardware.
  94          */
  95         u32 update_pending;
  96
  97         /* Protects .update_pending */
  98         spinlock_t lock;
  99 };
 100
 101 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
 102 {
 103         return container_of(chip, struct atmel_pwm_chip, chip);
 104 }
 105
 106 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
 107                                   unsigned long offset)
 108 {
 109         return readl_relaxed(chip->base + offset);
 110 }
 111
 112 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
 113                                     unsigned long offset, unsigned long val)
 114 {
 115         writel_relaxed(val, chip->base + offset);
 116 }
 117
 118 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
 119                                      unsigned int ch, unsigned long offset)
 120 {
 121         unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 122
 123         return atmel_pwm_readl(chip, base + offset);
 124 }
 125
 126 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
 127                                        unsigned int ch, unsigned long offset,
 128                                        unsigned long val)
 129 {
 130         unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 131
 132         atmel_pwm_writel(chip, base + offset, val);
 133 }
 134
 135 static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
 136 {
 137         /*
 138          * Each channel that has its bit in ISR set started a new period since
 139          * ISR was cleared and so there is no more update pending.  Note that
 140          * reading ISR clears it, so this needs to handle all channels to not
 141          * loose information.
 142          */
 143         u32 isr = atmel_pwm_readl(chip, PWM_ISR);
 144
 145         chip->update_pending &= ~isr;
 146 }
 147
 148 static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
 149 {
 150         spin_lock(&chip->lock);
 151
 152         /*
 153          * Clear pending flags in hardware because otherwise there might still
 154          * be a stale flag in ISR.
 155          */
 156         atmel_pwm_update_pending(chip);
 157
 158         chip->update_pending |= (1 << ch);
 159
 160         spin_unlock(&chip->lock);
 161 }
 162
 163 static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
 164 {
 165         int ret = 0;
 166
 167         spin_lock(&chip->lock);
 168
 169         if (chip->update_pending & (1 << ch)) {
 170                 atmel_pwm_update_pending(chip);
 171
 172                 if (chip->update_pending & (1 << ch))
 173                         ret = 1;
 174         }
 175
 176         spin_unlock(&chip->lock);
 177
 178         return ret;
 179 }
 180
 181 static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
 182 {
 183         unsigned long timeout = jiffies + 2 * HZ;
 184         int ret;
 185
 186         while ((ret = atmel_pwm_test_pending(chip, ch)) &&
 187                time_before(jiffies, timeout))
 188                 usleep_range(10, 100);
 189
 190         return ret ? -ETIMEDOUT : 0;
 191 }
 192
 193 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
 194                                              unsigned long clkrate,
 195                                              const struct pwm_state *state,
 196                                              unsigned long *cprd, u32 *pres)
 197 {
 198         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 199         unsigned long long cycles = state->period;
 200         int shift;
 201
 202         /* Calculate the period cycles and prescale value */
 203         cycles *= clkrate;
 204         do_div(cycles, NSEC_PER_SEC);
 205
 206         /*
 207          * The register for the period length is cfg.period_bits bits wide.
 208          * So for each bit the number of clock cycles is wider divide the input
 209          * clock frequency by two using pres and shift cprd accordingly.
 210          */
 211         shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
 212
 213         if (shift > PWM_MAX_PRES) {
 214                 dev_err(chip->dev, "pres exceeds the maximum value\n");
 215                 return -EINVAL;
 216         } else if (shift > 0) {
 217                 *pres = shift;
 218                 cycles >>= *pres;
 219         } else {
 220                 *pres = 0;
 221         }
 222
 223         *cprd = cycles;
 224
 225         return 0;
 226 }
 227
 228 static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
 229                                      unsigned long clkrate, unsigned long cprd,
 230                                      u32 pres, unsigned long *cdty)
 231 {
 232         unsigned long long cycles = state->duty_cycle;
 233
 234         cycles *= clkrate;
 235         do_div(cycles, NSEC_PER_SEC);
 236         cycles >>= pres;
 237         *cdty = cprd - cycles;
 238 }
 239
 240 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
 241                                   unsigned long cdty)
 242 {
 243         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 244         u32 val;
 245
 246         if (atmel_pwm->data->regs.duty_upd ==
 247             atmel_pwm->data->regs.period_upd) {
 248                 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 249                 val &= ~PWM_CMR_UPD_CDTY;
 250                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 251         }
 252
 253         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 254                             atmel_pwm->data->regs.duty_upd, cdty);
 255         atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
 256 }
 257
 258 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
 259                                     struct pwm_device *pwm,
 260                                     unsigned long cprd, unsigned long cdty)
 261 {
 262         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 263
 264         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 265                             atmel_pwm->data->regs.duty, cdty);
 266         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 267                             atmel_pwm->data->regs.period, cprd);
 268 }
 269
 270 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
 271                               bool disable_clk)
 272 {
 273         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 274         unsigned long timeout;
 275
 276         atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
 277
 278         atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
 279
 280         /*
 281          * Wait for the PWM channel disable operation to be effective before
 282          * stopping the clock.
 283          */
 284         timeout = jiffies + 2 * HZ;
 285
 286         while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
 287                time_before(jiffies, timeout))
 288                 usleep_range(10, 100);
 289
 290         if (disable_clk)
 291                 clk_disable(atmel_pwm->clk);
 292 }
 293
 294 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 295                            const struct pwm_state *state)
 296 {
 297         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 298         struct pwm_state cstate;
 299         unsigned long cprd, cdty;
 300         u32 pres, val;
 301         int ret;
 302
 303         pwm_get_state(pwm, &cstate);
 304
 305         if (state->enabled) {
 306                 unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
 307
 308                 if (cstate.enabled &&
 309                     cstate.polarity == state->polarity &&
 310                     cstate.period == state->period) {
 311                         u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 312
 313                         cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
 314                                                   atmel_pwm->data->regs.period);
 315                         pres = cmr & PWM_CMR_CPRE_MSK;
 316
 317                         atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
 318                         atmel_pwm_update_cdty(chip, pwm, cdty);
 319                         return 0;
 320                 }
 321
 322                 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
 323                                                         &pres);
 324                 if (ret) {
 325                         dev_err(chip->dev,
 326                                 "failed to calculate cprd and prescaler\n");
 327                         return ret;
 328                 }
 329
 330                 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
 331
 332                 if (cstate.enabled) {
 333                         atmel_pwm_disable(chip, pwm, false);
 334                 } else {
 335                         ret = clk_enable(atmel_pwm->clk);
 336                         if (ret) {
 337                                 dev_err(chip->dev, "failed to enable clock\n");
 338                                 return ret;
 339                         }
 340                 }
 341
 342                 /* It is necessary to preserve CPOL, inside CMR */
 343                 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 344                 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
 345                 if (state->polarity == PWM_POLARITY_NORMAL)
 346                         val &= ~PWM_CMR_CPOL;
 347                 else
 348                         val |= PWM_CMR_CPOL;
 349                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 350                 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
 351                 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
 352         } else if (cstate.enabled) {
 353                 atmel_pwm_disable(chip, pwm, true);
 354         }
 355
 356         return 0;
 357 }
 358
 359 static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 360                                 struct pwm_state *state)
 361 {
 362         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 363         u32 sr, cmr;
 364
 365         sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
 366         cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 367
 368         if (sr & (1 << pwm->hwpwm)) {
 369                 unsigned long rate = clk_get_rate(atmel_pwm->clk);
 370                 u32 cdty, cprd, pres;
 371                 u64 tmp;
 372
 373                 pres = cmr & PWM_CMR_CPRE_MSK;
 374
 375                 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
 376                                           atmel_pwm->data->regs.period);
 377                 tmp = (u64)cprd * NSEC_PER_SEC;
 378                 tmp <<= pres;
 379                 state->period = DIV64_U64_ROUND_UP(tmp, rate);
 380
 381                 /* Wait for an updated duty_cycle queued in hardware */
 382                 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
 383
 384                 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
 385                                           atmel_pwm->data->regs.duty);
 386                 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
 387                 tmp <<= pres;
 388                 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
 389
 390                 state->enabled = true;
 391         } else {
 392                 state->enabled = false;
 393         }
 394
 395         if (cmr & PWM_CMR_CPOL)
 396                 state->polarity = PWM_POLARITY_INVERSED;
 397         else
 398                 state->polarity = PWM_POLARITY_NORMAL;
 399 }
 400
 401 static const struct pwm_ops atmel_pwm_ops = {
 402         .apply = atmel_pwm_apply,
 403         .get_state = atmel_pwm_get_state,
 404         .owner = THIS_MODULE,
 405 };
 406
 407 static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
 408         .regs = {
 409                 .period         = PWMV1_CPRD,
 410                 .period_upd     = PWMV1_CUPD,
 411                 .duty           = PWMV1_CDTY,
 412                 .duty_upd       = PWMV1_CUPD,
 413         },
 414         .cfg = {
 415                 /* 16 bits to keep period and duty. */
 416                 .period_bits    = 16,
 417         },
 418 };
 419
 420 static const struct atmel_pwm_data atmel_sama5_pwm_data = {
 421         .regs = {
 422                 .period         = PWMV2_CPRD,
 423                 .period_upd     = PWMV2_CPRDUPD,
 424                 .duty           = PWMV2_CDTY,
 425                 .duty_upd       = PWMV2_CDTYUPD,
 426         },
 427         .cfg = {
 428                 /* 16 bits to keep period and duty. */
 429                 .period_bits    = 16,
 430         },
 431 };
 432
 433 static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
 434         .regs = {
 435                 .period         = PWMV1_CPRD,
 436                 .period_upd     = PWMV1_CUPD,
 437                 .duty           = PWMV1_CDTY,
 438                 .duty_upd       = PWMV1_CUPD,
 439         },
 440         .cfg = {
 441                 /* 32 bits to keep period and duty. */
 442                 .period_bits    = 32,
 443         },
 444 };
 445
 446 static const struct of_device_id atmel_pwm_dt_ids[] = {
 447         {
 448                 .compatible = "atmel,at91sam9rl-pwm",
 449                 .data = &atmel_sam9rl_pwm_data,
 450         }, {
 451                 .compatible = "atmel,sama5d3-pwm",
 452                 .data = &atmel_sama5_pwm_data,
 453         }, {
 454                 .compatible = "atmel,sama5d2-pwm",
 455                 .data = &atmel_sama5_pwm_data,
 456         }, {
 457                 .compatible = "microchip,sam9x60-pwm",
 458                 .data = &mchp_sam9x60_pwm_data,
 459         }, {
 460                 /* sentinel */
 461         },
 462 };
 463 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
 464
 465 static int atmel_pwm_probe(struct platform_device *pdev)
 466 {
 467         struct atmel_pwm_chip *atmel_pwm;
 468         int ret;
 469
 470         atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
 471         if (!atmel_pwm)
 472                 return -ENOMEM;
 473
 474         atmel_pwm->data = of_device_get_match_data(&pdev->dev);
 475
 476         atmel_pwm->update_pending = 0;
 477         spin_lock_init(&atmel_pwm->lock);
 478
 479         atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
 480         if (IS_ERR(atmel_pwm->base))
 481                 return PTR_ERR(atmel_pwm->base);
 482
 483         atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
 484         if (IS_ERR(atmel_pwm->clk))
 485                 return PTR_ERR(atmel_pwm->clk);
 486
 487         ret = clk_prepare(atmel_pwm->clk);
 488         if (ret) {
 489                 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
 490                 return ret;
 491         }
 492
 493         atmel_pwm->chip.dev = &pdev->dev;
 494         atmel_pwm->chip.ops = &atmel_pwm_ops;
 495         atmel_pwm->chip.npwm = 4;
 496
 497         ret = pwmchip_add(&atmel_pwm->chip);
 498         if (ret < 0) {
 499                 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
 500                 goto unprepare_clk;
 501         }
 502
 503         platform_set_drvdata(pdev, atmel_pwm);
 504
 505         return ret;
 506
 507 unprepare_clk:
 508         clk_unprepare(atmel_pwm->clk);
 509         return ret;
 510 }
 511
 512 static int atmel_pwm_remove(struct platform_device *pdev)
 513 {
 514         struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
 515
 516         pwmchip_remove(&atmel_pwm->chip);
 517
 518         clk_unprepare(atmel_pwm->clk);
 519
 520         return 0;
 521 }
 522
 523 static struct platform_driver atmel_pwm_driver = {
 524         .driver = {
 525                 .name = "atmel-pwm",
 526                 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
 527         },
 528         .probe = atmel_pwm_probe,
 529         .remove = atmel_pwm_remove,
 530 };
 531 module_platform_driver(atmel_pwm_driver);
 532
 533 MODULE_ALIAS("platform:atmel-pwm");
 534 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
 535 MODULE_DESCRIPTION("Atmel PWM driver");
 536 MODULE_LICENSE("GPL v2");