drivers/pwm/pwm-atmel-tcb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) Overkiz SAS 2012
   4  *
   5  * Author: Boris BREZILLON <b.brezillon@overkiz.com>
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/ioport.h>
  18 #include <linux/io.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pwm.h>
  22 #include <linux/of.h>
  23 #include <linux/regmap.h>
  24 #include <linux/slab.h>
  25 #include <soc/at91/atmel_tcb.h>
  26
  27 #define NPWM    2
  28
  29 #define ATMEL_TC_ACMR_MASK      (ATMEL_TC_ACPA | ATMEL_TC_ACPC |        \
  30                                  ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
  31
  32 #define ATMEL_TC_BCMR_MASK      (ATMEL_TC_BCPB | ATMEL_TC_BCPC |        \
  33                                  ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
  34
  35 struct atmel_tcb_pwm_device {
  36         enum pwm_polarity polarity;     /* PWM polarity */
  37         unsigned div;                   /* PWM clock divider */
  38         unsigned duty;                  /* PWM duty expressed in clk cycles */
  39         unsigned period;                /* PWM period expressed in clk cycles */
  40 };
  41
  42 struct atmel_tcb_channel {
  43         u32 enabled;
  44         u32 cmr;
  45         u32 ra;
  46         u32 rb;
  47         u32 rc;
  48 };
  49
  50 struct atmel_tcb_pwm_chip {
  51         struct pwm_chip chip;
  52         spinlock_t lock;
  53         u8 channel;
  54         u8 width;
  55         struct regmap *regmap;
  56         struct clk *clk;
  57         struct clk *gclk;
  58         struct clk *slow_clk;
  59         struct atmel_tcb_pwm_device pwms[NPWM];
  60         struct atmel_tcb_channel bkup;
  61 };
  62
  63 static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
  64
  65 static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
  66 {
  67         return container_of(chip, struct atmel_tcb_pwm_chip, chip);
  68 }
  69
  70 static int atmel_tcb_pwm_request(struct pwm_chip *chip,
  71                                  struct pwm_device *pwm)
  72 {
  73         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
  74         struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
  75         unsigned cmr;
  76         int ret;
  77
  78         ret = clk_prepare_enable(tcbpwmc->clk);
  79         if (ret)
  80                 return ret;
  81
  82         tcbpwm->polarity = PWM_POLARITY_NORMAL;
  83         tcbpwm->duty = 0;
  84         tcbpwm->period = 0;
  85         tcbpwm->div = 0;
  86
  87         spin_lock(&tcbpwmc->lock);
  88         regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
  89         /*
  90          * Get init config from Timer Counter registers if
  91          * Timer Counter is already configured as a PWM generator.
  92          */
  93         if (cmr & ATMEL_TC_WAVE) {
  94                 if (pwm->hwpwm == 0)
  95                         regmap_read(tcbpwmc->regmap,
  96                                     ATMEL_TC_REG(tcbpwmc->channel, RA),
  97                                     &tcbpwm->duty);
  98                 else
  99                         regmap_read(tcbpwmc->regmap,
 100                                     ATMEL_TC_REG(tcbpwmc->channel, RB),
 101                                     &tcbpwm->duty);
 102
 103                 tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
 104                 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
 105                             &tcbpwm->period);
 106                 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
 107                         ATMEL_TC_BCMR_MASK);
 108         } else
 109                 cmr = 0;
 110
 111         cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
 112         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
 113         spin_unlock(&tcbpwmc->lock);
 114
 115         return 0;
 116 }
 117
 118 static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 119 {
 120         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 121
 122         clk_disable_unprepare(tcbpwmc->clk);
 123 }
 124
 125 static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 126 {
 127         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 128         struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
 129         unsigned cmr;
 130         enum pwm_polarity polarity = tcbpwm->polarity;
 131
 132         /*
 133          * If duty is 0 the timer will be stopped and we have to
 134          * configure the output correctly on software trigger:
 135          *  - set output to high if PWM_POLARITY_INVERSED
 136          *  - set output to low if PWM_POLARITY_NORMAL
 137          *
 138          * This is why we're reverting polarity in this case.
 139          */
 140         if (tcbpwm->duty == 0)
 141                 polarity = !polarity;
 142
 143         spin_lock(&tcbpwmc->lock);
 144         regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
 145
 146         /* flush old setting and set the new one */
 147         if (pwm->hwpwm == 0) {
 148                 cmr &= ~ATMEL_TC_ACMR_MASK;
 149                 if (polarity == PWM_POLARITY_INVERSED)
 150                         cmr |= ATMEL_TC_ASWTRG_CLEAR;
 151                 else
 152                         cmr |= ATMEL_TC_ASWTRG_SET;
 153         } else {
 154                 cmr &= ~ATMEL_TC_BCMR_MASK;
 155                 if (polarity == PWM_POLARITY_INVERSED)
 156                         cmr |= ATMEL_TC_BSWTRG_CLEAR;
 157                 else
 158                         cmr |= ATMEL_TC_BSWTRG_SET;
 159         }
 160
 161         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
 162
 163         /*
 164          * Use software trigger to apply the new setting.
 165          * If both PWM devices in this group are disabled we stop the clock.
 166          */
 167         if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
 168                 regmap_write(tcbpwmc->regmap,
 169                              ATMEL_TC_REG(tcbpwmc->channel, CCR),
 170                              ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
 171                 tcbpwmc->bkup.enabled = 1;
 172         } else {
 173                 regmap_write(tcbpwmc->regmap,
 174                              ATMEL_TC_REG(tcbpwmc->channel, CCR),
 175                              ATMEL_TC_SWTRG);
 176                 tcbpwmc->bkup.enabled = 0;
 177         }
 178
 179         spin_unlock(&tcbpwmc->lock);
 180 }
 181
 182 static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 183 {
 184         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 185         struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
 186         u32 cmr;
 187         enum pwm_polarity polarity = tcbpwm->polarity;
 188
 189         /*
 190          * If duty is 0 the timer will be stopped and we have to
 191          * configure the output correctly on software trigger:
 192          *  - set output to high if PWM_POLARITY_INVERSED
 193          *  - set output to low if PWM_POLARITY_NORMAL
 194          *
 195          * This is why we're reverting polarity in this case.
 196          */
 197         if (tcbpwm->duty == 0)
 198                 polarity = !polarity;
 199
 200         spin_lock(&tcbpwmc->lock);
 201         regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
 202
 203         /* flush old setting and set the new one */
 204         cmr &= ~ATMEL_TC_TCCLKS;
 205
 206         if (pwm->hwpwm == 0) {
 207                 cmr &= ~ATMEL_TC_ACMR_MASK;
 208
 209                 /* Set CMR flags according to given polarity */
 210                 if (polarity == PWM_POLARITY_INVERSED)
 211                         cmr |= ATMEL_TC_ASWTRG_CLEAR;
 212                 else
 213                         cmr |= ATMEL_TC_ASWTRG_SET;
 214         } else {
 215                 cmr &= ~ATMEL_TC_BCMR_MASK;
 216                 if (polarity == PWM_POLARITY_INVERSED)
 217                         cmr |= ATMEL_TC_BSWTRG_CLEAR;
 218                 else
 219                         cmr |= ATMEL_TC_BSWTRG_SET;
 220         }
 221
 222         /*
 223          * If duty is 0 or equal to period there's no need to register
 224          * a specific action on RA/RB and RC compare.
 225          * The output will be configured on software trigger and keep
 226          * this config till next config call.
 227          */
 228         if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
 229                 if (pwm->hwpwm == 0) {
 230                         if (polarity == PWM_POLARITY_INVERSED)
 231                                 cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
 232                         else
 233                                 cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
 234                 } else {
 235                         if (polarity == PWM_POLARITY_INVERSED)
 236                                 cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
 237                         else
 238                                 cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
 239                 }
 240         }
 241
 242         cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
 243
 244         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
 245
 246         if (pwm->hwpwm == 0)
 247                 regmap_write(tcbpwmc->regmap,
 248                              ATMEL_TC_REG(tcbpwmc->channel, RA),
 249                              tcbpwm->duty);
 250         else
 251                 regmap_write(tcbpwmc->regmap,
 252                              ATMEL_TC_REG(tcbpwmc->channel, RB),
 253                              tcbpwm->duty);
 254
 255         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
 256                      tcbpwm->period);
 257
 258         /* Use software trigger to apply the new setting */
 259         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
 260                      ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
 261         tcbpwmc->bkup.enabled = 1;
 262         spin_unlock(&tcbpwmc->lock);
 263         return 0;
 264 }
 265
 266 static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 267                                 int duty_ns, int period_ns)
 268 {
 269         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 270         struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
 271         struct atmel_tcb_pwm_device *atcbpwm = NULL;
 272         int i = 0;
 273         int slowclk = 0;
 274         unsigned period;
 275         unsigned duty;
 276         unsigned rate = clk_get_rate(tcbpwmc->clk);
 277         unsigned long long min;
 278         unsigned long long max;
 279
 280         /*
 281          * Find best clk divisor:
 282          * the smallest divisor which can fulfill the period_ns requirements.
 283          * If there is a gclk, the first divisor is actually the gclk selector
 284          */
 285         if (tcbpwmc->gclk)
 286                 i = 1;
 287         for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
 288                 if (atmel_tcb_divisors[i] == 0) {
 289                         slowclk = i;
 290                         continue;
 291                 }
 292                 min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
 293                 max = min << tcbpwmc->width;
 294                 if (max >= period_ns)
 295                         break;
 296         }
 297
 298         /*
 299          * If none of the divisor are small enough to represent period_ns
 300          * take slow clock (32KHz).
 301          */
 302         if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
 303                 i = slowclk;
 304                 rate = clk_get_rate(tcbpwmc->slow_clk);
 305                 min = div_u64(NSEC_PER_SEC, rate);
 306                 max = min << tcbpwmc->width;
 307
 308                 /* If period is too big return ERANGE error */
 309                 if (max < period_ns)
 310                         return -ERANGE;
 311         }
 312
 313         duty = div_u64(duty_ns, min);
 314         period = div_u64(period_ns, min);
 315
 316         if (pwm->hwpwm == 0)
 317                 atcbpwm = &tcbpwmc->pwms[1];
 318         else
 319                 atcbpwm = &tcbpwmc->pwms[0];
 320
 321         /*
 322          * PWM devices provided by the TCB driver are grouped by 2.
 323          * PWM devices in a given group must be configured with the
 324          * same period_ns.
 325          *
 326          * We're checking the period value of the second PWM device
 327          * in this group before applying the new config.
 328          */
 329         if ((atcbpwm && atcbpwm->duty > 0 &&
 330                         atcbpwm->duty != atcbpwm->period) &&
 331                 (atcbpwm->div != i || atcbpwm->period != period)) {
 332                 dev_err(chip->dev,
 333                         "failed to configure period_ns: PWM group already configured with a different value\n");
 334                 return -EINVAL;
 335         }
 336
 337         tcbpwm->period = period;
 338         tcbpwm->div = i;
 339         tcbpwm->duty = duty;
 340
 341         return 0;
 342 }
 343
 344 static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 345                                const struct pwm_state *state)
 346 {
 347         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 348         struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
 349         int duty_cycle, period;
 350         int ret;
 351
 352         tcbpwm->polarity = state->polarity;
 353
 354         if (!state->enabled) {
 355                 atmel_tcb_pwm_disable(chip, pwm);
 356                 return 0;
 357         }
 358
 359         period = state->period < INT_MAX ? state->period : INT_MAX;
 360         duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
 361
 362         ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
 363         if (ret)
 364                 return ret;
 365
 366         return atmel_tcb_pwm_enable(chip, pwm);
 367 }
 368
 369 static const struct pwm_ops atmel_tcb_pwm_ops = {
 370         .request = atmel_tcb_pwm_request,
 371         .free = atmel_tcb_pwm_free,
 372         .apply = atmel_tcb_pwm_apply,
 373         .owner = THIS_MODULE,
 374 };
 375
 376 static struct atmel_tcb_config tcb_rm9200_config = {
 377         .counter_width = 16,
 378 };
 379
 380 static struct atmel_tcb_config tcb_sam9x5_config = {
 381         .counter_width = 32,
 382 };
 383
 384 static struct atmel_tcb_config tcb_sama5d2_config = {
 385         .counter_width = 32,
 386         .has_gclk = 1,
 387 };
 388
 389 static const struct of_device_id atmel_tcb_of_match[] = {
 390         { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
 391         { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
 392         { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
 393         { /* sentinel */ }
 394 };
 395
 396 static int atmel_tcb_pwm_probe(struct platform_device *pdev)
 397 {
 398         const struct of_device_id *match;
 399         struct atmel_tcb_pwm_chip *tcbpwm;
 400         const struct atmel_tcb_config *config;
 401         struct device_node *np = pdev->dev.of_node;
 402         char clk_name[] = "t0_clk";
 403         int err;
 404         int channel;
 405
 406         tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
 407         if (tcbpwm == NULL)
 408                 return -ENOMEM;
 409
 410         err = of_property_read_u32(np, "reg", &channel);
 411         if (err < 0) {
 412                 dev_err(&pdev->dev,
 413                         "failed to get Timer Counter Block channel from device tree (error: %d)\n",
 414                         err);
 415                 return err;
 416         }
 417
 418         tcbpwm->regmap = syscon_node_to_regmap(np->parent);
 419         if (IS_ERR(tcbpwm->regmap))
 420                 return PTR_ERR(tcbpwm->regmap);
 421
 422         tcbpwm->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
 423         if (IS_ERR(tcbpwm->slow_clk))
 424                 return PTR_ERR(tcbpwm->slow_clk);
 425
 426         clk_name[1] += channel;
 427         tcbpwm->clk = of_clk_get_by_name(np->parent, clk_name);
 428         if (IS_ERR(tcbpwm->clk))
 429                 tcbpwm->clk = of_clk_get_by_name(np->parent, "t0_clk");
 430         if (IS_ERR(tcbpwm->clk)) {
 431                 err = PTR_ERR(tcbpwm->clk);
 432                 goto err_slow_clk;
 433         }
 434
 435         match = of_match_node(atmel_tcb_of_match, np->parent);
 436         config = match->data;
 437
 438         if (config->has_gclk) {
 439                 tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk");
 440                 if (IS_ERR(tcbpwm->gclk)) {
 441                         err = PTR_ERR(tcbpwm->gclk);
 442                         goto err_clk;
 443                 }
 444         }
 445
 446         tcbpwm->chip.dev = &pdev->dev;
 447         tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
 448         tcbpwm->chip.npwm = NPWM;
 449         tcbpwm->channel = channel;
 450         tcbpwm->width = config->counter_width;
 451
 452         err = clk_prepare_enable(tcbpwm->slow_clk);
 453         if (err)
 454                 goto err_gclk;
 455
 456         spin_lock_init(&tcbpwm->lock);
 457
 458         err = pwmchip_add(&tcbpwm->chip);
 459         if (err < 0)
 460                 goto err_disable_clk;
 461
 462         platform_set_drvdata(pdev, tcbpwm);
 463
 464         return 0;
 465
 466 err_disable_clk:
 467         clk_disable_unprepare(tcbpwm->slow_clk);
 468
 469 err_gclk:
 470         clk_put(tcbpwm->gclk);
 471
 472 err_clk:
 473         clk_put(tcbpwm->clk);
 474
 475 err_slow_clk:
 476         clk_put(tcbpwm->slow_clk);
 477
 478         return err;
 479 }
 480
 481 static void atmel_tcb_pwm_remove(struct platform_device *pdev)
 482 {
 483         struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
 484
 485         pwmchip_remove(&tcbpwm->chip);
 486
 487         clk_disable_unprepare(tcbpwm->slow_clk);
 488         clk_put(tcbpwm->gclk);
 489         clk_put(tcbpwm->clk);
 490         clk_put(tcbpwm->slow_clk);
 491 }
 492
 493 static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
 494         { .compatible = "atmel,tcb-pwm", },
 495         { /* sentinel */ }
 496 };
 497 MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
 498
 499 #ifdef CONFIG_PM_SLEEP
 500 static int atmel_tcb_pwm_suspend(struct device *dev)
 501 {
 502         struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
 503         struct atmel_tcb_channel *chan = &tcbpwm->bkup;
 504         unsigned int channel = tcbpwm->channel;
 505
 506         regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
 507         regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
 508         regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
 509         regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
 510
 511         return 0;
 512 }
 513
 514 static int atmel_tcb_pwm_resume(struct device *dev)
 515 {
 516         struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
 517         struct atmel_tcb_channel *chan = &tcbpwm->bkup;
 518         unsigned int channel = tcbpwm->channel;
 519
 520         regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
 521         regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
 522         regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
 523         regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
 524
 525         if (chan->enabled)
 526                 regmap_write(tcbpwm->regmap,
 527                              ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 528                              ATMEL_TC_REG(channel, CCR));
 529
 530         return 0;
 531 }
 532 #endif
 533
 534 static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
 535                          atmel_tcb_pwm_resume);
 536
 537 static struct platform_driver atmel_tcb_pwm_driver = {
 538         .driver = {
 539                 .name = "atmel-tcb-pwm",
 540                 .of_match_table = atmel_tcb_pwm_dt_ids,
 541                 .pm = &atmel_tcb_pwm_pm_ops,
 542         },
 543         .probe = atmel_tcb_pwm_probe,
 544         .remove_new = atmel_tcb_pwm_remove,
 545 };
 546 module_platform_driver(atmel_tcb_pwm_driver);
 547
 548 MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
 549 MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
 550 MODULE_LICENSE("GPL v2");