1 // SPDX-License-Identifier: GPL-2.0+
3 * PWM support for Microchip AT91 architectures.
5 * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries
7 * Author: Dan Sneddon <daniel.sneddon@microchip.com>
9 * Based on drivers/pwm/pwm-atmel.c from Linux.
15 #include <linux/bitops.h>
19 #define PERIOD_BITS 16
20 #define PWM_MAX_PRES 10
21 #define NSEC_PER_SEC 1000000000L
24 #define PWM_CHANNEL_OFFSET 0x20
26 #define PWM_CMR_CPRE_MSK GENMASK(3, 0)
27 #define PWM_CMR_CPOL BIT(9)
28 #define PWM_CDTY 0x204
29 #define PWM_CPRD 0x20C
31 struct at91_pwm_priv {
37 static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev,
38 unsigned long clkrate,
39 uint period_ns, uint duty_ns,
40 unsigned long *cprd, u32 *pres)
42 u64 cycles = period_ns;
45 /* Calculate the period cycles and prescale value */
47 do_div(cycles, NSEC_PER_SEC);
50 * The register for the period length is period_bits bits wide.
51 * So for each bit the number of clock cycles is wider divide the input
52 * clock frequency by two using pres and shift cprd accordingly.
54 shift = fls(cycles) - PERIOD_BITS;
56 if (shift > PWM_MAX_PRES) {
58 } else if (shift > 0) {
70 static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns,
71 unsigned long clkrate, unsigned long cprd,
72 u32 pres, unsigned long *cdty)
77 do_div(cycles, NSEC_PER_SEC);
79 *cdty = cprd - cycles;
83 * Returns: channel status after set operation
85 static bool at91_pwm_set(void __iomem *base, uint channel, bool enable)
89 val = ioread32(base + PWM_ENA);
90 cur_status = !!(val & BIT(channel));
92 /* if channel is already in that state, do nothing */
93 if (!(enable ^ cur_status))
99 val &= ~(BIT(channel));
101 iowrite32(val, base + PWM_ENA);
106 static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
108 struct at91_pwm_priv *priv = dev_get_priv(dev);
110 at91_pwm_set(priv->base, channel, enable);
115 static int at91_pwm_set_config(struct udevice *dev, uint channel,
116 uint period_ns, uint duty_ns)
118 struct at91_pwm_priv *priv = dev_get_priv(dev);
119 unsigned long cprd, cdty;
124 ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns,
125 duty_ns, &cprd, &pres);
129 at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty);
131 /* disable the channel */
132 channel_enabled = at91_pwm_set(priv->base, channel, false);
134 /* It is necessary to preserve CPOL, inside CMR */
135 val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
136 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
137 iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
139 iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD);
141 iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY);
143 /* renable the channel if needed */
145 at91_pwm_set(priv->base, channel, true);
150 static int at91_pwm_set_invert(struct udevice *dev, uint channel,
153 struct at91_pwm_priv *priv = dev_get_priv(dev);
156 val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
160 val &= ~PWM_CMR_CPOL;
161 iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
166 static int at91_pwm_probe(struct udevice *dev)
168 struct at91_pwm_priv *priv = dev_get_priv(dev);
171 priv->base = dev_read_addr_ptr(dev);
175 ret = clk_get_by_index(dev, 0, &priv->pclk);
179 /* clocks aren't ref-counted so just enabled them once here */
180 ret = clk_enable(&priv->pclk);
184 priv->clkrate = clk_get_rate(&priv->pclk);
189 static const struct pwm_ops at91_pwm_ops = {
190 .set_config = at91_pwm_set_config,
191 .set_enable = at91_pwm_set_enable,
192 .set_invert = at91_pwm_set_invert,
195 static const struct udevice_id at91_pwm_of_match[] = {
196 { .compatible = "atmel,sama5d2-pwm" },
200 U_BOOT_DRIVER(at91_pwm) = {
203 .of_match = at91_pwm_of_match,
204 .probe = at91_pwm_probe,
205 .priv_auto = sizeof(struct at91_pwm_priv),
206 .ops = &at91_pwm_ops,