drivers/pwm/pwm-apple.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Driver for the Apple SoC PWM controller
   4  *
   5  * Copyright The Asahi Linux Contributors
   6  *
   7  * Limitations:
   8  * - The writes to cycle registers are shadowed until a write to
   9  *   the control register.
  10  * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output
  11  *   is a constant off signal.
  12  * - When APPLE_PWM_CTRL is set to 0, the output is constant low
  13  */
  14
  15 #include <linux/mod_devicetable.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/io.h>
  20 #include <linux/clk.h>
  21 #include <linux/math64.h>
  22
  23 #define APPLE_PWM_CTRL        0x00
  24 #define APPLE_PWM_ON_CYCLES   0x1c
  25 #define APPLE_PWM_OFF_CYCLES  0x18
  26
  27 #define APPLE_PWM_CTRL_ENABLE        BIT(0)
  28 #define APPLE_PWM_CTRL_MODE          BIT(2)
  29 #define APPLE_PWM_CTRL_UPDATE        BIT(5)
  30 #define APPLE_PWM_CTRL_TRIGGER       BIT(9)
  31 #define APPLE_PWM_CTRL_INVERT        BIT(10)
  32 #define APPLE_PWM_CTRL_OUTPUT_ENABLE BIT(14)
  33
  34 struct apple_pwm {
  35         struct pwm_chip chip;
  36         void __iomem *base;
  37         u64 clkrate;
  38 };
  39
  40 static inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip)
  41 {
  42         return container_of(chip, struct apple_pwm, chip);
  43 }
  44
  45 static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  46                            const struct pwm_state *state)
  47 {
  48         struct apple_pwm *fpwm;
  49
  50         if (state->polarity == PWM_POLARITY_INVERSED)
  51                 return -EINVAL;
  52
  53         fpwm = to_apple_pwm(chip);
  54         if (state->enabled) {
  55                 u64 on_cycles, off_cycles;
  56
  57                 on_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
  58                                                 state->duty_cycle, NSEC_PER_SEC);
  59                 if (on_cycles > 0xFFFFFFFF)
  60                         on_cycles = 0xFFFFFFFF;
  61
  62                 off_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
  63                                                  state->period, NSEC_PER_SEC) - on_cycles;
  64                 if (off_cycles > 0xFFFFFFFF)
  65                         off_cycles = 0xFFFFFFFF;
  66
  67                 writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES);
  68                 writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES);
  69                 writel(APPLE_PWM_CTRL_ENABLE | APPLE_PWM_CTRL_OUTPUT_ENABLE | APPLE_PWM_CTRL_UPDATE,
  70                        fpwm->base + APPLE_PWM_CTRL);
  71         } else {
  72                 writel(0, fpwm->base + APPLE_PWM_CTRL);
  73         }
  74         return 0;
  75 }
  76
  77 static int apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  78                            struct pwm_state *state)
  79 {
  80         struct apple_pwm *fpwm;
  81         u32 on_cycles, off_cycles, ctrl;
  82
  83         fpwm = to_apple_pwm(chip);
  84
  85         ctrl = readl(fpwm->base + APPLE_PWM_CTRL);
  86         on_cycles = readl(fpwm->base + APPLE_PWM_ON_CYCLES);
  87         off_cycles = readl(fpwm->base + APPLE_PWM_OFF_CYCLES);
  88
  89         state->enabled = (ctrl & APPLE_PWM_CTRL_ENABLE) && (ctrl & APPLE_PWM_CTRL_OUTPUT_ENABLE);
  90         state->polarity = PWM_POLARITY_NORMAL;
  91         // on_cycles + off_cycles is 33 bits, NSEC_PER_SEC is 30, there is no overflow
  92         state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate);
  93         state->period = DIV64_U64_ROUND_UP(((u64)off_cycles + (u64)on_cycles) *
  94                                             NSEC_PER_SEC, fpwm->clkrate);
  95
  96         return 0;
  97 }
  98
  99 static const struct pwm_ops apple_pwm_ops = {
 100         .apply = apple_pwm_apply,
 101         .get_state = apple_pwm_get_state,
 102         .owner = THIS_MODULE,
 103 };
 104
 105 static int apple_pwm_probe(struct platform_device *pdev)
 106 {
 107         struct apple_pwm *fpwm;
 108         struct clk *clk;
 109         int ret;
 110
 111         fpwm = devm_kzalloc(&pdev->dev, sizeof(*fpwm), GFP_KERNEL);
 112         if (!fpwm)
 113                 return -ENOMEM;
 114
 115         fpwm->base = devm_platform_ioremap_resource(pdev, 0);
 116         if (IS_ERR(fpwm->base))
 117                 return PTR_ERR(fpwm->base);
 118
 119         clk = devm_clk_get_enabled(&pdev->dev, NULL);
 120         if (IS_ERR(clk))
 121                 return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get the clock");
 122
 123         /*
 124          * Uses the 24MHz system clock on all existing devices, can only
 125          * happen if the device tree is broken
 126          *
 127          * This check is done to prevent an overflow in .apply
 128          */
 129         fpwm->clkrate = clk_get_rate(clk);
 130         if (fpwm->clkrate > NSEC_PER_SEC)
 131                 return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock out of range");
 132
 133         fpwm->chip.dev = &pdev->dev;
 134         fpwm->chip.npwm = 1;
 135         fpwm->chip.ops = &apple_pwm_ops;
 136
 137         ret = devm_pwmchip_add(&pdev->dev, &fpwm->chip);
 138         if (ret < 0)
 139                 return dev_err_probe(&pdev->dev, ret, "unable to add pwm chip");
 140
 141         return 0;
 142 }
 143
 144 static const struct of_device_id apple_pwm_of_match[] = {
 145         { .compatible = "apple,s5l-fpwm" },
 146         {}
 147 };
 148 MODULE_DEVICE_TABLE(of, apple_pwm_of_match);
 149
 150 static struct platform_driver apple_pwm_driver = {
 151         .probe = apple_pwm_probe,
 152         .driver = {
 153                 .name = "apple-pwm",
 154                 .of_match_table = apple_pwm_of_match,
 155         },
 156 };
 157 module_platform_driver(apple_pwm_driver);
 158
 159 MODULE_DESCRIPTION("Apple SoC PWM driver");
 160 MODULE_LICENSE("Dual MIT/GPL");