1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2018 Integrated Device Technology, Inc
6 #define pr_fmt(fmt) "IDT_82p33xxx: " fmt
8 #include <linux/firmware.h>
10 #include <linux/module.h>
11 #include <linux/ptp_clock_kernel.h>
12 #include <linux/delay.h>
13 #include <linux/kernel.h>
14 #include <linux/timekeeping.h>
15 #include <linux/bitops.h>
17 #include "ptp_private.h"
18 #include "ptp_idt82p33.h"
20 MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices");
21 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
22 MODULE_VERSION("1.0");
23 MODULE_LICENSE("GPL");
24 MODULE_FIRMWARE(FW_FILENAME);
26 /* Module Parameters */
27 static u32 sync_tod_timeout = SYNC_TOD_TIMEOUT_SEC;
28 module_param(sync_tod_timeout, uint, 0);
29 MODULE_PARM_DESC(sync_tod_timeout,
30 "duration in second to keep SYNC_TOD on (set to 0 to keep it always on)");
32 static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
33 module_param(phase_snap_threshold, uint, 0);
34 MODULE_PARM_DESC(phase_snap_threshold,
35 "threshold (150000ns by default) below which adjtime would ignore");
37 static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,
38 u8 buf[TOD_BYTE_COUNT])
45 for (i = 0; i < 3; i++) {
51 for (i = 0; i < 5; i++) {
60 static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,
61 u8 buf[TOD_BYTE_COUNT])
70 for (i = 0; i < 4; i++) {
75 for (i = 4; i < TOD_BYTE_COUNT; i++) {
81 static int idt82p33_xfer_read(struct idt82p33 *idt82p33,
82 unsigned char regaddr,
86 struct i2c_client *client = idt82p33->client;
87 struct i2c_msg msg[2];
90 msg[0].addr = client->addr;
93 msg[0].buf = ®addr;
95 msg[1].addr = client->addr;
96 msg[1].flags = I2C_M_RD;
100 cnt = i2c_transfer(client->adapter, msg, 2);
102 dev_err(&client->dev, "i2c_transfer returned %d\n", cnt);
104 } else if (cnt != 2) {
105 dev_err(&client->dev,
106 "i2c_transfer sent only %d of %d messages\n", cnt, 2);
112 static int idt82p33_xfer_write(struct idt82p33 *idt82p33,
117 struct i2c_client *client = idt82p33->client;
118 /* we add 1 byte for device register */
119 u8 msg[IDT82P33_MAX_WRITE_COUNT + 1];
122 if (count > IDT82P33_MAX_WRITE_COUNT)
126 memcpy(&msg[1], buf, count);
128 err = i2c_master_send(client, msg, count + 1);
130 dev_err(&client->dev, "i2c_master_send returned %d\n", err);
137 static int idt82p33_page_offset(struct idt82p33 *idt82p33, unsigned char val)
141 if (idt82p33->page_offset == val)
144 err = idt82p33_xfer_write(idt82p33, PAGE_ADDR, &val, sizeof(val));
146 dev_err(&idt82p33->client->dev,
147 "failed to set page offset %d\n", val);
149 idt82p33->page_offset = val;
154 static int idt82p33_rdwr(struct idt82p33 *idt82p33, unsigned int regaddr,
155 unsigned char *buf, unsigned int count, bool write)
160 page = _PAGE(regaddr);
161 offset = _OFFSET(regaddr);
163 err = idt82p33_page_offset(idt82p33, page);
168 return idt82p33_xfer_write(idt82p33, offset, buf, count);
170 return idt82p33_xfer_read(idt82p33, offset, buf, count);
173 static int idt82p33_read(struct idt82p33 *idt82p33, unsigned int regaddr,
174 unsigned char *buf, unsigned int count)
176 return idt82p33_rdwr(idt82p33, regaddr, buf, count, false);
179 static int idt82p33_write(struct idt82p33 *idt82p33, unsigned int regaddr,
180 unsigned char *buf, unsigned int count)
182 return idt82p33_rdwr(idt82p33, regaddr, buf, count, true);
185 static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
188 struct idt82p33 *idt82p33 = channel->idt82p33;
192 if (channel->pll_mode == mode)
195 err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
196 &dpll_mode, sizeof(dpll_mode));
200 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
202 dpll_mode |= (mode << PLL_MODE_SHIFT);
204 err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
205 &dpll_mode, sizeof(dpll_mode));
209 channel->pll_mode = dpll_mode;
214 static int _idt82p33_gettime(struct idt82p33_channel *channel,
215 struct timespec64 *ts)
217 struct idt82p33 *idt82p33 = channel->idt82p33;
218 u8 buf[TOD_BYTE_COUNT];
222 trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
223 HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
226 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
227 &trigger, sizeof(trigger));
232 if (idt82p33->calculate_overhead_flag)
233 idt82p33->start_time = ktime_get_raw();
235 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
240 idt82p33_byte_array_to_timespec(ts, buf);
247 * Bits[7:4] Write 0x9, MSB write
248 * Bits[3:0] Read 0x9, LSB read
251 static int _idt82p33_settime(struct idt82p33_channel *channel,
252 struct timespec64 const *ts)
254 struct idt82p33 *idt82p33 = channel->idt82p33;
255 struct timespec64 local_ts = *ts;
256 char buf[TOD_BYTE_COUNT];
257 s64 dynamic_overhead_ns;
258 unsigned char trigger;
262 trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
263 HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
265 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
266 &trigger, sizeof(trigger));
271 if (idt82p33->calculate_overhead_flag) {
272 dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
273 - ktime_to_ns(idt82p33->start_time);
275 timespec64_add_ns(&local_ts, dynamic_overhead_ns);
277 idt82p33->calculate_overhead_flag = 0;
280 idt82p33_timespec_to_byte_array(&local_ts, buf);
283 * Store the new time value.
285 for (i = 0; i < TOD_BYTE_COUNT; i++) {
286 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
287 &buf[i], sizeof(buf[i]));
295 static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
297 struct idt82p33 *idt82p33 = channel->idt82p33;
298 struct timespec64 ts;
302 idt82p33->calculate_overhead_flag = 1;
304 err = _idt82p33_gettime(channel, &ts);
309 now_ns = timespec64_to_ns(&ts);
310 now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
312 ts = ns_to_timespec64(now_ns);
314 err = _idt82p33_settime(channel, &ts);
319 static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
321 struct idt82p33 *idt82p33 = channel->idt82p33;
322 unsigned char buf[5] = {0};
326 if (scaled_ppm == channel->current_freq_ppb)
330 * Frequency Control Word unit is: 1.68 * 10^-10 ppm
339 * FCW = -------------
343 fcw = scaled_ppm * 244140625ULL;
344 fcw = div_s64(fcw, 2688);
346 for (i = 0; i < 5; i++) {
351 err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
356 err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
360 channel->current_freq_ppb = scaled_ppm;
365 static int idt82p33_measure_one_byte_write_overhead(
366 struct idt82p33_channel *channel, s64 *overhead_ns)
368 struct idt82p33 *idt82p33 = channel->idt82p33;
377 trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
378 HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
380 for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
382 start = ktime_get_raw();
384 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
385 &trigger, sizeof(trigger));
387 stop = ktime_get_raw();
392 total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
395 *overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
400 static int idt82p33_measure_tod_write_9_byte_overhead(
401 struct idt82p33_channel *channel)
403 struct idt82p33 *idt82p33 = channel->idt82p33;
404 u8 buf[TOD_BYTE_COUNT];
411 idt82p33->tod_write_overhead_ns = 0;
413 for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
415 start = ktime_get_raw();
417 /* Need one less byte for applicable overhead */
418 for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) {
419 err = idt82p33_write(idt82p33,
420 channel->dpll_tod_cnfg + i,
421 &buf[i], sizeof(buf[i]));
426 stop = ktime_get_raw();
428 total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
431 idt82p33->tod_write_overhead_ns = div_s64(total_ns,
432 MAX_MEASURMENT_COUNT);
437 static int idt82p33_measure_settime_gettime_gap_overhead(
438 struct idt82p33_channel *channel, s64 *overhead_ns)
440 struct timespec64 ts1 = {0, 0};
441 struct timespec64 ts2;
446 err = _idt82p33_settime(channel, &ts1);
451 err = _idt82p33_gettime(channel, &ts2);
454 *overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1);
459 static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
461 s64 trailing_overhead_ns, one_byte_write_ns, gap_ns;
462 struct idt82p33 *idt82p33 = channel->idt82p33;
465 idt82p33->tod_write_overhead_ns = 0;
467 err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
470 dev_err(&idt82p33->client->dev,
471 "Failed in %s with err %d!\n", __func__, err);
475 err = idt82p33_measure_one_byte_write_overhead(channel,
481 err = idt82p33_measure_tod_write_9_byte_overhead(channel);
486 trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);
488 idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
493 static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
500 if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) {
501 if ((val & 0xfc) || !(val & 0x3)) {
502 dev_err(&idt82p33->client->dev,
503 "Invalid PLL mask 0x%hhx\n", val);
506 idt82p33->pll_mask = val;
508 } else if (page == PLL0_OUTMASK_ADDR_HI &&
509 offset == PLL0_OUTMASK_ADDR_LO) {
510 idt82p33->channel[0].output_mask = val;
511 } else if (page == PLL1_OUTMASK_ADDR_HI &&
512 offset == PLL1_OUTMASK_ADDR_LO) {
513 idt82p33->channel[1].output_mask = val;
519 static void idt82p33_display_masks(struct idt82p33 *idt82p33)
523 dev_info(&idt82p33->client->dev,
524 "pllmask = 0x%02x\n", idt82p33->pll_mask);
526 for (i = 0; i < MAX_PHC_PLL; i++) {
529 if (mask & idt82p33->pll_mask)
530 dev_info(&idt82p33->client->dev,
531 "PLL%d output_mask = 0x%04x\n",
532 i, idt82p33->channel[i].output_mask);
536 static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
538 struct idt82p33 *idt82p33 = channel->idt82p33;
542 /* Turn it off after sync_tod_timeout seconds */
543 if (enable && sync_tod_timeout)
544 ptp_schedule_worker(channel->ptp_clock,
545 sync_tod_timeout * HZ);
547 err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
548 &sync_cnfg, sizeof(sync_cnfg));
552 sync_cnfg &= ~SYNC_TOD;
554 sync_cnfg |= SYNC_TOD;
556 return idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
557 &sync_cnfg, sizeof(sync_cnfg));
560 static long idt82p33_sync_tod_work_handler(struct ptp_clock_info *ptp)
562 struct idt82p33_channel *channel =
563 container_of(ptp, struct idt82p33_channel, caps);
564 struct idt82p33 *idt82p33 = channel->idt82p33;
566 mutex_lock(&idt82p33->reg_lock);
568 (void)idt82p33_sync_tod(channel, false);
570 mutex_unlock(&idt82p33->reg_lock);
572 /* Return a negative value here to not reschedule */
576 static int idt82p33_output_enable(struct idt82p33_channel *channel,
577 bool enable, unsigned int outn)
579 struct idt82p33 *idt82p33 = channel->idt82p33;
583 err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
587 val &= ~SQUELCH_ENABLE;
589 val |= SQUELCH_ENABLE;
591 return idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
594 static int idt82p33_output_mask_enable(struct idt82p33_channel *channel,
601 mask = channel->output_mask;
606 err = idt82p33_output_enable(channel, enable, outn);
618 static int idt82p33_perout_enable(struct idt82p33_channel *channel,
620 struct ptp_perout_request *perout)
622 unsigned int flags = perout->flags;
624 /* Enable/disable output based on output_mask */
625 if (flags == PEROUT_ENABLE_OUTPUT_MASK)
626 return idt82p33_output_mask_enable(channel, enable);
628 /* Enable/disable individual output instead */
629 return idt82p33_output_enable(channel, enable, perout->index);
632 static int idt82p33_enable_tod(struct idt82p33_channel *channel)
634 struct idt82p33 *idt82p33 = channel->idt82p33;
635 struct timespec64 ts = {0, 0};
640 err = idt82p33_write(idt82p33, channel->dpll_input_mode_cnfg,
645 err = idt82p33_measure_tod_write_overhead(channel);
648 dev_err(&idt82p33->client->dev,
649 "Failed in %s with err %d!\n", __func__, err);
653 err = _idt82p33_settime(channel, &ts);
658 return idt82p33_sync_tod(channel, true);
661 static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
663 struct idt82p33_channel *channel;
666 for (i = 0; i < MAX_PHC_PLL; i++) {
668 channel = &idt82p33->channel[i];
670 if (channel->ptp_clock)
671 ptp_clock_unregister(channel->ptp_clock);
675 static int idt82p33_enable(struct ptp_clock_info *ptp,
676 struct ptp_clock_request *rq, int on)
678 struct idt82p33_channel *channel =
679 container_of(ptp, struct idt82p33_channel, caps);
680 struct idt82p33 *idt82p33 = channel->idt82p33;
685 mutex_lock(&idt82p33->reg_lock);
687 if (rq->type == PTP_CLK_REQ_PEROUT) {
689 err = idt82p33_perout_enable(channel, false,
691 /* Only accept a 1-PPS aligned to the second. */
692 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
693 rq->perout.period.nsec) {
696 err = idt82p33_perout_enable(channel, true,
700 mutex_unlock(&idt82p33->reg_lock);
705 static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns)
707 struct idt82p33_channel *channel =
708 container_of(ptp, struct idt82p33_channel, caps);
709 struct idt82p33 *idt82p33 = channel->idt82p33;
710 s64 offset_regval, offset_fs;
714 offset_fs = (s64)(-offset_ns) * 1000000;
716 if (offset_fs > WRITE_PHASE_OFFSET_LIMIT)
717 offset_fs = WRITE_PHASE_OFFSET_LIMIT;
718 else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT)
719 offset_fs = -WRITE_PHASE_OFFSET_LIMIT;
721 /* Convert from phaseoffset_fs to register value */
722 offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL);
724 val[0] = offset_regval & 0xFF;
725 val[1] = (offset_regval >> 8) & 0xFF;
726 val[2] = (offset_regval >> 16) & 0xFF;
727 val[3] = (offset_regval >> 24) & 0x1F;
728 val[3] |= PH_OFFSET_EN;
730 mutex_lock(&idt82p33->reg_lock);
732 err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH);
734 dev_err(&idt82p33->client->dev,
735 "Failed in %s with err %d!\n", __func__, err);
739 err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val,
743 mutex_unlock(&idt82p33->reg_lock);
747 static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
749 struct idt82p33_channel *channel =
750 container_of(ptp, struct idt82p33_channel, caps);
751 struct idt82p33 *idt82p33 = channel->idt82p33;
754 mutex_lock(&idt82p33->reg_lock);
755 err = _idt82p33_adjfine(channel, scaled_ppm);
757 dev_err(&idt82p33->client->dev,
758 "Failed in %s with err %d!\n", __func__, err);
759 mutex_unlock(&idt82p33->reg_lock);
764 static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
766 struct idt82p33_channel *channel =
767 container_of(ptp, struct idt82p33_channel, caps);
768 struct idt82p33 *idt82p33 = channel->idt82p33;
771 mutex_lock(&idt82p33->reg_lock);
773 if (abs(delta_ns) < phase_snap_threshold) {
774 mutex_unlock(&idt82p33->reg_lock);
778 err = _idt82p33_adjtime(channel, delta_ns);
781 mutex_unlock(&idt82p33->reg_lock);
782 dev_err(&idt82p33->client->dev,
783 "Adjtime failed in %s with err %d!\n", __func__, err);
787 err = idt82p33_sync_tod(channel, true);
789 dev_err(&idt82p33->client->dev,
790 "Sync_tod failed in %s with err %d!\n", __func__, err);
792 mutex_unlock(&idt82p33->reg_lock);
797 static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
799 struct idt82p33_channel *channel =
800 container_of(ptp, struct idt82p33_channel, caps);
801 struct idt82p33 *idt82p33 = channel->idt82p33;
804 mutex_lock(&idt82p33->reg_lock);
805 err = _idt82p33_gettime(channel, ts);
807 dev_err(&idt82p33->client->dev,
808 "Failed in %s with err %d!\n", __func__, err);
809 mutex_unlock(&idt82p33->reg_lock);
814 static int idt82p33_settime(struct ptp_clock_info *ptp,
815 const struct timespec64 *ts)
817 struct idt82p33_channel *channel =
818 container_of(ptp, struct idt82p33_channel, caps);
819 struct idt82p33 *idt82p33 = channel->idt82p33;
822 mutex_lock(&idt82p33->reg_lock);
823 err = _idt82p33_settime(channel, ts);
825 dev_err(&idt82p33->client->dev,
826 "Failed in %s with err %d!\n", __func__, err);
827 mutex_unlock(&idt82p33->reg_lock);
832 static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
836 channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
837 channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
838 channel->dpll_tod_sts = DPLL1_TOD_STS;
839 channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
840 channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
841 channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
842 channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
843 channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
846 channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
847 channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
848 channel->dpll_tod_sts = DPLL2_TOD_STS;
849 channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
850 channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
851 channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
852 channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
853 channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
859 channel->current_freq_ppb = 0;
864 static void idt82p33_caps_init(struct ptp_clock_info *caps)
866 caps->owner = THIS_MODULE;
867 caps->max_adj = 92000;
868 caps->n_per_out = 11;
869 caps->adjphase = idt82p33_adjwritephase;
870 caps->adjfine = idt82p33_adjfine;
871 caps->adjtime = idt82p33_adjtime;
872 caps->gettime64 = idt82p33_gettime;
873 caps->settime64 = idt82p33_settime;
874 caps->enable = idt82p33_enable;
875 caps->do_aux_work = idt82p33_sync_tod_work_handler;
878 static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
880 struct idt82p33_channel *channel;
883 if (!(index < MAX_PHC_PLL))
886 channel = &idt82p33->channel[index];
888 err = idt82p33_channel_init(channel, index);
890 dev_err(&idt82p33->client->dev,
891 "Channel_init failed in %s with err %d!\n",
896 channel->idt82p33 = idt82p33;
898 idt82p33_caps_init(&channel->caps);
899 snprintf(channel->caps.name, sizeof(channel->caps.name),
900 "IDT 82P33 PLL%u", index);
902 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
904 if (IS_ERR(channel->ptp_clock)) {
905 err = PTR_ERR(channel->ptp_clock);
906 channel->ptp_clock = NULL;
910 if (!channel->ptp_clock)
913 err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
915 dev_err(&idt82p33->client->dev,
916 "Dpll_set_mode failed in %s with err %d!\n",
921 err = idt82p33_enable_tod(channel);
923 dev_err(&idt82p33->client->dev,
924 "Enable_tod failed in %s with err %d!\n",
929 dev_info(&idt82p33->client->dev, "PLL%d registered as ptp%d\n",
930 index, channel->ptp_clock->index);
935 static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
937 const struct firmware *fw;
938 struct idt82p33_fwrc *rec;
939 u8 loaddr, page, val;
943 dev_dbg(&idt82p33->client->dev,
944 "requesting firmware '%s'\n", FW_FILENAME);
946 err = request_firmware(&fw, FW_FILENAME, &idt82p33->client->dev);
949 dev_err(&idt82p33->client->dev,
950 "Failed in %s with err %d!\n", __func__, err);
954 dev_dbg(&idt82p33->client->dev, "firmware size %zu bytes\n", fw->size);
956 rec = (struct idt82p33_fwrc *) fw->data;
958 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
961 dev_err(&idt82p33->client->dev,
962 "bad firmware, reserved field non-zero\n");
966 loaddr = rec->loaddr;
971 err = idt82p33_check_and_set_masks(idt82p33, page,
976 /* maximum 8 pages */
977 if (page >= PAGE_NUM)
980 /* Page size 128, last 4 bytes of page skipped */
981 if (((loaddr > 0x7b) && (loaddr <= 0x7f))
985 err = idt82p33_write(idt82p33, _ADDR(page, loaddr),
993 idt82p33_display_masks(idt82p33);
995 release_firmware(fw);
1000 static int idt82p33_probe(struct i2c_client *client,
1001 const struct i2c_device_id *id)
1003 struct idt82p33 *idt82p33;
1009 idt82p33 = devm_kzalloc(&client->dev,
1010 sizeof(struct idt82p33), GFP_KERNEL);
1014 mutex_init(&idt82p33->reg_lock);
1016 idt82p33->client = client;
1017 idt82p33->page_offset = 0xff;
1018 idt82p33->tod_write_overhead_ns = 0;
1019 idt82p33->calculate_overhead_flag = 0;
1020 idt82p33->pll_mask = DEFAULT_PLL_MASK;
1021 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
1022 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
1024 mutex_lock(&idt82p33->reg_lock);
1026 err = idt82p33_load_firmware(idt82p33);
1029 dev_warn(&idt82p33->client->dev,
1030 "loading firmware failed with %d\n", err);
1032 if (idt82p33->pll_mask) {
1033 for (i = 0; i < MAX_PHC_PLL; i++) {
1034 if (idt82p33->pll_mask & (1 << i)) {
1035 err = idt82p33_enable_channel(idt82p33, i);
1037 dev_err(&idt82p33->client->dev,
1038 "Failed in %s with err %d!\n",
1045 dev_err(&idt82p33->client->dev,
1046 "no PLLs flagged as PHCs, nothing to do\n");
1050 mutex_unlock(&idt82p33->reg_lock);
1053 idt82p33_ptp_clock_unregister_all(idt82p33);
1057 i2c_set_clientdata(client, idt82p33);
1062 static int idt82p33_remove(struct i2c_client *client)
1064 struct idt82p33 *idt82p33 = i2c_get_clientdata(client);
1066 idt82p33_ptp_clock_unregister_all(idt82p33);
1067 mutex_destroy(&idt82p33->reg_lock);
1073 static const struct of_device_id idt82p33_dt_id[] = {
1074 { .compatible = "idt,82p33810" },
1075 { .compatible = "idt,82p33813" },
1076 { .compatible = "idt,82p33814" },
1077 { .compatible = "idt,82p33831" },
1078 { .compatible = "idt,82p33910" },
1079 { .compatible = "idt,82p33913" },
1080 { .compatible = "idt,82p33914" },
1081 { .compatible = "idt,82p33931" },
1084 MODULE_DEVICE_TABLE(of, idt82p33_dt_id);
1087 static const struct i2c_device_id idt82p33_i2c_id[] = {
1098 MODULE_DEVICE_TABLE(i2c, idt82p33_i2c_id);
1100 static struct i2c_driver idt82p33_driver = {
1102 .of_match_table = of_match_ptr(idt82p33_dt_id),
1105 .probe = idt82p33_probe,
1106 .remove = idt82p33_remove,
1107 .id_table = idt82p33_i2c_id,
1110 module_i2c_driver(idt82p33_driver);