1 // SPDX-License-Identifier: GPL-2.0+
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
8 #include <linux/firmware.h>
10 #include <linux/module.h>
11 #include <linux/ptp_clock_kernel.h>
12 #include <linux/delay.h>
13 #include <linux/jiffies.h>
14 #include <linux/kernel.h>
15 #include <linux/timekeeping.h>
16 #include <linux/string.h>
18 #include "ptp_private.h"
19 #include "ptp_clockmatrix.h"
21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
24 MODULE_VERSION("1.0");
25 MODULE_LICENSE("GPL");
28 * The name of the firmware file to be loaded
29 * over-rides any automatic selection
31 static char *firmware;
32 module_param(firmware, charp, 0);
34 #define SETTIME_CORRECTION (0)
36 static int contains_full_configuration(const struct firmware *fw)
38 s32 full_count = FULL_FW_CFG_BYTES - FULL_FW_CFG_SKIPPED_BYTES;
39 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
45 /* If the firmware contains 'full configuration' SM_RESET can be used
46 * to ensure proper configuration.
48 * Full configuration is defined as the number of programmable
49 * bytes within the configuration range minus page offset addr range.
51 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
52 regaddr = rec->hiaddr << 8;
53 regaddr |= rec->loaddr;
59 /* Top (status registers) and bottom are read-only */
60 if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
63 /* Page size 128, last 4 bytes of page skipped */
64 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
70 return (count >= full_count);
73 static int char_array_to_timespec(u8 *buf,
75 struct timespec64 *ts)
81 if (count < TOD_BYTE_COUNT)
84 /* Sub-nanoseconds are in buf[0]. */
86 for (i = 0; i < 3; i++) {
92 for (i = 0; i < 5; i++) {
103 static int timespec_to_char_array(struct timespec64 const *ts,
111 if (count < TOD_BYTE_COUNT)
117 /* Sub-nanoseconds are in buf[0]. */
119 for (i = 1; i < 5; i++) {
120 buf[i] = nsec & 0xff;
124 for (i = 5; i < TOD_BYTE_COUNT; i++) {
133 static int idtcm_strverscmp(const char *version1, const char *version2)
138 if (sscanf(version1, "%hhu.%hhu.%hhu",
139 &ver1[0], &ver1[1], &ver1[2]) != 3)
141 if (sscanf(version2, "%hhu.%hhu.%hhu",
142 &ver2[0], &ver2[1], &ver2[2]) != 3)
145 for (i = 0; i < 3; i++) {
146 if (ver1[i] > ver2[i])
148 if (ver1[i] < ver2[i])
155 static int idtcm_xfer_read(struct idtcm *idtcm,
160 struct i2c_client *client = idtcm->client;
161 struct i2c_msg msg[2];
164 msg[0].addr = client->addr;
167 msg[0].buf = ®addr;
169 msg[1].addr = client->addr;
170 msg[1].flags = I2C_M_RD;
174 cnt = i2c_transfer(client->adapter, msg, 2);
177 dev_err(&client->dev,
178 "i2c_transfer failed at %d in %s, at addr: %04x!",
179 __LINE__, __func__, regaddr);
181 } else if (cnt != 2) {
182 dev_err(&client->dev,
183 "i2c_transfer sent only %d of %d messages", cnt, 2);
190 static int idtcm_xfer_write(struct idtcm *idtcm,
195 struct i2c_client *client = idtcm->client;
196 /* we add 1 byte for device register */
197 u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
200 if (count > IDTCM_MAX_WRITE_COUNT)
204 memcpy(&msg[1], buf, count);
206 cnt = i2c_master_send(client, msg, count + 1);
209 dev_err(&client->dev,
210 "i2c_master_send failed at %d in %s, at addr: %04x!",
211 __LINE__, __func__, regaddr);
218 static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
223 if (idtcm->page_offset == val)
231 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
233 idtcm->page_offset = 0xff;
234 dev_err(&idtcm->client->dev, "failed to set page offset");
236 idtcm->page_offset = val;
242 static int _idtcm_rdwr(struct idtcm *idtcm,
252 hi = (regaddr >> 8) & 0xff;
255 err = idtcm_page_offset(idtcm, hi);
260 return idtcm_xfer_write(idtcm, lo, buf, count);
262 return idtcm_xfer_read(idtcm, lo, buf, count);
265 static int idtcm_read(struct idtcm *idtcm,
271 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
274 static int idtcm_write(struct idtcm *idtcm,
280 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
283 static int clear_boot_status(struct idtcm *idtcm)
287 return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
290 static int read_boot_status(struct idtcm *idtcm, u32 *status)
295 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
297 *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
302 static int wait_for_boot_status_ready(struct idtcm *idtcm)
305 u8 i = 30; /* 30 * 100ms = 3s */
309 err = read_boot_status(idtcm, &status);
321 dev_warn(&idtcm->client->dev, "%s timed out", __func__);
326 static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
328 return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
332 static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
334 return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
337 static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
339 unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
345 err = read_sys_apll_status(idtcm, &apll);
349 err = read_sys_dpll_status(idtcm, &dpll);
353 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
354 dpll &= DPLL_SYS_STATE_MASK;
356 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
357 dpll == DPLL_STATE_LOCKED) {
359 } else if (dpll == DPLL_STATE_FREERUN ||
360 dpll == DPLL_STATE_HOLDOVER ||
361 dpll == DPLL_STATE_OPEN_LOOP) {
362 dev_warn(&idtcm->client->dev,
363 "No wait state: DPLL_SYS_STATE %d", dpll);
367 msleep(LOCK_POLL_INTERVAL_MS);
368 } while (time_is_after_jiffies(timeout));
370 dev_warn(&idtcm->client->dev,
371 "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d",
372 LOCK_TIMEOUT_MS, apll, dpll);
377 static void wait_for_chip_ready(struct idtcm *idtcm)
379 if (wait_for_boot_status_ready(idtcm))
380 dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0");
382 if (wait_for_sys_apll_dpll_lock(idtcm))
383 dev_warn(&idtcm->client->dev,
384 "Continuing while SYS APLL/DPLL is not locked");
387 static int _idtcm_gettime(struct idtcm_channel *channel,
388 struct timespec64 *ts)
390 struct idtcm *idtcm = channel->idtcm;
391 u8 buf[TOD_BYTE_COUNT];
396 err = idtcm_read(idtcm, channel->tod_read_primary,
397 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
401 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
402 trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
403 trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
405 err = idtcm_write(idtcm, channel->tod_read_primary,
406 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
410 /* wait trigger to be 0 */
411 while (trigger & TOD_READ_TRIGGER_MASK) {
412 if (idtcm->calculate_overhead_flag)
413 idtcm->start_time = ktime_get_raw();
415 err = idtcm_read(idtcm, channel->tod_read_primary,
416 TOD_READ_PRIMARY_CMD, &trigger,
425 err = idtcm_read(idtcm, channel->tod_read_primary,
426 TOD_READ_PRIMARY, buf, sizeof(buf));
430 err = char_array_to_timespec(buf, sizeof(buf), ts);
435 static int _sync_pll_output(struct idtcm *idtcm,
447 if (qn == 0 && qn_plus_1 == 0)
452 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
453 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
456 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
457 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
460 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
461 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
464 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
465 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
468 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
469 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
472 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
473 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
476 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
477 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
480 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
481 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
487 val = SYNCTRL1_MASTER_SYNC_RST;
489 /* Place master sync in reset */
490 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
494 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
498 /* Set sync trigger mask */
499 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
502 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
505 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
507 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
511 /* PLL5 can have OUT8 as second additional output. */
512 if (pll == 5 && qn_plus_1 != 0) {
513 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
514 &temp, sizeof(temp));
518 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
520 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
521 &temp, sizeof(temp));
525 temp |= Q9_TO_Q8_SYNC_TRIG;
527 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
528 &temp, sizeof(temp));
533 /* PLL6 can have OUT11 as second additional output. */
534 if (pll == 6 && qn_plus_1 != 0) {
535 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
536 &temp, sizeof(temp));
540 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
542 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
543 &temp, sizeof(temp));
547 temp |= Q10_TO_Q11_SYNC_TRIG;
549 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
550 &temp, sizeof(temp));
555 /* Place master sync out of reset */
556 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
557 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
562 static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
568 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
571 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
574 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
577 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
586 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
588 struct idtcm *idtcm = channel->idtcm;
597 u16 output_mask = channel->output_mask;
599 err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
603 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
604 &temp, sizeof(temp));
608 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
609 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
612 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
613 &temp, sizeof(temp));
617 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
618 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
621 for (pll = 0; pll < 8; pll++) {
626 /* First 4 pll has 2 outputs */
627 qn = output_mask & 0x1;
628 output_mask = output_mask >> 1;
629 qn_plus_1 = output_mask & 0x1;
630 output_mask = output_mask >> 1;
631 } else if (pll == 4) {
633 qn = output_mask & 0x1;
634 output_mask = output_mask >> 1;
636 } else if (pll == 5) {
638 qn_plus_1 = output_mask & 0x1;
639 output_mask = output_mask >> 1;
641 qn = output_mask & 0x1;
642 output_mask = output_mask >> 1;
643 } else if (pll == 6) {
644 qn = output_mask & 0x1;
645 output_mask = output_mask >> 1;
647 qn_plus_1 = output_mask & 0x1;
648 output_mask = output_mask >> 1;
650 } else if (pll == 7) {
651 if (out11_mux == 0) {
652 qn = output_mask & 0x1;
653 output_mask = output_mask >> 1;
657 if (qn != 0 || qn_plus_1 != 0)
658 err = _sync_pll_output(idtcm, pll, sync_src, qn,
668 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
669 struct timespec64 const *ts,
670 enum hw_tod_write_trig_sel wr_trig)
672 struct idtcm *idtcm = channel->idtcm;
673 u8 buf[TOD_BYTE_COUNT];
676 struct timespec64 local_ts = *ts;
677 s64 total_overhead_ns;
679 /* Configure HW TOD write trigger. */
680 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
686 cmd |= wr_trig | 0x08;
688 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
693 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
694 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
698 err = idtcm_write(idtcm, channel->hw_dpll_n,
699 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
704 /* ARM HW TOD write trigger. */
707 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
710 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
711 if (idtcm->calculate_overhead_flag) {
712 /* Assumption: I2C @ 400KHz */
713 ktime_t diff = ktime_sub(ktime_get_raw(),
715 total_overhead_ns = ktime_to_ns(diff)
716 + idtcm->tod_write_overhead_ns
717 + SETTIME_CORRECTION;
719 timespec64_add_ns(&local_ts, total_overhead_ns);
721 idtcm->calculate_overhead_flag = 0;
724 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
728 err = idtcm_write(idtcm, channel->hw_dpll_n,
729 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
735 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
736 struct timespec64 const *ts,
737 enum scsr_tod_write_trig_sel wr_trig,
738 enum scsr_tod_write_type_sel wr_type)
740 struct idtcm *idtcm = channel->idtcm;
741 unsigned char buf[TOD_BYTE_COUNT], cmd;
742 struct timespec64 local_ts = *ts;
745 timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
747 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
751 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
756 /* Trigger the write operation. */
757 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
762 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
763 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
764 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
765 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
767 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
772 /* Wait for the operation to complete. */
774 /* pps trigger takes up to 1 sec to complete */
775 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
778 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
783 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
787 dev_err(&idtcm->client->dev,
788 "Timed out waiting for the write counter");
796 static int get_output_base_addr(u8 outn)
844 static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
845 struct timespec64 const *ts)
847 struct idtcm *idtcm = channel->idtcm;
850 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
852 dev_err(&idtcm->client->dev,
853 "%s: Set HW ToD failed", __func__);
857 return idtcm_sync_pps_output(channel);
860 static int _idtcm_settime(struct idtcm_channel *channel,
861 struct timespec64 const *ts,
862 enum scsr_tod_write_type_sel wr_type)
864 return _idtcm_set_dpll_scsr_tod(channel, ts,
865 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
869 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
874 struct idtcm *idtcm = channel->idtcm;
877 for (i = 0; i < 4; i++) {
878 buf[i] = 0xff & (offset_ns);
882 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
888 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
893 struct idtcm *idtcm = channel->idtcm;
896 if (max_ffo_ppb & 0xff000000)
899 for (i = 0; i < 3; i++) {
900 buf[i] = 0xff & (max_ffo_ppb);
904 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
905 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
910 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
913 struct idtcm *idtcm = channel->idtcm;
916 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
923 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
924 PULL_IN_CTRL, &buf, sizeof(buf));
932 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
938 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
942 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
946 err = idtcm_start_phase_pull_in(channel);
951 static int set_tod_write_overhead(struct idtcm_channel *channel)
953 struct idtcm *idtcm = channel->idtcm;
962 char buf[TOD_BYTE_COUNT] = {0};
964 /* Set page offset */
965 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
968 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
969 start = ktime_get_raw();
971 err = idtcm_write(idtcm, channel->hw_dpll_n,
972 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
976 stop = ktime_get_raw();
978 diff = ktime_sub(stop, start);
980 current_ns = ktime_to_ns(diff);
983 lowest_ns = current_ns;
985 if (current_ns < lowest_ns)
986 lowest_ns = current_ns;
990 idtcm->tod_write_overhead_ns = lowest_ns;
995 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
998 struct idtcm *idtcm = channel->idtcm;
999 struct timespec64 ts;
1002 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
1003 err = idtcm_do_phase_pull_in(channel, delta, 0);
1005 idtcm->calculate_overhead_flag = 1;
1007 err = set_tod_write_overhead(channel);
1011 err = _idtcm_gettime(channel, &ts);
1015 now = timespec64_to_ns(&ts);
1018 ts = ns_to_timespec64(now);
1020 err = _idtcm_settime_deprecated(channel, &ts);
1026 static int idtcm_state_machine_reset(struct idtcm *idtcm)
1028 u8 byte = SM_RESET_CMD;
1033 clear_boot_status(idtcm);
1035 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
1038 for (i = 0; i < 30; i++) {
1039 msleep_interruptible(100);
1040 read_boot_status(idtcm, &status);
1042 if (status == 0xA0) {
1043 dev_dbg(&idtcm->client->dev,
1044 "SM_RESET completed in %d ms", i * 100);
1050 dev_err(&idtcm->client->dev,
1051 "Timed out waiting for CM_RESET to complete");
1057 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1059 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
1062 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1067 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1069 *product_id = (buf[1] << 8) | buf[0];
1074 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1079 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1086 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1088 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1091 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1093 return idtcm_read(idtcm,
1100 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1103 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1104 config_select, sizeof(u8));
1107 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1112 case TOD0_OUT_ALIGN_MASK_ADDR:
1113 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1115 case TOD0_OUT_ALIGN_MASK_ADDR + 1:
1116 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1118 case TOD1_OUT_ALIGN_MASK_ADDR:
1119 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1121 case TOD1_OUT_ALIGN_MASK_ADDR + 1:
1122 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1124 case TOD2_OUT_ALIGN_MASK_ADDR:
1125 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1127 case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1128 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1130 case TOD3_OUT_ALIGN_MASK_ADDR:
1131 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1133 case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1134 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1137 err = -EFAULT; /* Bad address */;
1144 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1146 if (index >= MAX_TOD) {
1147 dev_err(&idtcm->client->dev, "ToD%d not supported", index);
1151 if (pll >= MAX_PLL) {
1152 dev_err(&idtcm->client->dev, "Pll%d not supported", pll);
1156 idtcm->channel[index].pll = pll;
1161 static int check_and_set_masks(struct idtcm *idtcm,
1169 if ((val & 0xf0) || !(val & 0x0f)) {
1170 dev_err(&idtcm->client->dev, "Invalid TOD mask 0x%02x", val);
1173 idtcm->tod_mask = val;
1176 case TOD0_PTP_PLL_ADDR:
1177 err = set_tod_ptp_pll(idtcm, 0, val);
1179 case TOD1_PTP_PLL_ADDR:
1180 err = set_tod_ptp_pll(idtcm, 1, val);
1182 case TOD2_PTP_PLL_ADDR:
1183 err = set_tod_ptp_pll(idtcm, 2, val);
1185 case TOD3_PTP_PLL_ADDR:
1186 err = set_tod_ptp_pll(idtcm, 3, val);
1189 err = set_pll_output_mask(idtcm, regaddr, val);
1196 static void display_pll_and_masks(struct idtcm *idtcm)
1201 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x", idtcm->tod_mask);
1203 for (i = 0; i < MAX_TOD; i++) {
1206 if (mask & idtcm->tod_mask)
1207 dev_dbg(&idtcm->client->dev,
1208 "TOD%d pll = %d output_mask = 0x%04x",
1209 i, idtcm->channel[i].pll,
1210 idtcm->channel[i].output_mask);
1214 static int idtcm_load_firmware(struct idtcm *idtcm,
1217 char fname[128] = FW_FILENAME;
1218 const struct firmware *fw;
1219 struct idtcm_fwrc *rec;
1226 if (firmware) /* module parameter */
1227 snprintf(fname, sizeof(fname), "%s", firmware);
1229 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'", fname);
1231 err = request_firmware(&fw, fname, dev);
1233 dev_err(&idtcm->client->dev,
1234 "Failed at line %d in %s!", __LINE__, __func__);
1238 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes", fw->size);
1240 rec = (struct idtcm_fwrc *) fw->data;
1242 if (contains_full_configuration(fw))
1243 idtcm_state_machine_reset(idtcm);
1245 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1246 if (rec->reserved) {
1247 dev_err(&idtcm->client->dev,
1248 "bad firmware, reserved field non-zero");
1251 regaddr = rec->hiaddr << 8;
1252 regaddr |= rec->loaddr;
1255 loaddr = rec->loaddr;
1259 err = check_and_set_masks(idtcm, regaddr, val);
1262 if (err != -EINVAL) {
1265 /* Top (status registers) and bottom are read-only */
1266 if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
1269 /* Page size 128, last 4 bytes of page skipped */
1270 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
1273 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1280 display_pll_and_masks(idtcm);
1283 release_firmware(fw);
1287 static int idtcm_output_enable(struct idtcm_channel *channel,
1288 bool enable, unsigned int outn)
1290 struct idtcm *idtcm = channel->idtcm;
1295 base = get_output_base_addr(outn);
1298 dev_err(&idtcm->client->dev,
1299 "%s - Unsupported out%d", __func__, outn);
1303 err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1308 val |= SQUELCH_DISABLE;
1310 val &= ~SQUELCH_DISABLE;
1312 return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1315 static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1322 mask = channel->output_mask;
1327 err = idtcm_output_enable(channel, enable, outn);
1339 static int idtcm_perout_enable(struct idtcm_channel *channel,
1341 struct ptp_perout_request *perout)
1343 struct idtcm *idtcm = channel->idtcm;
1344 unsigned int flags = perout->flags;
1345 struct timespec64 ts = {0, 0};
1348 if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1349 err = idtcm_output_mask_enable(channel, enable);
1351 err = idtcm_output_enable(channel, enable, perout->index);
1354 dev_err(&idtcm->client->dev, "Unable to set output enable");
1358 /* Align output to internal 1 PPS */
1359 return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS);
1362 static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1363 enum pll_mode *pll_mode)
1365 struct idtcm *idtcm = channel->idtcm;
1369 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1370 &dpll_mode, sizeof(dpll_mode));
1374 *pll_mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1379 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1380 enum pll_mode pll_mode)
1382 struct idtcm *idtcm = channel->idtcm;
1386 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1387 &dpll_mode, sizeof(dpll_mode));
1391 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1393 dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1395 channel->pll_mode = pll_mode;
1397 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1398 &dpll_mode, sizeof(dpll_mode));
1405 /* PTP Hardware Clock interface */
1408 * Maximum absolute value for write phase offset in picoseconds
1410 * Destination signed register is 32-bit register in resolution of 50ps
1412 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1414 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1416 struct idtcm *idtcm = channel->idtcm;
1423 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1424 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1429 offset_ps = (s64)delta_ns * 1000;
1432 * Check for 32-bit signed max * 50:
1434 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1436 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1437 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1438 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1439 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1441 phase_50ps = div_s64(offset_ps, 50);
1443 for (i = 0; i < 4; i++) {
1444 buf[i] = phase_50ps & 0xff;
1448 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1454 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1456 struct idtcm *idtcm = channel->idtcm;
1462 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
1463 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1469 * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1478 * FCW = -------------
1482 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1483 fcw = scaled_ppm * 244140625ULL;
1485 fcw = div_s64(fcw, 1776);
1487 for (i = 0; i < 6; i++) {
1488 buf[i] = fcw & 0xff;
1492 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1498 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1500 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1501 struct idtcm *idtcm = channel->idtcm;
1504 mutex_lock(&idtcm->reg_lock);
1506 err = _idtcm_gettime(channel, ts);
1508 dev_err(&idtcm->client->dev, "Failed at line %d in %s!",
1509 __LINE__, __func__);
1511 mutex_unlock(&idtcm->reg_lock);
1516 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1517 const struct timespec64 *ts)
1519 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1520 struct idtcm *idtcm = channel->idtcm;
1523 mutex_lock(&idtcm->reg_lock);
1525 err = _idtcm_settime_deprecated(channel, ts);
1527 dev_err(&idtcm->client->dev,
1528 "Failed at line %d in %s!", __LINE__, __func__);
1530 mutex_unlock(&idtcm->reg_lock);
1535 static int idtcm_settime(struct ptp_clock_info *ptp,
1536 const struct timespec64 *ts)
1538 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1539 struct idtcm *idtcm = channel->idtcm;
1542 mutex_lock(&idtcm->reg_lock);
1544 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1546 dev_err(&idtcm->client->dev,
1547 "Failed at line %d in %s!", __LINE__, __func__);
1549 mutex_unlock(&idtcm->reg_lock);
1554 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
1556 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1557 struct idtcm *idtcm = channel->idtcm;
1560 mutex_lock(&idtcm->reg_lock);
1562 err = _idtcm_adjtime_deprecated(channel, delta);
1564 dev_err(&idtcm->client->dev,
1565 "Failed at line %d in %s!", __LINE__, __func__);
1567 mutex_unlock(&idtcm->reg_lock);
1572 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1574 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1575 struct idtcm *idtcm = channel->idtcm;
1576 struct timespec64 ts;
1577 enum scsr_tod_write_type_sel type;
1580 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
1581 err = idtcm_do_phase_pull_in(channel, delta, 0);
1583 dev_err(&idtcm->client->dev,
1584 "Failed at line %d in %s!", __LINE__, __func__);
1589 ts = ns_to_timespec64(delta);
1590 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1592 ts = ns_to_timespec64(-delta);
1593 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1596 mutex_lock(&idtcm->reg_lock);
1598 err = _idtcm_settime(channel, &ts, type);
1600 dev_err(&idtcm->client->dev,
1601 "Failed at line %d in %s!", __LINE__, __func__);
1603 mutex_unlock(&idtcm->reg_lock);
1608 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1610 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1611 struct idtcm *idtcm = channel->idtcm;
1614 mutex_lock(&idtcm->reg_lock);
1616 err = _idtcm_adjphase(channel, delta);
1618 dev_err(&idtcm->client->dev,
1619 "Failed at line %d in %s!", __LINE__, __func__);
1621 mutex_unlock(&idtcm->reg_lock);
1626 static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1628 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1629 struct idtcm *idtcm = channel->idtcm;
1632 mutex_lock(&idtcm->reg_lock);
1634 err = _idtcm_adjfine(channel, scaled_ppm);
1636 dev_err(&idtcm->client->dev,
1637 "Failed at line %d in %s!", __LINE__, __func__);
1639 mutex_unlock(&idtcm->reg_lock);
1644 static int idtcm_enable(struct ptp_clock_info *ptp,
1645 struct ptp_clock_request *rq, int on)
1648 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1651 case PTP_CLK_REQ_PEROUT:
1653 err = idtcm_perout_enable(channel, false, &rq->perout);
1655 dev_err(&channel->idtcm->client->dev,
1656 "Failed at line %d in %s!",
1657 __LINE__, __func__);
1661 /* Only accept a 1-PPS aligned to the second. */
1662 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1663 rq->perout.period.nsec)
1666 err = idtcm_perout_enable(channel, true, &rq->perout);
1668 dev_err(&channel->idtcm->client->dev,
1669 "Failed at line %d in %s!", __LINE__, __func__);
1678 static int _enable_pll_tod_sync(struct idtcm *idtcm,
1687 u16 out0 = 0, out1 = 0;
1689 if (qn == 0 && qn_plus_1 == 0)
1750 * Enable OUTPUT OUT_SYNC.
1753 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1757 val &= ~OUT_SYNC_DISABLE;
1759 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1765 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1769 val &= ~OUT_SYNC_DISABLE;
1771 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1776 /* enable dpll sync tod pps, must be set before dpll_mode */
1777 err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1781 val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1782 val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1785 return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1788 static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1790 struct idtcm *idtcm = channel->idtcm;
1797 u16 output_mask = channel->output_mask;
1803 * set tod_out_sync_enable to 0.
1805 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1809 cfg &= ~TOD_OUT_SYNC_ENABLE;
1811 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1815 switch (channel->tod_n) {
1832 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, &temp, sizeof(temp));
1836 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1837 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1840 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, &temp, sizeof(temp));
1844 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1845 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1848 for (pll = 0; pll < 8; pll++) {
1853 /* First 4 pll has 2 outputs */
1854 qn = output_mask & 0x1;
1855 output_mask = output_mask >> 1;
1856 qn_plus_1 = output_mask & 0x1;
1857 output_mask = output_mask >> 1;
1858 } else if (pll == 4) {
1859 if (out8_mux == 0) {
1860 qn = output_mask & 0x1;
1861 output_mask = output_mask >> 1;
1863 } else if (pll == 5) {
1865 qn_plus_1 = output_mask & 0x1;
1866 output_mask = output_mask >> 1;
1868 qn = output_mask & 0x1;
1869 output_mask = output_mask >> 1;
1870 } else if (pll == 6) {
1871 qn = output_mask & 0x1;
1872 output_mask = output_mask >> 1;
1874 qn_plus_1 = output_mask & 0x1;
1875 output_mask = output_mask >> 1;
1877 } else if (pll == 7) {
1878 if (out11_mux == 0) {
1879 qn = output_mask & 0x1;
1880 output_mask = output_mask >> 1;
1884 if (qn != 0 || qn_plus_1 != 0)
1885 err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1894 static int idtcm_enable_tod(struct idtcm_channel *channel)
1896 struct idtcm *idtcm = channel->idtcm;
1897 struct timespec64 ts = {0, 0};
1902 * Start the TOD clock ticking.
1904 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1910 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1914 if (idtcm->deprecated)
1915 return _idtcm_settime_deprecated(channel, &ts);
1917 return _idtcm_settime(channel, &ts,
1918 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1921 static void idtcm_set_version_info(struct idtcm *idtcm)
1930 idtcm_read_major_release(idtcm, &major);
1931 idtcm_read_minor_release(idtcm, &minor);
1932 idtcm_read_hotfix_release(idtcm, &hotfix);
1934 idtcm_read_product_id(idtcm, &product_id);
1935 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1937 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
1939 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
1940 major, minor, hotfix);
1942 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
1943 idtcm->deprecated = 0;
1945 idtcm->deprecated = 1;
1947 dev_info(&idtcm->client->dev,
1948 "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d",
1949 major, minor, hotfix,
1950 product_id, hw_rev_id, config_select);
1953 static const struct ptp_clock_info idtcm_caps = {
1954 .owner = THIS_MODULE,
1957 .adjphase = &idtcm_adjphase,
1958 .adjfine = &idtcm_adjfine,
1959 .adjtime = &idtcm_adjtime,
1960 .gettime64 = &idtcm_gettime,
1961 .settime64 = &idtcm_settime,
1962 .enable = &idtcm_enable,
1965 static const struct ptp_clock_info idtcm_caps_deprecated = {
1966 .owner = THIS_MODULE,
1969 .adjphase = &idtcm_adjphase,
1970 .adjfine = &idtcm_adjfine,
1971 .adjtime = &idtcm_adjtime_deprecated,
1972 .gettime64 = &idtcm_gettime,
1973 .settime64 = &idtcm_settime_deprecated,
1974 .enable = &idtcm_enable,
1977 static int configure_channel_pll(struct idtcm_channel *channel)
1981 switch (channel->pll) {
1983 channel->dpll_freq = DPLL_FREQ_0;
1984 channel->dpll_n = DPLL_0;
1985 channel->hw_dpll_n = HW_DPLL_0;
1986 channel->dpll_phase = DPLL_PHASE_0;
1987 channel->dpll_ctrl_n = DPLL_CTRL_0;
1988 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
1991 channel->dpll_freq = DPLL_FREQ_1;
1992 channel->dpll_n = DPLL_1;
1993 channel->hw_dpll_n = HW_DPLL_1;
1994 channel->dpll_phase = DPLL_PHASE_1;
1995 channel->dpll_ctrl_n = DPLL_CTRL_1;
1996 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
1999 channel->dpll_freq = DPLL_FREQ_2;
2000 channel->dpll_n = DPLL_2;
2001 channel->hw_dpll_n = HW_DPLL_2;
2002 channel->dpll_phase = DPLL_PHASE_2;
2003 channel->dpll_ctrl_n = DPLL_CTRL_2;
2004 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2007 channel->dpll_freq = DPLL_FREQ_3;
2008 channel->dpll_n = DPLL_3;
2009 channel->hw_dpll_n = HW_DPLL_3;
2010 channel->dpll_phase = DPLL_PHASE_3;
2011 channel->dpll_ctrl_n = DPLL_CTRL_3;
2012 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2015 channel->dpll_freq = DPLL_FREQ_4;
2016 channel->dpll_n = DPLL_4;
2017 channel->hw_dpll_n = HW_DPLL_4;
2018 channel->dpll_phase = DPLL_PHASE_4;
2019 channel->dpll_ctrl_n = DPLL_CTRL_4;
2020 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2023 channel->dpll_freq = DPLL_FREQ_5;
2024 channel->dpll_n = DPLL_5;
2025 channel->hw_dpll_n = HW_DPLL_5;
2026 channel->dpll_phase = DPLL_PHASE_5;
2027 channel->dpll_ctrl_n = DPLL_CTRL_5;
2028 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2031 channel->dpll_freq = DPLL_FREQ_6;
2032 channel->dpll_n = DPLL_6;
2033 channel->hw_dpll_n = HW_DPLL_6;
2034 channel->dpll_phase = DPLL_PHASE_6;
2035 channel->dpll_ctrl_n = DPLL_CTRL_6;
2036 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2039 channel->dpll_freq = DPLL_FREQ_7;
2040 channel->dpll_n = DPLL_7;
2041 channel->hw_dpll_n = HW_DPLL_7;
2042 channel->dpll_phase = DPLL_PHASE_7;
2043 channel->dpll_ctrl_n = DPLL_CTRL_7;
2044 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2053 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2055 struct idtcm_channel *channel;
2058 if (!(index < MAX_TOD))
2061 channel = &idtcm->channel[index];
2063 /* Set pll addresses */
2064 err = configure_channel_pll(channel);
2068 /* Set tod addresses */
2071 channel->tod_read_primary = TOD_READ_PRIMARY_0;
2072 channel->tod_write = TOD_WRITE_0;
2073 channel->tod_n = TOD_0;
2076 channel->tod_read_primary = TOD_READ_PRIMARY_1;
2077 channel->tod_write = TOD_WRITE_1;
2078 channel->tod_n = TOD_1;
2081 channel->tod_read_primary = TOD_READ_PRIMARY_2;
2082 channel->tod_write = TOD_WRITE_2;
2083 channel->tod_n = TOD_2;
2086 channel->tod_read_primary = TOD_READ_PRIMARY_3;
2087 channel->tod_write = TOD_WRITE_3;
2088 channel->tod_n = TOD_3;
2094 channel->idtcm = idtcm;
2096 if (idtcm->deprecated)
2097 channel->caps = idtcm_caps_deprecated;
2099 channel->caps = idtcm_caps;
2101 snprintf(channel->caps.name, sizeof(channel->caps.name),
2102 "IDT CM TOD%u", index);
2104 if (!idtcm->deprecated) {
2105 err = idtcm_enable_tod_sync(channel);
2107 dev_err(&idtcm->client->dev,
2108 "Failed at line %d in %s!", __LINE__, __func__);
2113 /* Sync pll mode with hardware */
2114 err = idtcm_get_pll_mode(channel, &channel->pll_mode);
2116 dev_err(&idtcm->client->dev,
2117 "Error: %s - Unable to read pll mode", __func__);
2121 err = idtcm_enable_tod(channel);
2123 dev_err(&idtcm->client->dev,
2124 "Failed at line %d in %s!", __LINE__, __func__);
2128 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2130 if (IS_ERR(channel->ptp_clock)) {
2131 err = PTR_ERR(channel->ptp_clock);
2132 channel->ptp_clock = NULL;
2136 if (!channel->ptp_clock)
2139 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d",
2140 index, channel->ptp_clock->index);
2145 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2148 struct idtcm_channel *channel;
2150 for (i = 0; i < MAX_TOD; i++) {
2151 channel = &idtcm->channel[i];
2153 if (channel->ptp_clock)
2154 ptp_clock_unregister(channel->ptp_clock);
2158 static void set_default_masks(struct idtcm *idtcm)
2160 idtcm->tod_mask = DEFAULT_TOD_MASK;
2162 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2163 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2164 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2165 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2167 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2168 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2169 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2170 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2173 static int idtcm_probe(struct i2c_client *client,
2174 const struct i2c_device_id *id)
2176 struct idtcm *idtcm;
2180 /* Unused for now */
2183 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2188 idtcm->client = client;
2189 idtcm->page_offset = 0xff;
2190 idtcm->calculate_overhead_flag = 0;
2192 set_default_masks(idtcm);
2194 mutex_init(&idtcm->reg_lock);
2195 mutex_lock(&idtcm->reg_lock);
2197 idtcm_set_version_info(idtcm);
2199 err = idtcm_load_firmware(idtcm, &client->dev);
2201 dev_warn(&idtcm->client->dev, "loading firmware failed with %d", err);
2203 wait_for_chip_ready(idtcm);
2205 if (idtcm->tod_mask) {
2206 for (i = 0; i < MAX_TOD; i++) {
2207 if (idtcm->tod_mask & (1 << i)) {
2208 err = idtcm_enable_channel(idtcm, i);
2210 dev_err(&idtcm->client->dev,
2211 "idtcm_enable_channel %d failed!", i);
2217 dev_err(&idtcm->client->dev,
2218 "no PLLs flagged as PHCs, nothing to do");
2222 mutex_unlock(&idtcm->reg_lock);
2225 ptp_clock_unregister_all(idtcm);
2229 i2c_set_clientdata(client, idtcm);
2234 static int idtcm_remove(struct i2c_client *client)
2236 struct idtcm *idtcm = i2c_get_clientdata(client);
2238 ptp_clock_unregister_all(idtcm);
2240 mutex_destroy(&idtcm->reg_lock);
2246 static const struct of_device_id idtcm_dt_id[] = {
2247 { .compatible = "idt,8a34000" },
2248 { .compatible = "idt,8a34001" },
2249 { .compatible = "idt,8a34002" },
2250 { .compatible = "idt,8a34003" },
2251 { .compatible = "idt,8a34004" },
2252 { .compatible = "idt,8a34005" },
2253 { .compatible = "idt,8a34006" },
2254 { .compatible = "idt,8a34007" },
2255 { .compatible = "idt,8a34008" },
2256 { .compatible = "idt,8a34009" },
2257 { .compatible = "idt,8a34010" },
2258 { .compatible = "idt,8a34011" },
2259 { .compatible = "idt,8a34012" },
2260 { .compatible = "idt,8a34013" },
2261 { .compatible = "idt,8a34014" },
2262 { .compatible = "idt,8a34015" },
2263 { .compatible = "idt,8a34016" },
2264 { .compatible = "idt,8a34017" },
2265 { .compatible = "idt,8a34018" },
2266 { .compatible = "idt,8a34019" },
2267 { .compatible = "idt,8a34040" },
2268 { .compatible = "idt,8a34041" },
2269 { .compatible = "idt,8a34042" },
2270 { .compatible = "idt,8a34043" },
2271 { .compatible = "idt,8a34044" },
2272 { .compatible = "idt,8a34045" },
2273 { .compatible = "idt,8a34046" },
2274 { .compatible = "idt,8a34047" },
2275 { .compatible = "idt,8a34048" },
2276 { .compatible = "idt,8a34049" },
2279 MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2282 static const struct i2c_device_id idtcm_i2c_id[] = {
2315 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2317 static struct i2c_driver idtcm_driver = {
2319 .of_match_table = of_match_ptr(idtcm_dt_id),
2322 .probe = idtcm_probe,
2323 .remove = idtcm_remove,
2324 .id_table = idtcm_i2c_id,
2327 module_i2c_driver(idtcm_driver);