Merge tag 'ntfs3_for_5.15' of git://github.com/Paragon-Software-Group/linux-ntfs3
[platform/kernel/linux-rpi.git] / drivers / ptp / ptp_clockmatrix.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4  * synchronization devices.
5  *
6  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
7  */
8 #include <linux/firmware.h>
9 #include <linux/i2c.h>
10 #include <linux/module.h>
11 #include <linux/ptp_clock_kernel.h>
12 #include <linux/delay.h>
13 #include <linux/jiffies.h>
14 #include <linux/kernel.h>
15 #include <linux/timekeeping.h>
16 #include <linux/string.h>
17
18 #include "ptp_private.h"
19 #include "ptp_clockmatrix.h"
20
21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
24 MODULE_VERSION("1.0");
25 MODULE_LICENSE("GPL");
26
27 /*
28  * The name of the firmware file to be loaded
29  * over-rides any automatic selection
30  */
31 static char *firmware;
32 module_param(firmware, charp, 0);
33
34 #define SETTIME_CORRECTION (0)
35
36 static int contains_full_configuration(const struct firmware *fw)
37 {
38         s32 full_count = FULL_FW_CFG_BYTES - FULL_FW_CFG_SKIPPED_BYTES;
39         struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
40         s32 count = 0;
41         u16 regaddr;
42         u8 loaddr;
43         s32 len;
44
45         /* If the firmware contains 'full configuration' SM_RESET can be used
46          * to ensure proper configuration.
47          *
48          * Full configuration is defined as the number of programmable
49          * bytes within the configuration range minus page offset addr range.
50          */
51         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
52                 regaddr = rec->hiaddr << 8;
53                 regaddr |= rec->loaddr;
54
55                 loaddr = rec->loaddr;
56
57                 rec++;
58
59                 /* Top (status registers) and bottom are read-only */
60                 if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
61                         continue;
62
63                 /* Page size 128, last 4 bytes of page skipped */
64                 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
65                         continue;
66
67                 count++;
68         }
69
70         return (count >= full_count);
71 }
72
73 static int char_array_to_timespec(u8 *buf,
74                                   u8 count,
75                                   struct timespec64 *ts)
76 {
77         u8 i;
78         u64 nsec;
79         time64_t sec;
80
81         if (count < TOD_BYTE_COUNT)
82                 return 1;
83
84         /* Sub-nanoseconds are in buf[0]. */
85         nsec = buf[4];
86         for (i = 0; i < 3; i++) {
87                 nsec <<= 8;
88                 nsec |= buf[3 - i];
89         }
90
91         sec = buf[10];
92         for (i = 0; i < 5; i++) {
93                 sec <<= 8;
94                 sec |= buf[9 - i];
95         }
96
97         ts->tv_sec = sec;
98         ts->tv_nsec = nsec;
99
100         return 0;
101 }
102
103 static int timespec_to_char_array(struct timespec64 const *ts,
104                                   u8 *buf,
105                                   u8 count)
106 {
107         u8 i;
108         s32 nsec;
109         time64_t sec;
110
111         if (count < TOD_BYTE_COUNT)
112                 return 1;
113
114         nsec = ts->tv_nsec;
115         sec = ts->tv_sec;
116
117         /* Sub-nanoseconds are in buf[0]. */
118         buf[0] = 0;
119         for (i = 1; i < 5; i++) {
120                 buf[i] = nsec & 0xff;
121                 nsec >>= 8;
122         }
123
124         for (i = 5; i < TOD_BYTE_COUNT; i++) {
125
126                 buf[i] = sec & 0xff;
127                 sec >>= 8;
128         }
129
130         return 0;
131 }
132
133 static int idtcm_strverscmp(const char *version1, const char *version2)
134 {
135         u8 ver1[3], ver2[3];
136         int i;
137
138         if (sscanf(version1, "%hhu.%hhu.%hhu",
139                    &ver1[0], &ver1[1], &ver1[2]) != 3)
140                 return -1;
141         if (sscanf(version2, "%hhu.%hhu.%hhu",
142                    &ver2[0], &ver2[1], &ver2[2]) != 3)
143                 return -1;
144
145         for (i = 0; i < 3; i++) {
146                 if (ver1[i] > ver2[i])
147                         return 1;
148                 if (ver1[i] < ver2[i])
149                         return -1;
150         }
151
152         return 0;
153 }
154
155 static int idtcm_xfer_read(struct idtcm *idtcm,
156                            u8 regaddr,
157                            u8 *buf,
158                            u16 count)
159 {
160         struct i2c_client *client = idtcm->client;
161         struct i2c_msg msg[2];
162         int cnt;
163
164         msg[0].addr = client->addr;
165         msg[0].flags = 0;
166         msg[0].len = 1;
167         msg[0].buf = &regaddr;
168
169         msg[1].addr = client->addr;
170         msg[1].flags = I2C_M_RD;
171         msg[1].len = count;
172         msg[1].buf = buf;
173
174         cnt = i2c_transfer(client->adapter, msg, 2);
175
176         if (cnt < 0) {
177                 dev_err(&client->dev,
178                         "i2c_transfer failed at %d in %s, at addr: %04x!",
179                         __LINE__, __func__, regaddr);
180                 return cnt;
181         } else if (cnt != 2) {
182                 dev_err(&client->dev,
183                         "i2c_transfer sent only %d of %d messages", cnt, 2);
184                 return -EIO;
185         }
186
187         return 0;
188 }
189
190 static int idtcm_xfer_write(struct idtcm *idtcm,
191                             u8 regaddr,
192                             u8 *buf,
193                             u16 count)
194 {
195         struct i2c_client *client = idtcm->client;
196         /* we add 1 byte for device register */
197         u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
198         int cnt;
199
200         if (count > IDTCM_MAX_WRITE_COUNT)
201                 return -EINVAL;
202
203         msg[0] = regaddr;
204         memcpy(&msg[1], buf, count);
205
206         cnt = i2c_master_send(client, msg, count + 1);
207
208         if (cnt < 0) {
209                 dev_err(&client->dev,
210                         "i2c_master_send failed at %d in %s, at addr: %04x!",
211                         __LINE__, __func__, regaddr);
212                 return cnt;
213         }
214
215         return 0;
216 }
217
218 static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
219 {
220         u8 buf[4];
221         int err;
222
223         if (idtcm->page_offset == val)
224                 return 0;
225
226         buf[0] = 0x0;
227         buf[1] = val;
228         buf[2] = 0x10;
229         buf[3] = 0x20;
230
231         err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
232         if (err) {
233                 idtcm->page_offset = 0xff;
234                 dev_err(&idtcm->client->dev, "failed to set page offset");
235         } else {
236                 idtcm->page_offset = val;
237         }
238
239         return err;
240 }
241
242 static int _idtcm_rdwr(struct idtcm *idtcm,
243                        u16 regaddr,
244                        u8 *buf,
245                        u16 count,
246                        bool write)
247 {
248         u8 hi;
249         u8 lo;
250         int err;
251
252         hi = (regaddr >> 8) & 0xff;
253         lo = regaddr & 0xff;
254
255         err = idtcm_page_offset(idtcm, hi);
256         if (err)
257                 return err;
258
259         if (write)
260                 return idtcm_xfer_write(idtcm, lo, buf, count);
261
262         return idtcm_xfer_read(idtcm, lo, buf, count);
263 }
264
265 static int idtcm_read(struct idtcm *idtcm,
266                       u16 module,
267                       u16 regaddr,
268                       u8 *buf,
269                       u16 count)
270 {
271         return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
272 }
273
274 static int idtcm_write(struct idtcm *idtcm,
275                        u16 module,
276                        u16 regaddr,
277                        u8 *buf,
278                        u16 count)
279 {
280         return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
281 }
282
283 static int clear_boot_status(struct idtcm *idtcm)
284 {
285         u8 buf[4] = {0};
286
287         return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
288 }
289
290 static int read_boot_status(struct idtcm *idtcm, u32 *status)
291 {
292         int err;
293         u8 buf[4] = {0};
294
295         err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
296
297         *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
298
299         return err;
300 }
301
302 static int wait_for_boot_status_ready(struct idtcm *idtcm)
303 {
304         u32 status = 0;
305         u8 i = 30;      /* 30 * 100ms = 3s */
306         int err;
307
308         do {
309                 err = read_boot_status(idtcm, &status);
310                 if (err)
311                         return err;
312
313                 if (status == 0xA0)
314                         return 0;
315
316                 msleep(100);
317                 i--;
318
319         } while (i);
320
321         dev_warn(&idtcm->client->dev, "%s timed out", __func__);
322
323         return -EBUSY;
324 }
325
326 static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
327 {
328         return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
329                           sizeof(u8));
330 }
331
332 static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
333 {
334         return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
335 }
336
337 static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
338 {
339         unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
340         u8 apll = 0;
341         u8 dpll = 0;
342         int err;
343
344         do {
345                 err = read_sys_apll_status(idtcm, &apll);
346                 if (err)
347                         return err;
348
349                 err = read_sys_dpll_status(idtcm, &dpll);
350                 if (err)
351                         return err;
352
353                 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
354                 dpll &= DPLL_SYS_STATE_MASK;
355
356                 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
357                     dpll == DPLL_STATE_LOCKED) {
358                         return 0;
359                 } else if (dpll == DPLL_STATE_FREERUN ||
360                            dpll == DPLL_STATE_HOLDOVER ||
361                            dpll == DPLL_STATE_OPEN_LOOP) {
362                         dev_warn(&idtcm->client->dev,
363                                 "No wait state: DPLL_SYS_STATE %d", dpll);
364                         return -EPERM;
365                 }
366
367                 msleep(LOCK_POLL_INTERVAL_MS);
368         } while (time_is_after_jiffies(timeout));
369
370         dev_warn(&idtcm->client->dev,
371                  "%d ms lock timeout: SYS APLL Loss Lock %d  SYS DPLL state %d",
372                  LOCK_TIMEOUT_MS, apll, dpll);
373
374         return -ETIME;
375 }
376
377 static void wait_for_chip_ready(struct idtcm *idtcm)
378 {
379         if (wait_for_boot_status_ready(idtcm))
380                 dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0");
381
382         if (wait_for_sys_apll_dpll_lock(idtcm))
383                 dev_warn(&idtcm->client->dev,
384                          "Continuing while SYS APLL/DPLL is not locked");
385 }
386
387 static int _idtcm_gettime(struct idtcm_channel *channel,
388                           struct timespec64 *ts)
389 {
390         struct idtcm *idtcm = channel->idtcm;
391         u8 buf[TOD_BYTE_COUNT];
392         u8 timeout = 10;
393         u8 trigger;
394         int err;
395
396         err = idtcm_read(idtcm, channel->tod_read_primary,
397                          TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
398         if (err)
399                 return err;
400
401         trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
402         trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
403         trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
404
405         err = idtcm_write(idtcm, channel->tod_read_primary,
406                           TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
407         if (err)
408                 return err;
409
410         /* wait trigger to be 0 */
411         while (trigger & TOD_READ_TRIGGER_MASK) {
412                 if (idtcm->calculate_overhead_flag)
413                         idtcm->start_time = ktime_get_raw();
414
415                 err = idtcm_read(idtcm, channel->tod_read_primary,
416                                  TOD_READ_PRIMARY_CMD, &trigger,
417                                  sizeof(trigger));
418                 if (err)
419                         return err;
420
421                 if (--timeout == 0)
422                         return -EIO;
423         }
424
425         err = idtcm_read(idtcm, channel->tod_read_primary,
426                          TOD_READ_PRIMARY, buf, sizeof(buf));
427         if (err)
428                 return err;
429
430         err = char_array_to_timespec(buf, sizeof(buf), ts);
431
432         return err;
433 }
434
435 static int _sync_pll_output(struct idtcm *idtcm,
436                             u8 pll,
437                             u8 sync_src,
438                             u8 qn,
439                             u8 qn_plus_1)
440 {
441         int err;
442         u8 val;
443         u16 sync_ctrl0;
444         u16 sync_ctrl1;
445         u8 temp;
446
447         if (qn == 0 && qn_plus_1 == 0)
448                 return 0;
449
450         switch (pll) {
451         case 0:
452                 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
453                 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
454                 break;
455         case 1:
456                 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
457                 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
458                 break;
459         case 2:
460                 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
461                 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
462                 break;
463         case 3:
464                 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
465                 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
466                 break;
467         case 4:
468                 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
469                 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
470                 break;
471         case 5:
472                 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
473                 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
474                 break;
475         case 6:
476                 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
477                 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
478                 break;
479         case 7:
480                 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
481                 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
482                 break;
483         default:
484                 return -EINVAL;
485         }
486
487         val = SYNCTRL1_MASTER_SYNC_RST;
488
489         /* Place master sync in reset */
490         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
491         if (err)
492                 return err;
493
494         err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
495         if (err)
496                 return err;
497
498         /* Set sync trigger mask */
499         val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
500
501         if (qn)
502                 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
503
504         if (qn_plus_1)
505                 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
506
507         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
508         if (err)
509                 return err;
510
511         /* PLL5 can have OUT8 as second additional output. */
512         if (pll == 5 && qn_plus_1 != 0) {
513                 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
514                                  &temp, sizeof(temp));
515                 if (err)
516                         return err;
517
518                 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
519
520                 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
521                                   &temp, sizeof(temp));
522                 if (err)
523                         return err;
524
525                 temp |= Q9_TO_Q8_SYNC_TRIG;
526
527                 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
528                                   &temp, sizeof(temp));
529                 if (err)
530                         return err;
531         }
532
533         /* PLL6 can have OUT11 as second additional output. */
534         if (pll == 6 && qn_plus_1 != 0) {
535                 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
536                                  &temp, sizeof(temp));
537                 if (err)
538                         return err;
539
540                 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
541
542                 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
543                                   &temp, sizeof(temp));
544                 if (err)
545                         return err;
546
547                 temp |= Q10_TO_Q11_SYNC_TRIG;
548
549                 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
550                                   &temp, sizeof(temp));
551                 if (err)
552                         return err;
553         }
554
555         /* Place master sync out of reset */
556         val &= ~(SYNCTRL1_MASTER_SYNC_RST);
557         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
558
559         return err;
560 }
561
562 static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
563 {
564         int err = 0;
565
566         switch (tod_addr) {
567         case TOD_0:
568                 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
569                 break;
570         case TOD_1:
571                 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
572                 break;
573         case TOD_2:
574                 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
575                 break;
576         case TOD_3:
577                 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
578                 break;
579         default:
580                 err = -EINVAL;
581         }
582
583         return err;
584 }
585
586 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
587 {
588         struct idtcm *idtcm = channel->idtcm;
589         u8 pll;
590         u8 sync_src;
591         u8 qn;
592         u8 qn_plus_1;
593         int err = 0;
594         u8 out8_mux = 0;
595         u8 out11_mux = 0;
596         u8 temp;
597         u16 output_mask = channel->output_mask;
598
599         err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
600         if (err)
601                 return err;
602
603         err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
604                          &temp, sizeof(temp));
605         if (err)
606                 return err;
607
608         if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
609             Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
610                 out8_mux = 1;
611
612         err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
613                          &temp, sizeof(temp));
614         if (err)
615                 return err;
616
617         if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
618             Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
619                 out11_mux = 1;
620
621         for (pll = 0; pll < 8; pll++) {
622                 qn = 0;
623                 qn_plus_1 = 0;
624
625                 if (pll < 4) {
626                         /* First 4 pll has 2 outputs */
627                         qn = output_mask & 0x1;
628                         output_mask = output_mask >> 1;
629                         qn_plus_1 = output_mask & 0x1;
630                         output_mask = output_mask >> 1;
631                 } else if (pll == 4) {
632                         if (out8_mux == 0) {
633                                 qn = output_mask & 0x1;
634                                 output_mask = output_mask >> 1;
635                         }
636                 } else if (pll == 5) {
637                         if (out8_mux) {
638                                 qn_plus_1 = output_mask & 0x1;
639                                 output_mask = output_mask >> 1;
640                         }
641                         qn = output_mask & 0x1;
642                         output_mask = output_mask >> 1;
643                 } else if (pll == 6) {
644                         qn = output_mask & 0x1;
645                         output_mask = output_mask >> 1;
646                         if (out11_mux) {
647                                 qn_plus_1 = output_mask & 0x1;
648                                 output_mask = output_mask >> 1;
649                         }
650                 } else if (pll == 7) {
651                         if (out11_mux == 0) {
652                                 qn = output_mask & 0x1;
653                                 output_mask = output_mask >> 1;
654                         }
655                 }
656
657                 if (qn != 0 || qn_plus_1 != 0)
658                         err = _sync_pll_output(idtcm, pll, sync_src, qn,
659                                                qn_plus_1);
660
661                 if (err)
662                         return err;
663         }
664
665         return err;
666 }
667
668 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
669                                struct timespec64 const *ts,
670                                enum hw_tod_write_trig_sel wr_trig)
671 {
672         struct idtcm *idtcm = channel->idtcm;
673         u8 buf[TOD_BYTE_COUNT];
674         u8 cmd;
675         int err;
676         struct timespec64 local_ts = *ts;
677         s64 total_overhead_ns;
678
679         /* Configure HW TOD write trigger. */
680         err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
681                          &cmd, sizeof(cmd));
682         if (err)
683                 return err;
684
685         cmd &= ~(0x0f);
686         cmd |= wr_trig | 0x08;
687
688         err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
689                           &cmd, sizeof(cmd));
690         if (err)
691                 return err;
692
693         if (wr_trig  != HW_TOD_WR_TRIG_SEL_MSB) {
694                 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
695                 if (err)
696                         return err;
697
698                 err = idtcm_write(idtcm, channel->hw_dpll_n,
699                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
700                 if (err)
701                         return err;
702         }
703
704         /* ARM HW TOD write trigger. */
705         cmd &= ~(0x08);
706
707         err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
708                           &cmd, sizeof(cmd));
709
710         if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
711                 if (idtcm->calculate_overhead_flag) {
712                         /* Assumption: I2C @ 400KHz */
713                         ktime_t diff = ktime_sub(ktime_get_raw(),
714                                                  idtcm->start_time);
715                         total_overhead_ns =  ktime_to_ns(diff)
716                                              + idtcm->tod_write_overhead_ns
717                                              + SETTIME_CORRECTION;
718
719                         timespec64_add_ns(&local_ts, total_overhead_ns);
720
721                         idtcm->calculate_overhead_flag = 0;
722                 }
723
724                 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
725                 if (err)
726                         return err;
727
728                 err = idtcm_write(idtcm, channel->hw_dpll_n,
729                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
730         }
731
732         return err;
733 }
734
735 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
736                                     struct timespec64 const *ts,
737                                     enum scsr_tod_write_trig_sel wr_trig,
738                                     enum scsr_tod_write_type_sel wr_type)
739 {
740         struct idtcm *idtcm = channel->idtcm;
741         unsigned char buf[TOD_BYTE_COUNT], cmd;
742         struct timespec64 local_ts = *ts;
743         int err, count = 0;
744
745         timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
746
747         err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
748         if (err)
749                 return err;
750
751         err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
752                           buf, sizeof(buf));
753         if (err)
754                 return err;
755
756         /* Trigger the write operation. */
757         err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
758                          &cmd, sizeof(cmd));
759         if (err)
760                 return err;
761
762         cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
763         cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
764         cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
765         cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
766
767         err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
768                            &cmd, sizeof(cmd));
769         if (err)
770                 return err;
771
772         /* Wait for the operation to complete. */
773         while (1) {
774                 /* pps trigger takes up to 1 sec to complete */
775                 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
776                         msleep(50);
777
778                 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
779                                  &cmd, sizeof(cmd));
780                 if (err)
781                         return err;
782
783                 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
784                         break;
785
786                 if (++count > 20) {
787                         dev_err(&idtcm->client->dev,
788                                 "Timed out waiting for the write counter");
789                         return -EIO;
790                 }
791         }
792
793         return 0;
794 }
795
796 static int get_output_base_addr(u8 outn)
797 {
798         int base;
799
800         switch (outn) {
801         case 0:
802                 base = OUTPUT_0;
803                 break;
804         case 1:
805                 base = OUTPUT_1;
806                 break;
807         case 2:
808                 base = OUTPUT_2;
809                 break;
810         case 3:
811                 base = OUTPUT_3;
812                 break;
813         case 4:
814                 base = OUTPUT_4;
815                 break;
816         case 5:
817                 base = OUTPUT_5;
818                 break;
819         case 6:
820                 base = OUTPUT_6;
821                 break;
822         case 7:
823                 base = OUTPUT_7;
824                 break;
825         case 8:
826                 base = OUTPUT_8;
827                 break;
828         case 9:
829                 base = OUTPUT_9;
830                 break;
831         case 10:
832                 base = OUTPUT_10;
833                 break;
834         case 11:
835                 base = OUTPUT_11;
836                 break;
837         default:
838                 base = -EINVAL;
839         }
840
841         return base;
842 }
843
844 static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
845                                      struct timespec64 const *ts)
846 {
847         struct idtcm *idtcm = channel->idtcm;
848         int err;
849
850         err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
851         if (err) {
852                 dev_err(&idtcm->client->dev,
853                         "%s: Set HW ToD failed", __func__);
854                 return err;
855         }
856
857         return idtcm_sync_pps_output(channel);
858 }
859
860 static int _idtcm_settime(struct idtcm_channel *channel,
861                           struct timespec64 const *ts,
862                           enum scsr_tod_write_type_sel wr_type)
863 {
864         return _idtcm_set_dpll_scsr_tod(channel, ts,
865                                         SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
866                                         wr_type);
867 }
868
869 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
870                                           s32 offset_ns)
871 {
872         int err;
873         int i;
874         struct idtcm *idtcm = channel->idtcm;
875         u8 buf[4];
876
877         for (i = 0; i < 4; i++) {
878                 buf[i] = 0xff & (offset_ns);
879                 offset_ns >>= 8;
880         }
881
882         err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
883                           buf, sizeof(buf));
884
885         return err;
886 }
887
888 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
889                                                u32 max_ffo_ppb)
890 {
891         int err;
892         u8 i;
893         struct idtcm *idtcm = channel->idtcm;
894         u8 buf[3];
895
896         if (max_ffo_ppb & 0xff000000)
897                 max_ffo_ppb = 0;
898
899         for (i = 0; i < 3; i++) {
900                 buf[i] = 0xff & (max_ffo_ppb);
901                 max_ffo_ppb >>= 8;
902         }
903
904         err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
905                           PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
906
907         return err;
908 }
909
910 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
911 {
912         int err;
913         struct idtcm *idtcm = channel->idtcm;
914         u8 buf;
915
916         err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
917                          &buf, sizeof(buf));
918         if (err)
919                 return err;
920
921         if (buf == 0) {
922                 buf = 0x01;
923                 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
924                                   PULL_IN_CTRL, &buf, sizeof(buf));
925         } else {
926                 err = -EBUSY;
927         }
928
929         return err;
930 }
931
932 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
933                                   s32 offset_ns,
934                                   u32 max_ffo_ppb)
935 {
936         int err;
937
938         err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
939         if (err)
940                 return err;
941
942         err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
943         if (err)
944                 return err;
945
946         err = idtcm_start_phase_pull_in(channel);
947
948         return err;
949 }
950
951 static int set_tod_write_overhead(struct idtcm_channel *channel)
952 {
953         struct idtcm *idtcm = channel->idtcm;
954         s64 current_ns = 0;
955         s64 lowest_ns = 0;
956         int err;
957         u8 i;
958         ktime_t start;
959         ktime_t stop;
960         ktime_t diff;
961
962         char buf[TOD_BYTE_COUNT] = {0};
963
964         /* Set page offset */
965         idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
966                     buf, sizeof(buf));
967
968         for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
969                 start = ktime_get_raw();
970
971                 err = idtcm_write(idtcm, channel->hw_dpll_n,
972                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
973                 if (err)
974                         return err;
975
976                 stop = ktime_get_raw();
977
978                 diff = ktime_sub(stop, start);
979
980                 current_ns = ktime_to_ns(diff);
981
982                 if (i == 0) {
983                         lowest_ns = current_ns;
984                 } else {
985                         if (current_ns < lowest_ns)
986                                 lowest_ns = current_ns;
987                 }
988         }
989
990         idtcm->tod_write_overhead_ns = lowest_ns;
991
992         return err;
993 }
994
995 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
996 {
997         int err;
998         struct idtcm *idtcm = channel->idtcm;
999         struct timespec64 ts;
1000         s64 now;
1001
1002         if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
1003                 err = idtcm_do_phase_pull_in(channel, delta, 0);
1004         } else {
1005                 idtcm->calculate_overhead_flag = 1;
1006
1007                 err = set_tod_write_overhead(channel);
1008                 if (err)
1009                         return err;
1010
1011                 err = _idtcm_gettime(channel, &ts);
1012                 if (err)
1013                         return err;
1014
1015                 now = timespec64_to_ns(&ts);
1016                 now += delta;
1017
1018                 ts = ns_to_timespec64(now);
1019
1020                 err = _idtcm_settime_deprecated(channel, &ts);
1021         }
1022
1023         return err;
1024 }
1025
1026 static int idtcm_state_machine_reset(struct idtcm *idtcm)
1027 {
1028         u8 byte = SM_RESET_CMD;
1029         u32 status = 0;
1030         int err;
1031         u8 i;
1032
1033         clear_boot_status(idtcm);
1034
1035         err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
1036
1037         if (!err) {
1038                 for (i = 0; i < 30; i++) {
1039                         msleep_interruptible(100);
1040                         read_boot_status(idtcm, &status);
1041
1042                         if (status == 0xA0) {
1043                                 dev_dbg(&idtcm->client->dev,
1044                                         "SM_RESET completed in %d ms", i * 100);
1045                                 break;
1046                         }
1047                 }
1048
1049                 if (!status)
1050                         dev_err(&idtcm->client->dev,
1051                                 "Timed out waiting for CM_RESET to complete");
1052         }
1053
1054         return err;
1055 }
1056
1057 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1058 {
1059         return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
1060 }
1061
1062 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1063 {
1064         int err;
1065         u8 buf[2] = {0};
1066
1067         err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1068
1069         *product_id = (buf[1] << 8) | buf[0];
1070
1071         return err;
1072 }
1073
1074 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1075 {
1076         int err;
1077         u8 buf = 0;
1078
1079         err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1080
1081         *major = buf >> 1;
1082
1083         return err;
1084 }
1085
1086 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1087 {
1088         return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1089 }
1090
1091 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1092 {
1093         return idtcm_read(idtcm,
1094                           GENERAL_STATUS,
1095                           HOTFIX_REL,
1096                           hotfix,
1097                           sizeof(u8));
1098 }
1099
1100 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1101                                              u8 *config_select)
1102 {
1103         return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1104                           config_select, sizeof(u8));
1105 }
1106
1107 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1108 {
1109         int err = 0;
1110
1111         switch (addr) {
1112         case TOD0_OUT_ALIGN_MASK_ADDR:
1113                 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1114                 break;
1115         case TOD0_OUT_ALIGN_MASK_ADDR + 1:
1116                 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1117                 break;
1118         case TOD1_OUT_ALIGN_MASK_ADDR:
1119                 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1120                 break;
1121         case TOD1_OUT_ALIGN_MASK_ADDR + 1:
1122                 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1123                 break;
1124         case TOD2_OUT_ALIGN_MASK_ADDR:
1125                 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1126                 break;
1127         case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1128                 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1129                 break;
1130         case TOD3_OUT_ALIGN_MASK_ADDR:
1131                 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1132                 break;
1133         case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1134                 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1135                 break;
1136         default:
1137                 err = -EFAULT; /* Bad address */;
1138                 break;
1139         }
1140
1141         return err;
1142 }
1143
1144 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1145 {
1146         if (index >= MAX_TOD) {
1147                 dev_err(&idtcm->client->dev, "ToD%d not supported", index);
1148                 return -EINVAL;
1149         }
1150
1151         if (pll >= MAX_PLL) {
1152                 dev_err(&idtcm->client->dev, "Pll%d not supported", pll);
1153                 return -EINVAL;
1154         }
1155
1156         idtcm->channel[index].pll = pll;
1157
1158         return 0;
1159 }
1160
1161 static int check_and_set_masks(struct idtcm *idtcm,
1162                                u16 regaddr,
1163                                u8 val)
1164 {
1165         int err = 0;
1166
1167         switch (regaddr) {
1168         case TOD_MASK_ADDR:
1169                 if ((val & 0xf0) || !(val & 0x0f)) {
1170                         dev_err(&idtcm->client->dev, "Invalid TOD mask 0x%02x", val);
1171                         err = -EINVAL;
1172                 } else {
1173                         idtcm->tod_mask = val;
1174                 }
1175                 break;
1176         case TOD0_PTP_PLL_ADDR:
1177                 err = set_tod_ptp_pll(idtcm, 0, val);
1178                 break;
1179         case TOD1_PTP_PLL_ADDR:
1180                 err = set_tod_ptp_pll(idtcm, 1, val);
1181                 break;
1182         case TOD2_PTP_PLL_ADDR:
1183                 err = set_tod_ptp_pll(idtcm, 2, val);
1184                 break;
1185         case TOD3_PTP_PLL_ADDR:
1186                 err = set_tod_ptp_pll(idtcm, 3, val);
1187                 break;
1188         default:
1189                 err = set_pll_output_mask(idtcm, regaddr, val);
1190                 break;
1191         }
1192
1193         return err;
1194 }
1195
1196 static void display_pll_and_masks(struct idtcm *idtcm)
1197 {
1198         u8 i;
1199         u8 mask;
1200
1201         dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x", idtcm->tod_mask);
1202
1203         for (i = 0; i < MAX_TOD; i++) {
1204                 mask = 1 << i;
1205
1206                 if (mask & idtcm->tod_mask)
1207                         dev_dbg(&idtcm->client->dev,
1208                                 "TOD%d pll = %d    output_mask = 0x%04x",
1209                                 i, idtcm->channel[i].pll,
1210                                 idtcm->channel[i].output_mask);
1211         }
1212 }
1213
1214 static int idtcm_load_firmware(struct idtcm *idtcm,
1215                                struct device *dev)
1216 {
1217         char fname[128] = FW_FILENAME;
1218         const struct firmware *fw;
1219         struct idtcm_fwrc *rec;
1220         u32 regaddr;
1221         int err;
1222         s32 len;
1223         u8 val;
1224         u8 loaddr;
1225
1226         if (firmware) /* module parameter */
1227                 snprintf(fname, sizeof(fname), "%s", firmware);
1228
1229         dev_dbg(&idtcm->client->dev, "requesting firmware '%s'", fname);
1230
1231         err = request_firmware(&fw, fname, dev);
1232         if (err) {
1233                 dev_err(&idtcm->client->dev,
1234                         "Failed at line %d in %s!", __LINE__, __func__);
1235                 return err;
1236         }
1237
1238         dev_dbg(&idtcm->client->dev, "firmware size %zu bytes", fw->size);
1239
1240         rec = (struct idtcm_fwrc *) fw->data;
1241
1242         if (contains_full_configuration(fw))
1243                 idtcm_state_machine_reset(idtcm);
1244
1245         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1246                 if (rec->reserved) {
1247                         dev_err(&idtcm->client->dev,
1248                                 "bad firmware, reserved field non-zero");
1249                         err = -EINVAL;
1250                 } else {
1251                         regaddr = rec->hiaddr << 8;
1252                         regaddr |= rec->loaddr;
1253
1254                         val = rec->value;
1255                         loaddr = rec->loaddr;
1256
1257                         rec++;
1258
1259                         err = check_and_set_masks(idtcm, regaddr, val);
1260                 }
1261
1262                 if (err != -EINVAL) {
1263                         err = 0;
1264
1265                         /* Top (status registers) and bottom are read-only */
1266                         if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
1267                                 continue;
1268
1269                         /* Page size 128, last 4 bytes of page skipped */
1270                         if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
1271                                 continue;
1272
1273                         err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1274                 }
1275
1276                 if (err)
1277                         goto out;
1278         }
1279
1280         display_pll_and_masks(idtcm);
1281
1282 out:
1283         release_firmware(fw);
1284         return err;
1285 }
1286
1287 static int idtcm_output_enable(struct idtcm_channel *channel,
1288                                bool enable, unsigned int outn)
1289 {
1290         struct idtcm *idtcm = channel->idtcm;
1291         int base;
1292         int err;
1293         u8 val;
1294
1295         base = get_output_base_addr(outn);
1296
1297         if (!(base > 0)) {
1298                 dev_err(&idtcm->client->dev,
1299                         "%s - Unsupported out%d", __func__, outn);
1300                 return base;
1301         }
1302
1303         err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1304         if (err)
1305                 return err;
1306
1307         if (enable)
1308                 val |= SQUELCH_DISABLE;
1309         else
1310                 val &= ~SQUELCH_DISABLE;
1311
1312         return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1313 }
1314
1315 static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1316                                     bool enable)
1317 {
1318         u16 mask;
1319         int err;
1320         u8 outn;
1321
1322         mask = channel->output_mask;
1323         outn = 0;
1324
1325         while (mask) {
1326                 if (mask & 0x1) {
1327                         err = idtcm_output_enable(channel, enable, outn);
1328                         if (err)
1329                                 return err;
1330                 }
1331
1332                 mask >>= 0x1;
1333                 outn++;
1334         }
1335
1336         return 0;
1337 }
1338
1339 static int idtcm_perout_enable(struct idtcm_channel *channel,
1340                                bool enable,
1341                                struct ptp_perout_request *perout)
1342 {
1343         struct idtcm *idtcm = channel->idtcm;
1344         unsigned int flags = perout->flags;
1345         struct timespec64 ts = {0, 0};
1346         int err;
1347
1348         if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1349                 err = idtcm_output_mask_enable(channel, enable);
1350         else
1351                 err = idtcm_output_enable(channel, enable, perout->index);
1352
1353         if (err) {
1354                 dev_err(&idtcm->client->dev, "Unable to set output enable");
1355                 return err;
1356         }
1357
1358         /* Align output to internal 1 PPS */
1359         return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS);
1360 }
1361
1362 static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1363                               enum pll_mode *pll_mode)
1364 {
1365         struct idtcm *idtcm = channel->idtcm;
1366         int err;
1367         u8 dpll_mode;
1368
1369         err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1370                          &dpll_mode, sizeof(dpll_mode));
1371         if (err)
1372                 return err;
1373
1374         *pll_mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1375
1376         return 0;
1377 }
1378
1379 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1380                               enum pll_mode pll_mode)
1381 {
1382         struct idtcm *idtcm = channel->idtcm;
1383         int err;
1384         u8 dpll_mode;
1385
1386         err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1387                          &dpll_mode, sizeof(dpll_mode));
1388         if (err)
1389                 return err;
1390
1391         dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1392
1393         dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1394
1395         channel->pll_mode = pll_mode;
1396
1397         err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1398                           &dpll_mode, sizeof(dpll_mode));
1399         if (err)
1400                 return err;
1401
1402         return 0;
1403 }
1404
1405 /* PTP Hardware Clock interface */
1406
1407 /*
1408  * Maximum absolute value for write phase offset in picoseconds
1409  *
1410  * Destination signed register is 32-bit register in resolution of 50ps
1411  *
1412  * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
1413  */
1414 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1415 {
1416         struct idtcm *idtcm = channel->idtcm;
1417         int err;
1418         u8 i;
1419         u8 buf[4] = {0};
1420         s32 phase_50ps;
1421         s64 offset_ps;
1422
1423         if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1424                 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1425                 if (err)
1426                         return err;
1427         }
1428
1429         offset_ps = (s64)delta_ns * 1000;
1430
1431         /*
1432          * Check for 32-bit signed max * 50:
1433          *
1434          * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
1435          */
1436         if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1437                 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1438         else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1439                 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1440
1441         phase_50ps = div_s64(offset_ps, 50);
1442
1443         for (i = 0; i < 4; i++) {
1444                 buf[i] = phase_50ps & 0xff;
1445                 phase_50ps >>= 8;
1446         }
1447
1448         err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1449                           buf, sizeof(buf));
1450
1451         return err;
1452 }
1453
1454 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1455 {
1456         struct idtcm *idtcm = channel->idtcm;
1457         u8 i;
1458         int err;
1459         u8 buf[6] = {0};
1460         s64 fcw;
1461
1462         if (channel->pll_mode  != PLL_MODE_WRITE_FREQUENCY) {
1463                 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1464                 if (err)
1465                         return err;
1466         }
1467
1468         /*
1469          * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1470          *
1471          * adjfreq:
1472          *       ppb * 10^9
1473          * FCW = ----------
1474          *          111
1475          *
1476          * adjfine:
1477          *       ppm_16 * 5^12
1478          * FCW = -------------
1479          *         111 * 2^4
1480          */
1481
1482         /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1483         fcw = scaled_ppm * 244140625ULL;
1484
1485         fcw = div_s64(fcw, 1776);
1486
1487         for (i = 0; i < 6; i++) {
1488                 buf[i] = fcw & 0xff;
1489                 fcw >>= 8;
1490         }
1491
1492         err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1493                           buf, sizeof(buf));
1494
1495         return err;
1496 }
1497
1498 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1499 {
1500         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1501         struct idtcm *idtcm = channel->idtcm;
1502         int err;
1503
1504         mutex_lock(&idtcm->reg_lock);
1505
1506         err = _idtcm_gettime(channel, ts);
1507         if (err)
1508                 dev_err(&idtcm->client->dev, "Failed at line %d in %s!",
1509                         __LINE__, __func__);
1510
1511         mutex_unlock(&idtcm->reg_lock);
1512
1513         return err;
1514 }
1515
1516 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1517                                     const struct timespec64 *ts)
1518 {
1519         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1520         struct idtcm *idtcm = channel->idtcm;
1521         int err;
1522
1523         mutex_lock(&idtcm->reg_lock);
1524
1525         err = _idtcm_settime_deprecated(channel, ts);
1526         if (err)
1527                 dev_err(&idtcm->client->dev,
1528                         "Failed at line %d in %s!", __LINE__, __func__);
1529
1530         mutex_unlock(&idtcm->reg_lock);
1531
1532         return err;
1533 }
1534
1535 static int idtcm_settime(struct ptp_clock_info *ptp,
1536                          const struct timespec64 *ts)
1537 {
1538         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1539         struct idtcm *idtcm = channel->idtcm;
1540         int err;
1541
1542         mutex_lock(&idtcm->reg_lock);
1543
1544         err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1545         if (err)
1546                 dev_err(&idtcm->client->dev,
1547                         "Failed at line %d in %s!", __LINE__, __func__);
1548
1549         mutex_unlock(&idtcm->reg_lock);
1550
1551         return err;
1552 }
1553
1554 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
1555 {
1556         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1557         struct idtcm *idtcm = channel->idtcm;
1558         int err;
1559
1560         mutex_lock(&idtcm->reg_lock);
1561
1562         err = _idtcm_adjtime_deprecated(channel, delta);
1563         if (err)
1564                 dev_err(&idtcm->client->dev,
1565                         "Failed at line %d in %s!", __LINE__, __func__);
1566
1567         mutex_unlock(&idtcm->reg_lock);
1568
1569         return err;
1570 }
1571
1572 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1573 {
1574         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1575         struct idtcm *idtcm = channel->idtcm;
1576         struct timespec64 ts;
1577         enum scsr_tod_write_type_sel type;
1578         int err;
1579
1580         if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
1581                 err = idtcm_do_phase_pull_in(channel, delta, 0);
1582                 if (err)
1583                         dev_err(&idtcm->client->dev,
1584                                 "Failed at line %d in %s!", __LINE__, __func__);
1585                 return err;
1586         }
1587
1588         if (delta >= 0) {
1589                 ts = ns_to_timespec64(delta);
1590                 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1591         } else {
1592                 ts = ns_to_timespec64(-delta);
1593                 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1594         }
1595
1596         mutex_lock(&idtcm->reg_lock);
1597
1598         err = _idtcm_settime(channel, &ts, type);
1599         if (err)
1600                 dev_err(&idtcm->client->dev,
1601                         "Failed at line %d in %s!", __LINE__, __func__);
1602
1603         mutex_unlock(&idtcm->reg_lock);
1604
1605         return err;
1606 }
1607
1608 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1609 {
1610         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1611         struct idtcm *idtcm = channel->idtcm;
1612         int err;
1613
1614         mutex_lock(&idtcm->reg_lock);
1615
1616         err = _idtcm_adjphase(channel, delta);
1617         if (err)
1618                 dev_err(&idtcm->client->dev,
1619                         "Failed at line %d in %s!", __LINE__, __func__);
1620
1621         mutex_unlock(&idtcm->reg_lock);
1622
1623         return err;
1624 }
1625
1626 static int idtcm_adjfine(struct ptp_clock_info *ptp,  long scaled_ppm)
1627 {
1628         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1629         struct idtcm *idtcm = channel->idtcm;
1630         int err;
1631
1632         mutex_lock(&idtcm->reg_lock);
1633
1634         err = _idtcm_adjfine(channel, scaled_ppm);
1635         if (err)
1636                 dev_err(&idtcm->client->dev,
1637                         "Failed at line %d in %s!", __LINE__, __func__);
1638
1639         mutex_unlock(&idtcm->reg_lock);
1640
1641         return err;
1642 }
1643
1644 static int idtcm_enable(struct ptp_clock_info *ptp,
1645                         struct ptp_clock_request *rq, int on)
1646 {
1647         int err;
1648         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1649
1650         switch (rq->type) {
1651         case PTP_CLK_REQ_PEROUT:
1652                 if (!on) {
1653                         err = idtcm_perout_enable(channel, false, &rq->perout);
1654                         if (err)
1655                                 dev_err(&channel->idtcm->client->dev,
1656                                         "Failed at line %d in %s!",
1657                                         __LINE__, __func__);
1658                         return err;
1659                 }
1660
1661                 /* Only accept a 1-PPS aligned to the second. */
1662                 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1663                     rq->perout.period.nsec)
1664                         return -ERANGE;
1665
1666                 err = idtcm_perout_enable(channel, true, &rq->perout);
1667                 if (err)
1668                         dev_err(&channel->idtcm->client->dev,
1669                                 "Failed at line %d in %s!", __LINE__, __func__);
1670                 return err;
1671         default:
1672                 break;
1673         }
1674
1675         return -EOPNOTSUPP;
1676 }
1677
1678 static int _enable_pll_tod_sync(struct idtcm *idtcm,
1679                                 u8 pll,
1680                                 u8 sync_src,
1681                                 u8 qn,
1682                                 u8 qn_plus_1)
1683 {
1684         int err;
1685         u8 val;
1686         u16 dpll;
1687         u16 out0 = 0, out1 = 0;
1688
1689         if (qn == 0 && qn_plus_1 == 0)
1690                 return 0;
1691
1692         switch (pll) {
1693         case 0:
1694                 dpll = DPLL_0;
1695                 if (qn)
1696                         out0 = OUTPUT_0;
1697                 if (qn_plus_1)
1698                         out1 = OUTPUT_1;
1699                 break;
1700         case 1:
1701                 dpll = DPLL_1;
1702                 if (qn)
1703                         out0 = OUTPUT_2;
1704                 if (qn_plus_1)
1705                         out1 = OUTPUT_3;
1706                 break;
1707         case 2:
1708                 dpll = DPLL_2;
1709                 if (qn)
1710                         out0 = OUTPUT_4;
1711                 if (qn_plus_1)
1712                         out1 = OUTPUT_5;
1713                 break;
1714         case 3:
1715                 dpll = DPLL_3;
1716                 if (qn)
1717                         out0 = OUTPUT_6;
1718                 if (qn_plus_1)
1719                         out1 = OUTPUT_7;
1720                 break;
1721         case 4:
1722                 dpll = DPLL_4;
1723                 if (qn)
1724                         out0 = OUTPUT_8;
1725                 break;
1726         case 5:
1727                 dpll = DPLL_5;
1728                 if (qn)
1729                         out0 = OUTPUT_9;
1730                 if (qn_plus_1)
1731                         out1 = OUTPUT_8;
1732                 break;
1733         case 6:
1734                 dpll = DPLL_6;
1735                 if (qn)
1736                         out0 = OUTPUT_10;
1737                 if (qn_plus_1)
1738                         out1 = OUTPUT_11;
1739                 break;
1740         case 7:
1741                 dpll = DPLL_7;
1742                 if (qn)
1743                         out0 = OUTPUT_11;
1744                 break;
1745         default:
1746                 return -EINVAL;
1747         }
1748
1749         /*
1750          * Enable OUTPUT OUT_SYNC.
1751          */
1752         if (out0) {
1753                 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1754                 if (err)
1755                         return err;
1756
1757                 val &= ~OUT_SYNC_DISABLE;
1758
1759                 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1760                 if (err)
1761                         return err;
1762         }
1763
1764         if (out1) {
1765                 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1766                 if (err)
1767                         return err;
1768
1769                 val &= ~OUT_SYNC_DISABLE;
1770
1771                 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1772                 if (err)
1773                         return err;
1774         }
1775
1776         /* enable dpll sync tod pps, must be set before dpll_mode */
1777         err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1778         if (err)
1779                 return err;
1780
1781         val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1782         val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1783         val |= TOD_SYNC_EN;
1784
1785         return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1786 }
1787
1788 static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1789 {
1790         struct idtcm *idtcm = channel->idtcm;
1791         u8 pll;
1792         u8 sync_src;
1793         u8 qn;
1794         u8 qn_plus_1;
1795         u8 cfg;
1796         int err = 0;
1797         u16 output_mask = channel->output_mask;
1798         u8 out8_mux = 0;
1799         u8 out11_mux = 0;
1800         u8 temp;
1801
1802         /*
1803          * set tod_out_sync_enable to 0.
1804          */
1805         err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1806         if (err)
1807                 return err;
1808
1809         cfg &= ~TOD_OUT_SYNC_ENABLE;
1810
1811         err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1812         if (err)
1813                 return err;
1814
1815         switch (channel->tod_n) {
1816         case TOD_0:
1817                 sync_src = 0;
1818                 break;
1819         case TOD_1:
1820                 sync_src = 1;
1821                 break;
1822         case TOD_2:
1823                 sync_src = 2;
1824                 break;
1825         case TOD_3:
1826                 sync_src = 3;
1827                 break;
1828         default:
1829                 return -EINVAL;
1830         }
1831
1832         err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE, &temp, sizeof(temp));
1833         if (err)
1834                 return err;
1835
1836         if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1837             Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1838                 out8_mux = 1;
1839
1840         err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE, &temp, sizeof(temp));
1841         if (err)
1842                 return err;
1843
1844         if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1845             Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1846                 out11_mux = 1;
1847
1848         for (pll = 0; pll < 8; pll++) {
1849                 qn = 0;
1850                 qn_plus_1 = 0;
1851
1852                 if (pll < 4) {
1853                         /* First 4 pll has 2 outputs */
1854                         qn = output_mask & 0x1;
1855                         output_mask = output_mask >> 1;
1856                         qn_plus_1 = output_mask & 0x1;
1857                         output_mask = output_mask >> 1;
1858                 } else if (pll == 4) {
1859                         if (out8_mux == 0) {
1860                                 qn = output_mask & 0x1;
1861                                 output_mask = output_mask >> 1;
1862                         }
1863                 } else if (pll == 5) {
1864                         if (out8_mux) {
1865                                 qn_plus_1 = output_mask & 0x1;
1866                                 output_mask = output_mask >> 1;
1867                         }
1868                         qn = output_mask & 0x1;
1869                         output_mask = output_mask >> 1;
1870                 } else if (pll == 6) {
1871                         qn = output_mask & 0x1;
1872                         output_mask = output_mask >> 1;
1873                         if (out11_mux) {
1874                                 qn_plus_1 = output_mask & 0x1;
1875                                 output_mask = output_mask >> 1;
1876                         }
1877                 } else if (pll == 7) {
1878                         if (out11_mux == 0) {
1879                                 qn = output_mask & 0x1;
1880                                 output_mask = output_mask >> 1;
1881                         }
1882                 }
1883
1884                 if (qn != 0 || qn_plus_1 != 0)
1885                         err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1886                                                qn_plus_1);
1887                 if (err)
1888                         return err;
1889         }
1890
1891         return err;
1892 }
1893
1894 static int idtcm_enable_tod(struct idtcm_channel *channel)
1895 {
1896         struct idtcm *idtcm = channel->idtcm;
1897         struct timespec64 ts = {0, 0};
1898         u8 cfg;
1899         int err;
1900
1901         /*
1902          * Start the TOD clock ticking.
1903          */
1904         err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1905         if (err)
1906                 return err;
1907
1908         cfg |= TOD_ENABLE;
1909
1910         err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1911         if (err)
1912                 return err;
1913
1914         if (idtcm->deprecated)
1915                 return _idtcm_settime_deprecated(channel, &ts);
1916         else
1917                 return _idtcm_settime(channel, &ts,
1918                                       SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1919 }
1920
1921 static void idtcm_set_version_info(struct idtcm *idtcm)
1922 {
1923         u8 major;
1924         u8 minor;
1925         u8 hotfix;
1926         u16 product_id;
1927         u8 hw_rev_id;
1928         u8 config_select;
1929
1930         idtcm_read_major_release(idtcm, &major);
1931         idtcm_read_minor_release(idtcm, &minor);
1932         idtcm_read_hotfix_release(idtcm, &hotfix);
1933
1934         idtcm_read_product_id(idtcm, &product_id);
1935         idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1936
1937         idtcm_read_otp_scsr_config_select(idtcm, &config_select);
1938
1939         snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
1940                  major, minor, hotfix);
1941
1942         if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
1943                 idtcm->deprecated = 0;
1944         else
1945                 idtcm->deprecated = 1;
1946
1947         dev_info(&idtcm->client->dev,
1948                  "%d.%d.%d, Id: 0x%04x  HW Rev: %d  OTP Config Select: %d",
1949                  major, minor, hotfix,
1950                  product_id, hw_rev_id, config_select);
1951 }
1952
1953 static const struct ptp_clock_info idtcm_caps = {
1954         .owner          = THIS_MODULE,
1955         .max_adj        = 244000,
1956         .n_per_out      = 12,
1957         .adjphase       = &idtcm_adjphase,
1958         .adjfine        = &idtcm_adjfine,
1959         .adjtime        = &idtcm_adjtime,
1960         .gettime64      = &idtcm_gettime,
1961         .settime64      = &idtcm_settime,
1962         .enable         = &idtcm_enable,
1963 };
1964
1965 static const struct ptp_clock_info idtcm_caps_deprecated = {
1966         .owner          = THIS_MODULE,
1967         .max_adj        = 244000,
1968         .n_per_out      = 12,
1969         .adjphase       = &idtcm_adjphase,
1970         .adjfine        = &idtcm_adjfine,
1971         .adjtime        = &idtcm_adjtime_deprecated,
1972         .gettime64      = &idtcm_gettime,
1973         .settime64      = &idtcm_settime_deprecated,
1974         .enable         = &idtcm_enable,
1975 };
1976
1977 static int configure_channel_pll(struct idtcm_channel *channel)
1978 {
1979         int err = 0;
1980
1981         switch (channel->pll) {
1982         case 0:
1983                 channel->dpll_freq = DPLL_FREQ_0;
1984                 channel->dpll_n = DPLL_0;
1985                 channel->hw_dpll_n = HW_DPLL_0;
1986                 channel->dpll_phase = DPLL_PHASE_0;
1987                 channel->dpll_ctrl_n = DPLL_CTRL_0;
1988                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
1989                 break;
1990         case 1:
1991                 channel->dpll_freq = DPLL_FREQ_1;
1992                 channel->dpll_n = DPLL_1;
1993                 channel->hw_dpll_n = HW_DPLL_1;
1994                 channel->dpll_phase = DPLL_PHASE_1;
1995                 channel->dpll_ctrl_n = DPLL_CTRL_1;
1996                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
1997                 break;
1998         case 2:
1999                 channel->dpll_freq = DPLL_FREQ_2;
2000                 channel->dpll_n = DPLL_2;
2001                 channel->hw_dpll_n = HW_DPLL_2;
2002                 channel->dpll_phase = DPLL_PHASE_2;
2003                 channel->dpll_ctrl_n = DPLL_CTRL_2;
2004                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2005                 break;
2006         case 3:
2007                 channel->dpll_freq = DPLL_FREQ_3;
2008                 channel->dpll_n = DPLL_3;
2009                 channel->hw_dpll_n = HW_DPLL_3;
2010                 channel->dpll_phase = DPLL_PHASE_3;
2011                 channel->dpll_ctrl_n = DPLL_CTRL_3;
2012                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2013                 break;
2014         case 4:
2015                 channel->dpll_freq = DPLL_FREQ_4;
2016                 channel->dpll_n = DPLL_4;
2017                 channel->hw_dpll_n = HW_DPLL_4;
2018                 channel->dpll_phase = DPLL_PHASE_4;
2019                 channel->dpll_ctrl_n = DPLL_CTRL_4;
2020                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2021                 break;
2022         case 5:
2023                 channel->dpll_freq = DPLL_FREQ_5;
2024                 channel->dpll_n = DPLL_5;
2025                 channel->hw_dpll_n = HW_DPLL_5;
2026                 channel->dpll_phase = DPLL_PHASE_5;
2027                 channel->dpll_ctrl_n = DPLL_CTRL_5;
2028                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2029                 break;
2030         case 6:
2031                 channel->dpll_freq = DPLL_FREQ_6;
2032                 channel->dpll_n = DPLL_6;
2033                 channel->hw_dpll_n = HW_DPLL_6;
2034                 channel->dpll_phase = DPLL_PHASE_6;
2035                 channel->dpll_ctrl_n = DPLL_CTRL_6;
2036                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2037                 break;
2038         case 7:
2039                 channel->dpll_freq = DPLL_FREQ_7;
2040                 channel->dpll_n = DPLL_7;
2041                 channel->hw_dpll_n = HW_DPLL_7;
2042                 channel->dpll_phase = DPLL_PHASE_7;
2043                 channel->dpll_ctrl_n = DPLL_CTRL_7;
2044                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2045                 break;
2046         default:
2047                 err = -EINVAL;
2048         }
2049
2050         return err;
2051 }
2052
2053 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2054 {
2055         struct idtcm_channel *channel;
2056         int err;
2057
2058         if (!(index < MAX_TOD))
2059                 return -EINVAL;
2060
2061         channel = &idtcm->channel[index];
2062
2063         /* Set pll addresses */
2064         err = configure_channel_pll(channel);
2065         if (err)
2066                 return err;
2067
2068         /* Set tod addresses */
2069         switch (index) {
2070         case 0:
2071                 channel->tod_read_primary = TOD_READ_PRIMARY_0;
2072                 channel->tod_write = TOD_WRITE_0;
2073                 channel->tod_n = TOD_0;
2074                 break;
2075         case 1:
2076                 channel->tod_read_primary = TOD_READ_PRIMARY_1;
2077                 channel->tod_write = TOD_WRITE_1;
2078                 channel->tod_n = TOD_1;
2079                 break;
2080         case 2:
2081                 channel->tod_read_primary = TOD_READ_PRIMARY_2;
2082                 channel->tod_write = TOD_WRITE_2;
2083                 channel->tod_n = TOD_2;
2084                 break;
2085         case 3:
2086                 channel->tod_read_primary = TOD_READ_PRIMARY_3;
2087                 channel->tod_write = TOD_WRITE_3;
2088                 channel->tod_n = TOD_3;
2089                 break;
2090         default:
2091                 return -EINVAL;
2092         }
2093
2094         channel->idtcm = idtcm;
2095
2096         if (idtcm->deprecated)
2097                 channel->caps = idtcm_caps_deprecated;
2098         else
2099                 channel->caps = idtcm_caps;
2100
2101         snprintf(channel->caps.name, sizeof(channel->caps.name),
2102                  "IDT CM TOD%u", index);
2103
2104         if (!idtcm->deprecated) {
2105                 err = idtcm_enable_tod_sync(channel);
2106                 if (err) {
2107                         dev_err(&idtcm->client->dev,
2108                                 "Failed at line %d in %s!", __LINE__, __func__);
2109                         return err;
2110                 }
2111         }
2112
2113         /* Sync pll mode with hardware */
2114         err = idtcm_get_pll_mode(channel, &channel->pll_mode);
2115         if (err) {
2116                 dev_err(&idtcm->client->dev,
2117                         "Error: %s - Unable to read pll mode", __func__);
2118                 return err;
2119         }
2120
2121         err = idtcm_enable_tod(channel);
2122         if (err) {
2123                 dev_err(&idtcm->client->dev,
2124                         "Failed at line %d in %s!", __LINE__, __func__);
2125                 return err;
2126         }
2127
2128         channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2129
2130         if (IS_ERR(channel->ptp_clock)) {
2131                 err = PTR_ERR(channel->ptp_clock);
2132                 channel->ptp_clock = NULL;
2133                 return err;
2134         }
2135
2136         if (!channel->ptp_clock)
2137                 return -ENOTSUPP;
2138
2139         dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d",
2140                  index, channel->ptp_clock->index);
2141
2142         return 0;
2143 }
2144
2145 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2146 {
2147         u8 i;
2148         struct idtcm_channel *channel;
2149
2150         for (i = 0; i < MAX_TOD; i++) {
2151                 channel = &idtcm->channel[i];
2152
2153                 if (channel->ptp_clock)
2154                         ptp_clock_unregister(channel->ptp_clock);
2155         }
2156 }
2157
2158 static void set_default_masks(struct idtcm *idtcm)
2159 {
2160         idtcm->tod_mask = DEFAULT_TOD_MASK;
2161
2162         idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2163         idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2164         idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2165         idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2166
2167         idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2168         idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2169         idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2170         idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2171 }
2172
2173 static int idtcm_probe(struct i2c_client *client,
2174                        const struct i2c_device_id *id)
2175 {
2176         struct idtcm *idtcm;
2177         int err;
2178         u8 i;
2179
2180         /* Unused for now */
2181         (void)id;
2182
2183         idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2184
2185         if (!idtcm)
2186                 return -ENOMEM;
2187
2188         idtcm->client = client;
2189         idtcm->page_offset = 0xff;
2190         idtcm->calculate_overhead_flag = 0;
2191
2192         set_default_masks(idtcm);
2193
2194         mutex_init(&idtcm->reg_lock);
2195         mutex_lock(&idtcm->reg_lock);
2196
2197         idtcm_set_version_info(idtcm);
2198
2199         err = idtcm_load_firmware(idtcm, &client->dev);
2200         if (err)
2201                 dev_warn(&idtcm->client->dev, "loading firmware failed with %d", err);
2202
2203         wait_for_chip_ready(idtcm);
2204
2205         if (idtcm->tod_mask) {
2206                 for (i = 0; i < MAX_TOD; i++) {
2207                         if (idtcm->tod_mask & (1 << i)) {
2208                                 err = idtcm_enable_channel(idtcm, i);
2209                                 if (err) {
2210                                         dev_err(&idtcm->client->dev,
2211                                                 "idtcm_enable_channel %d failed!", i);
2212                                         break;
2213                                 }
2214                         }
2215                 }
2216         } else {
2217                 dev_err(&idtcm->client->dev,
2218                         "no PLLs flagged as PHCs, nothing to do");
2219                 err = -ENODEV;
2220         }
2221
2222         mutex_unlock(&idtcm->reg_lock);
2223
2224         if (err) {
2225                 ptp_clock_unregister_all(idtcm);
2226                 return err;
2227         }
2228
2229         i2c_set_clientdata(client, idtcm);
2230
2231         return 0;
2232 }
2233
2234 static int idtcm_remove(struct i2c_client *client)
2235 {
2236         struct idtcm *idtcm = i2c_get_clientdata(client);
2237
2238         ptp_clock_unregister_all(idtcm);
2239
2240         mutex_destroy(&idtcm->reg_lock);
2241
2242         return 0;
2243 }
2244
2245 #ifdef CONFIG_OF
2246 static const struct of_device_id idtcm_dt_id[] = {
2247         { .compatible = "idt,8a34000" },
2248         { .compatible = "idt,8a34001" },
2249         { .compatible = "idt,8a34002" },
2250         { .compatible = "idt,8a34003" },
2251         { .compatible = "idt,8a34004" },
2252         { .compatible = "idt,8a34005" },
2253         { .compatible = "idt,8a34006" },
2254         { .compatible = "idt,8a34007" },
2255         { .compatible = "idt,8a34008" },
2256         { .compatible = "idt,8a34009" },
2257         { .compatible = "idt,8a34010" },
2258         { .compatible = "idt,8a34011" },
2259         { .compatible = "idt,8a34012" },
2260         { .compatible = "idt,8a34013" },
2261         { .compatible = "idt,8a34014" },
2262         { .compatible = "idt,8a34015" },
2263         { .compatible = "idt,8a34016" },
2264         { .compatible = "idt,8a34017" },
2265         { .compatible = "idt,8a34018" },
2266         { .compatible = "idt,8a34019" },
2267         { .compatible = "idt,8a34040" },
2268         { .compatible = "idt,8a34041" },
2269         { .compatible = "idt,8a34042" },
2270         { .compatible = "idt,8a34043" },
2271         { .compatible = "idt,8a34044" },
2272         { .compatible = "idt,8a34045" },
2273         { .compatible = "idt,8a34046" },
2274         { .compatible = "idt,8a34047" },
2275         { .compatible = "idt,8a34048" },
2276         { .compatible = "idt,8a34049" },
2277         {},
2278 };
2279 MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2280 #endif
2281
2282 static const struct i2c_device_id idtcm_i2c_id[] = {
2283         { "8a34000" },
2284         { "8a34001" },
2285         { "8a34002" },
2286         { "8a34003" },
2287         { "8a34004" },
2288         { "8a34005" },
2289         { "8a34006" },
2290         { "8a34007" },
2291         { "8a34008" },
2292         { "8a34009" },
2293         { "8a34010" },
2294         { "8a34011" },
2295         { "8a34012" },
2296         { "8a34013" },
2297         { "8a34014" },
2298         { "8a34015" },
2299         { "8a34016" },
2300         { "8a34017" },
2301         { "8a34018" },
2302         { "8a34019" },
2303         { "8a34040" },
2304         { "8a34041" },
2305         { "8a34042" },
2306         { "8a34043" },
2307         { "8a34044" },
2308         { "8a34045" },
2309         { "8a34046" },
2310         { "8a34047" },
2311         { "8a34048" },
2312         { "8a34049" },
2313         {},
2314 };
2315 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2316
2317 static struct i2c_driver idtcm_driver = {
2318         .driver = {
2319                 .of_match_table = of_match_ptr(idtcm_dt_id),
2320                 .name           = "idtcm",
2321         },
2322         .probe          = idtcm_probe,
2323         .remove         = idtcm_remove,
2324         .id_table       = idtcm_i2c_id,
2325 };
2326
2327 module_i2c_driver(idtcm_driver);