1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Running Average Power Limit (RAPL) Driver
4 * Copyright (c) 2013, Intel Corporation.
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/list.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
13 #include <linux/slab.h>
14 #include <linux/log2.h>
15 #include <linux/bitmap.h>
16 #include <linux/delay.h>
17 #include <linux/sysfs.h>
18 #include <linux/cpu.h>
19 #include <linux/powercap.h>
20 #include <linux/suspend.h>
21 #include <linux/intel_rapl.h>
23 #include <asm/iosf_mbi.h>
24 #include <asm/processor.h>
25 #include <asm/cpu_device_id.h>
26 #include <asm/intel-family.h>
29 #define MSR_PLATFORM_POWER_LIMIT 0x0000065C
31 /* bitmasks for RAPL MSRs, used by primitive access functions */
32 #define ENERGY_STATUS_MASK 0xffffffff
34 #define POWER_LIMIT1_MASK 0x7FFF
35 #define POWER_LIMIT1_ENABLE BIT(15)
36 #define POWER_LIMIT1_CLAMP BIT(16)
38 #define POWER_LIMIT2_MASK (0x7FFFULL<<32)
39 #define POWER_LIMIT2_ENABLE BIT_ULL(47)
40 #define POWER_LIMIT2_CLAMP BIT_ULL(48)
41 #define POWER_PACKAGE_LOCK BIT_ULL(63)
42 #define POWER_PP_LOCK BIT(31)
44 #define TIME_WINDOW1_MASK (0x7FULL<<17)
45 #define TIME_WINDOW2_MASK (0x7FULL<<49)
47 #define POWER_UNIT_OFFSET 0
48 #define POWER_UNIT_MASK 0x0F
50 #define ENERGY_UNIT_OFFSET 0x08
51 #define ENERGY_UNIT_MASK 0x1F00
53 #define TIME_UNIT_OFFSET 0x10
54 #define TIME_UNIT_MASK 0xF0000
56 #define POWER_INFO_MAX_MASK (0x7fffULL<<32)
57 #define POWER_INFO_MIN_MASK (0x7fffULL<<16)
58 #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
59 #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
61 #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
62 #define PP_POLICY_MASK 0x1F
64 /* Non HW constants */
65 #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
66 #define RAPL_PRIMITIVE_DUMMY BIT(2)
68 #define TIME_WINDOW_MAX_MSEC 40000
69 #define TIME_WINDOW_MIN_MSEC 250
70 #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
72 ARBITRARY_UNIT, /* no translation */
78 /* private data for RAPL MSR Interface */
79 static struct rapl_if_priv rapl_msr_priv = {
80 .reg_unit = MSR_RAPL_POWER_UNIT,
81 .regs[RAPL_DOMAIN_PACKAGE] = {
82 MSR_PKG_POWER_LIMIT, MSR_PKG_ENERGY_STATUS, MSR_PKG_PERF_STATUS, 0, MSR_PKG_POWER_INFO },
83 .regs[RAPL_DOMAIN_PP0] = {
84 MSR_PP0_POWER_LIMIT, MSR_PP0_ENERGY_STATUS, 0, MSR_PP0_POLICY, 0 },
85 .regs[RAPL_DOMAIN_PP1] = {
86 MSR_PP1_POWER_LIMIT, MSR_PP1_ENERGY_STATUS, 0, MSR_PP1_POLICY, 0 },
87 .regs[RAPL_DOMAIN_DRAM] = {
88 MSR_DRAM_POWER_LIMIT, MSR_DRAM_ENERGY_STATUS, MSR_DRAM_PERF_STATUS, 0, MSR_DRAM_POWER_INFO },
89 .regs[RAPL_DOMAIN_PLATFORM] = {
90 MSR_PLATFORM_POWER_LIMIT, MSR_PLATFORM_ENERGY_STATUS, 0, 0, 0},
93 /* per domain data, some are optional */
94 #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
103 #define DOMAIN_STATE_INACTIVE BIT(0)
104 #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
105 #define DOMAIN_STATE_BIOS_LOCKED BIT(2)
107 static const char pl1_name[] = "long_term";
108 static const char pl2_name[] = "short_term";
110 #define power_zone_to_rapl_domain(_zone) \
111 container_of(_zone, struct rapl_domain, power_zone)
113 struct rapl_defaults {
114 u8 floor_freq_reg_addr;
115 int (*check_unit)(struct rapl_package *rp, int cpu);
116 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
117 u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
119 unsigned int dram_domain_energy_unit;
121 static struct rapl_defaults *rapl_defaults;
123 /* Sideband MBI registers */
124 #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
125 #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
127 #define PACKAGE_PLN_INT_SAVED BIT(0)
128 #define MAX_PRIM_NAME (32)
130 /* per domain data. used to describe individual knobs such that access function
131 * can be consolidated into one instead of many inline functions.
133 struct rapl_primitive_info {
137 enum rapl_domain_reg_id id;
142 #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
151 static void rapl_init_domains(struct rapl_package *rp);
152 static int rapl_read_data_raw(struct rapl_domain *rd,
153 enum rapl_primitives prim,
154 bool xlate, u64 *data);
155 static int rapl_write_data_raw(struct rapl_domain *rd,
156 enum rapl_primitives prim,
157 unsigned long long value);
158 static u64 rapl_unit_xlate(struct rapl_domain *rd,
159 enum unit_type type, u64 value,
161 static void package_power_limit_irq_save(struct rapl_package *rp);
163 static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
165 static const char * const rapl_domain_names[] = {
173 /* caller to ensure CPU hotplug lock is held */
174 static struct rapl_package *rapl_find_package_domain(int cpu, struct rapl_if_priv *priv)
176 int id = topology_logical_die_id(cpu);
177 struct rapl_package *rp;
179 list_for_each_entry(rp, &rapl_packages, plist) {
180 if (rp->id == id && rp->priv->control_type == priv->control_type)
187 static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
189 struct rapl_domain *rd;
192 /* prevent CPU hotplug, make sure the RAPL domain does not go
193 * away while reading the counter.
196 rd = power_zone_to_rapl_domain(power_zone);
198 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
199 *energy_raw = energy_now;
209 static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
211 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
213 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
217 static int release_zone(struct powercap_zone *power_zone)
219 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
220 struct rapl_package *rp = rd->rp;
222 /* package zone is the last zone of a package, we can free
223 * memory here since all children has been unregistered.
225 if (rd->id == RAPL_DOMAIN_PACKAGE) {
234 static int find_nr_power_limit(struct rapl_domain *rd)
238 for (i = 0; i < NR_POWER_LIMITS; i++) {
246 static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
248 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
250 if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
254 rapl_write_data_raw(rd, PL1_ENABLE, mode);
255 if (rapl_defaults->set_floor_freq)
256 rapl_defaults->set_floor_freq(rd, mode);
262 static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
264 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
267 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
272 if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
282 /* per RAPL domain ops, in the order of rapl_domain_type */
283 static const struct powercap_zone_ops zone_ops[] = {
284 /* RAPL_DOMAIN_PACKAGE */
286 .get_energy_uj = get_energy_counter,
287 .get_max_energy_range_uj = get_max_energy_counter,
288 .release = release_zone,
289 .set_enable = set_domain_enable,
290 .get_enable = get_domain_enable,
292 /* RAPL_DOMAIN_PP0 */
294 .get_energy_uj = get_energy_counter,
295 .get_max_energy_range_uj = get_max_energy_counter,
296 .release = release_zone,
297 .set_enable = set_domain_enable,
298 .get_enable = get_domain_enable,
300 /* RAPL_DOMAIN_PP1 */
302 .get_energy_uj = get_energy_counter,
303 .get_max_energy_range_uj = get_max_energy_counter,
304 .release = release_zone,
305 .set_enable = set_domain_enable,
306 .get_enable = get_domain_enable,
308 /* RAPL_DOMAIN_DRAM */
310 .get_energy_uj = get_energy_counter,
311 .get_max_energy_range_uj = get_max_energy_counter,
312 .release = release_zone,
313 .set_enable = set_domain_enable,
314 .get_enable = get_domain_enable,
316 /* RAPL_DOMAIN_PLATFORM */
318 .get_energy_uj = get_energy_counter,
319 .get_max_energy_range_uj = get_max_energy_counter,
320 .release = release_zone,
321 .set_enable = set_domain_enable,
322 .get_enable = get_domain_enable,
328 * Constraint index used by powercap can be different than power limit (PL)
329 * index in that some PLs maybe missing due to non-existant MSRs. So we
330 * need to convert here by finding the valid PLs only (name populated).
332 static int contraint_to_pl(struct rapl_domain *rd, int cid)
336 for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) {
337 if ((rd->rpl[i].name) && j++ == cid) {
338 pr_debug("%s: index %d\n", __func__, i);
342 pr_err("Cannot find matching power limit for constraint %d\n", cid);
347 static int set_power_limit(struct powercap_zone *power_zone, int cid,
350 struct rapl_domain *rd;
351 struct rapl_package *rp;
356 rd = power_zone_to_rapl_domain(power_zone);
357 id = contraint_to_pl(rd, cid);
365 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
366 dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
372 switch (rd->rpl[id].prim_id) {
374 rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
377 rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
383 package_power_limit_irq_save(rp);
389 static int get_current_power_limit(struct powercap_zone *power_zone, int cid,
392 struct rapl_domain *rd;
399 rd = power_zone_to_rapl_domain(power_zone);
400 id = contraint_to_pl(rd, cid);
406 switch (rd->rpl[id].prim_id) {
417 if (rapl_read_data_raw(rd, prim, true, &val))
428 static int set_time_window(struct powercap_zone *power_zone, int cid,
431 struct rapl_domain *rd;
436 rd = power_zone_to_rapl_domain(power_zone);
437 id = contraint_to_pl(rd, cid);
443 switch (rd->rpl[id].prim_id) {
445 rapl_write_data_raw(rd, TIME_WINDOW1, window);
448 rapl_write_data_raw(rd, TIME_WINDOW2, window);
459 static int get_time_window(struct powercap_zone *power_zone, int cid, u64 *data)
461 struct rapl_domain *rd;
467 rd = power_zone_to_rapl_domain(power_zone);
468 id = contraint_to_pl(rd, cid);
474 switch (rd->rpl[id].prim_id) {
476 ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
479 ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
494 static const char *get_constraint_name(struct powercap_zone *power_zone, int cid)
496 struct rapl_domain *rd;
499 rd = power_zone_to_rapl_domain(power_zone);
500 id = contraint_to_pl(rd, cid);
502 return rd->rpl[id].name;
508 static int get_max_power(struct powercap_zone *power_zone, int id,
511 struct rapl_domain *rd;
517 rd = power_zone_to_rapl_domain(power_zone);
518 switch (rd->rpl[id].prim_id) {
520 prim = THERMAL_SPEC_POWER;
529 if (rapl_read_data_raw(rd, prim, true, &val))
539 static const struct powercap_zone_constraint_ops constraint_ops = {
540 .set_power_limit_uw = set_power_limit,
541 .get_power_limit_uw = get_current_power_limit,
542 .set_time_window_us = set_time_window,
543 .get_time_window_us = get_time_window,
544 .get_max_power_uw = get_max_power,
545 .get_name = get_constraint_name,
548 /* called after domain detection and package level data are set */
549 static void rapl_init_domains(struct rapl_package *rp)
552 struct rapl_domain *rd = rp->domains;
554 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
555 unsigned int mask = rp->domain_map & (1 << i);
557 rd->regs[RAPL_DOMAIN_REG_LIMIT] = rp->priv->regs[i][RAPL_DOMAIN_REG_LIMIT];
558 rd->regs[RAPL_DOMAIN_REG_STATUS] = rp->priv->regs[i][RAPL_DOMAIN_REG_STATUS];
559 rd->regs[RAPL_DOMAIN_REG_PERF] = rp->priv->regs[i][RAPL_DOMAIN_REG_PERF];
560 rd->regs[RAPL_DOMAIN_REG_POLICY] = rp->priv->regs[i][RAPL_DOMAIN_REG_POLICY];
561 rd->regs[RAPL_DOMAIN_REG_INFO] = rp->priv->regs[i][RAPL_DOMAIN_REG_INFO];
564 case BIT(RAPL_DOMAIN_PACKAGE):
565 rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
566 rd->id = RAPL_DOMAIN_PACKAGE;
567 rd->rpl[0].prim_id = PL1_ENABLE;
568 rd->rpl[0].name = pl1_name;
569 rd->rpl[1].prim_id = PL2_ENABLE;
570 rd->rpl[1].name = pl2_name;
572 case BIT(RAPL_DOMAIN_PP0):
573 rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
574 rd->id = RAPL_DOMAIN_PP0;
575 rd->rpl[0].prim_id = PL1_ENABLE;
576 rd->rpl[0].name = pl1_name;
578 case BIT(RAPL_DOMAIN_PP1):
579 rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
580 rd->id = RAPL_DOMAIN_PP1;
581 rd->rpl[0].prim_id = PL1_ENABLE;
582 rd->rpl[0].name = pl1_name;
584 case BIT(RAPL_DOMAIN_DRAM):
585 rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
586 rd->id = RAPL_DOMAIN_DRAM;
587 rd->rpl[0].prim_id = PL1_ENABLE;
588 rd->rpl[0].name = pl1_name;
589 rd->domain_energy_unit =
590 rapl_defaults->dram_domain_energy_unit;
591 if (rd->domain_energy_unit)
592 pr_info("DRAM domain energy unit %dpj\n",
593 rd->domain_energy_unit);
603 static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
604 u64 value, int to_raw)
607 struct rapl_package *rp = rd->rp;
612 units = rp->power_unit;
615 scale = ENERGY_UNIT_SCALE;
616 /* per domain unit takes precedence */
617 if (rd->domain_energy_unit)
618 units = rd->domain_energy_unit;
620 units = rp->energy_unit;
623 return rapl_defaults->compute_time_window(rp, value, to_raw);
630 return div64_u64(value, units) * scale;
634 return div64_u64(value, scale);
637 /* in the order of enum rapl_primitives */
638 static struct rapl_primitive_info rpi[] = {
639 /* name, mask, shift, msr index, unit divisor */
640 PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
641 RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
642 PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
643 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
644 PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
645 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
646 PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
647 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
648 PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
649 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
650 PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
651 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
652 PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
653 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
654 PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
655 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
656 PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
657 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
658 PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
659 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
660 PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
661 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
662 PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
663 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
664 PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
665 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
666 PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
667 RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
668 PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
669 RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
670 PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
671 RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
673 PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
674 RAPL_PRIMITIVE_DERIVED),
678 /* Read primitive data based on its related struct rapl_primitive_info.
679 * if xlate flag is set, return translated data based on data units, i.e.
680 * time, energy, and power.
681 * RAPL MSRs are non-architectual and are laid out not consistently across
682 * domains. Here we use primitive info to allow writing consolidated access
684 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
685 * is pre-assigned based on RAPL unit MSRs read at init time.
686 * 63-------------------------- 31--------------------------- 0
688 * | |<- shift ----------------|
689 * 63-------------------------- 31--------------------------- 0
691 static int rapl_read_data_raw(struct rapl_domain *rd,
692 enum rapl_primitives prim,
693 bool xlate, u64 *data)
697 struct rapl_primitive_info *rp = &rpi[prim];
700 if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
703 msr = rd->regs[rp->id];
707 cpu = rd->rp->lead_cpu;
709 /* special-case package domain, which uses a different bit*/
710 if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
711 rp->mask = POWER_PACKAGE_LOCK;
714 /* non-hardware data are collected by the polling thread */
715 if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
716 *data = rd->rdd.primitives[prim];
720 if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
721 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
725 final = value & rp->mask;
726 final = final >> rp->shift;
728 *data = rapl_unit_xlate(rd, rp->unit, final, 0);
736 static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask)
741 err = rdmsrl_safe(msr_no, &val);
748 err = wrmsrl_safe(msr_no, val);
754 static void msrl_update_func(void *info)
756 struct msrl_action *ma = info;
758 ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask);
761 /* Similar use of primitive info in the read counterpart */
762 static int rapl_write_data_raw(struct rapl_domain *rd,
763 enum rapl_primitives prim,
764 unsigned long long value)
766 struct rapl_primitive_info *rp = &rpi[prim];
769 struct msrl_action ma;
772 cpu = rd->rp->lead_cpu;
773 bits = rapl_unit_xlate(rd, rp->unit, value, 1);
777 memset(&ma, 0, sizeof(ma));
779 ma.msr_no = rd->regs[rp->id];
780 ma.clear_mask = rp->mask;
783 ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1);
793 * Raw RAPL data stored in MSRs are in certain scales. We need to
794 * convert them into standard units based on the units reported in
795 * the RAPL unit MSRs. This is specific to CPUs as the method to
796 * calculate units differ on different CPUs.
797 * We convert the units to below format based on CPUs.
799 * energy unit: picoJoules : Represented in picoJoules by default
800 * power unit : microWatts : Represented in milliWatts by default
801 * time unit : microseconds: Represented in seconds by default
803 static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
808 if (rdmsrl_safe_on_cpu(cpu, rp->priv->reg_unit, &msr_val)) {
809 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
810 rp->priv->reg_unit, cpu);
814 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
815 rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
817 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
818 rp->power_unit = 1000000 / (1 << value);
820 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
821 rp->time_unit = 1000000 / (1 << value);
823 pr_debug("Core CPU %s energy=%dpJ, time=%dus, power=%duW\n",
824 rp->name, rp->energy_unit, rp->time_unit, rp->power_unit);
829 static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
834 if (rdmsrl_safe_on_cpu(cpu, rp->priv->reg_unit, &msr_val)) {
835 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
836 rp->priv->reg_unit, cpu);
839 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
840 rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
842 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
843 rp->power_unit = (1 << value) * 1000;
845 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
846 rp->time_unit = 1000000 / (1 << value);
848 pr_debug("Atom %s energy=%dpJ, time=%dus, power=%duW\n",
849 rp->name, rp->energy_unit, rp->time_unit, rp->power_unit);
854 static void power_limit_irq_save_cpu(void *info)
857 struct rapl_package *rp = (struct rapl_package *)info;
859 /* save the state of PLN irq mask bit before disabling it */
860 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
861 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
862 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
863 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
865 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
866 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
871 * When package power limit is set artificially low by RAPL, LVT
872 * thermal interrupt for package power limit should be ignored
873 * since we are not really exceeding the real limit. The intention
874 * is to avoid excessive interrupts while we are trying to save power.
875 * A useful feature might be routing the package_power_limit interrupt
876 * to userspace via eventfd. once we have a usecase, this is simple
877 * to do by adding an atomic notifier.
880 static void package_power_limit_irq_save(struct rapl_package *rp)
882 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
885 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1);
889 * Restore per package power limit interrupt enable state. Called from cpu
890 * hotplug code on package removal.
892 static void package_power_limit_irq_restore(struct rapl_package *rp)
896 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
899 /* irq enable state not saved, nothing to restore */
900 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
903 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
905 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
906 l |= PACKAGE_THERM_INT_PLN_ENABLE;
908 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
910 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
913 static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
915 int nr_powerlimit = find_nr_power_limit(rd);
917 /* always enable clamp such that p-state can go below OS requested
918 * range. power capping priority over guranteed frequency.
920 rapl_write_data_raw(rd, PL1_CLAMP, mode);
922 /* some domains have pl2 */
923 if (nr_powerlimit > 1) {
924 rapl_write_data_raw(rd, PL2_ENABLE, mode);
925 rapl_write_data_raw(rd, PL2_CLAMP, mode);
929 static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
931 static u32 power_ctrl_orig_val;
934 if (!rapl_defaults->floor_freq_reg_addr) {
935 pr_err("Invalid floor frequency config register\n");
939 if (!power_ctrl_orig_val)
940 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
941 rapl_defaults->floor_freq_reg_addr,
942 &power_ctrl_orig_val);
943 mdata = power_ctrl_orig_val;
945 mdata &= ~(0x7f << 8);
948 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
949 rapl_defaults->floor_freq_reg_addr, mdata);
952 static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
955 u64 f, y; /* fraction and exp. used for time unit */
958 * Special processing based on 2^Y*(1+F/4), refer
959 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
962 f = (value & 0x60) >> 5;
964 value = (1 << y) * (4 + f) * rp->time_unit / 4;
966 do_div(value, rp->time_unit);
968 f = div64_u64(4 * (value - (1 << y)), 1 << y);
969 value = (y & 0x1f) | ((f & 0x3) << 5);
974 static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
978 * Atom time unit encoding is straight forward val * time_unit,
979 * where time_unit is default to 1 sec. Never 0.
982 return (value) ? value *= rp->time_unit : rp->time_unit;
984 value = div64_u64(value, rp->time_unit);
989 static const struct rapl_defaults rapl_defaults_core = {
990 .floor_freq_reg_addr = 0,
991 .check_unit = rapl_check_unit_core,
992 .set_floor_freq = set_floor_freq_default,
993 .compute_time_window = rapl_compute_time_window_core,
996 static const struct rapl_defaults rapl_defaults_hsw_server = {
997 .check_unit = rapl_check_unit_core,
998 .set_floor_freq = set_floor_freq_default,
999 .compute_time_window = rapl_compute_time_window_core,
1000 .dram_domain_energy_unit = 15300,
1003 static const struct rapl_defaults rapl_defaults_byt = {
1004 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
1005 .check_unit = rapl_check_unit_atom,
1006 .set_floor_freq = set_floor_freq_atom,
1007 .compute_time_window = rapl_compute_time_window_atom,
1010 static const struct rapl_defaults rapl_defaults_tng = {
1011 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
1012 .check_unit = rapl_check_unit_atom,
1013 .set_floor_freq = set_floor_freq_atom,
1014 .compute_time_window = rapl_compute_time_window_atom,
1017 static const struct rapl_defaults rapl_defaults_ann = {
1018 .floor_freq_reg_addr = 0,
1019 .check_unit = rapl_check_unit_atom,
1020 .set_floor_freq = NULL,
1021 .compute_time_window = rapl_compute_time_window_atom,
1024 static const struct rapl_defaults rapl_defaults_cht = {
1025 .floor_freq_reg_addr = 0,
1026 .check_unit = rapl_check_unit_atom,
1027 .set_floor_freq = NULL,
1028 .compute_time_window = rapl_compute_time_window_atom,
1031 static const struct x86_cpu_id rapl_ids[] __initconst = {
1032 INTEL_CPU_FAM6(SANDYBRIDGE, rapl_defaults_core),
1033 INTEL_CPU_FAM6(SANDYBRIDGE_X, rapl_defaults_core),
1035 INTEL_CPU_FAM6(IVYBRIDGE, rapl_defaults_core),
1036 INTEL_CPU_FAM6(IVYBRIDGE_X, rapl_defaults_core),
1038 INTEL_CPU_FAM6(HASWELL_CORE, rapl_defaults_core),
1039 INTEL_CPU_FAM6(HASWELL_ULT, rapl_defaults_core),
1040 INTEL_CPU_FAM6(HASWELL_GT3E, rapl_defaults_core),
1041 INTEL_CPU_FAM6(HASWELL_X, rapl_defaults_hsw_server),
1043 INTEL_CPU_FAM6(BROADWELL_CORE, rapl_defaults_core),
1044 INTEL_CPU_FAM6(BROADWELL_GT3E, rapl_defaults_core),
1045 INTEL_CPU_FAM6(BROADWELL_XEON_D, rapl_defaults_core),
1046 INTEL_CPU_FAM6(BROADWELL_X, rapl_defaults_hsw_server),
1048 INTEL_CPU_FAM6(SKYLAKE_DESKTOP, rapl_defaults_core),
1049 INTEL_CPU_FAM6(SKYLAKE_MOBILE, rapl_defaults_core),
1050 INTEL_CPU_FAM6(SKYLAKE_X, rapl_defaults_hsw_server),
1051 INTEL_CPU_FAM6(KABYLAKE_MOBILE, rapl_defaults_core),
1052 INTEL_CPU_FAM6(KABYLAKE_DESKTOP, rapl_defaults_core),
1053 INTEL_CPU_FAM6(CANNONLAKE_MOBILE, rapl_defaults_core),
1054 INTEL_CPU_FAM6(ICELAKE_MOBILE, rapl_defaults_core),
1056 INTEL_CPU_FAM6(ATOM_SILVERMONT, rapl_defaults_byt),
1057 INTEL_CPU_FAM6(ATOM_AIRMONT, rapl_defaults_cht),
1058 INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, rapl_defaults_tng),
1059 INTEL_CPU_FAM6(ATOM_AIRMONT_MID, rapl_defaults_ann),
1060 INTEL_CPU_FAM6(ATOM_GOLDMONT, rapl_defaults_core),
1061 INTEL_CPU_FAM6(ATOM_GOLDMONT_PLUS, rapl_defaults_core),
1062 INTEL_CPU_FAM6(ATOM_GOLDMONT_X, rapl_defaults_core),
1063 INTEL_CPU_FAM6(ATOM_TREMONT_X, rapl_defaults_core),
1065 INTEL_CPU_FAM6(XEON_PHI_KNL, rapl_defaults_hsw_server),
1066 INTEL_CPU_FAM6(XEON_PHI_KNM, rapl_defaults_hsw_server),
1069 MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1071 /* Read once for all raw primitive data for domains */
1072 static void rapl_update_domain_data(struct rapl_package *rp)
1077 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
1078 pr_debug("update %s domain %s data\n", rp->name,
1079 rp->domains[dmn].name);
1080 /* exclude non-raw primitives */
1081 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) {
1082 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1083 rpi[prim].unit, &val))
1084 rp->domains[dmn].rdd.primitives[prim] = val;
1090 static void rapl_unregister_powercap(void)
1092 if (&rapl_msr_priv.platform_rapl_domain) {
1093 powercap_unregister_zone(rapl_msr_priv.control_type,
1094 &rapl_msr_priv.platform_rapl_domain->power_zone);
1095 kfree(rapl_msr_priv.platform_rapl_domain);
1097 powercap_unregister_control_type(rapl_msr_priv.control_type);
1100 static int rapl_package_register_powercap(struct rapl_package *rp)
1102 struct rapl_domain *rd;
1103 struct powercap_zone *power_zone = NULL;
1106 /* Update the domain data of the new package */
1107 rapl_update_domain_data(rp);
1109 /* first we register package domain as the parent zone*/
1110 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1111 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1112 nr_pl = find_nr_power_limit(rd);
1113 pr_debug("register package domain %s\n", rp->name);
1114 power_zone = powercap_register_zone(&rd->power_zone,
1115 rp->priv->control_type,
1120 if (IS_ERR(power_zone)) {
1121 pr_debug("failed to register power zone %s\n",
1123 return PTR_ERR(power_zone);
1125 /* track parent zone in per package/socket data */
1126 rp->power_zone = power_zone;
1127 /* done, only one package domain per socket */
1132 pr_err("no package domain found, unknown topology!\n");
1135 /* now register domains as children of the socket/package*/
1136 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1137 if (rd->id == RAPL_DOMAIN_PACKAGE)
1139 /* number of power limits per domain varies */
1140 nr_pl = find_nr_power_limit(rd);
1141 power_zone = powercap_register_zone(&rd->power_zone,
1142 rp->priv->control_type, rd->name,
1144 &zone_ops[rd->id], nr_pl,
1147 if (IS_ERR(power_zone)) {
1148 pr_debug("failed to register power_zone, %s:%s\n",
1149 rp->name, rd->name);
1150 ret = PTR_ERR(power_zone);
1158 * Clean up previously initialized domains within the package if we
1159 * failed after the first domain setup.
1161 while (--rd >= rp->domains) {
1162 pr_debug("unregister %s domain %s\n", rp->name, rd->name);
1163 powercap_unregister_zone(rp->priv->control_type, &rd->power_zone);
1169 static int __init rapl_register_psys(void)
1171 struct rapl_domain *rd;
1172 struct powercap_zone *power_zone;
1175 if (rdmsrl_safe_on_cpu(0, rapl_msr_priv.regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_STATUS], &val) || !val)
1178 if (rdmsrl_safe_on_cpu(0, rapl_msr_priv.regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_LIMIT], &val) || !val)
1181 rd = kzalloc(sizeof(*rd), GFP_KERNEL);
1185 rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
1186 rd->id = RAPL_DOMAIN_PLATFORM;
1187 rd->regs[RAPL_DOMAIN_REG_LIMIT] = rapl_msr_priv.regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_LIMIT];
1188 rd->regs[RAPL_DOMAIN_REG_STATUS] = rapl_msr_priv.regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_STATUS];
1189 rd->rpl[0].prim_id = PL1_ENABLE;
1190 rd->rpl[0].name = pl1_name;
1191 rd->rpl[1].prim_id = PL2_ENABLE;
1192 rd->rpl[1].name = pl2_name;
1193 rd->rp = rapl_find_package_domain(0, &rapl_msr_priv);
1195 power_zone = powercap_register_zone(&rd->power_zone, rapl_msr_priv.control_type,
1197 &zone_ops[RAPL_DOMAIN_PLATFORM],
1198 2, &constraint_ops);
1200 if (IS_ERR(power_zone)) {
1202 return PTR_ERR(power_zone);
1205 rapl_msr_priv.platform_rapl_domain = rd;
1210 static int __init rapl_register_powercap(void)
1212 rapl_msr_priv.control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
1213 if (IS_ERR(rapl_msr_priv.control_type)) {
1214 pr_debug("failed to register powercap control_type.\n");
1215 return PTR_ERR(rapl_msr_priv.control_type);
1220 static int rapl_check_domain(int cpu, int domain, struct rapl_package *rp)
1226 case RAPL_DOMAIN_PACKAGE:
1227 case RAPL_DOMAIN_PP0:
1228 case RAPL_DOMAIN_PP1:
1229 case RAPL_DOMAIN_DRAM:
1230 reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS];
1232 case RAPL_DOMAIN_PLATFORM:
1233 /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
1236 pr_err("invalid domain id %d\n", domain);
1239 /* make sure domain counters are available and contains non-zero
1240 * values, otherwise skip it.
1242 if (rdmsrl_safe_on_cpu(cpu, reg, &val) || !val)
1250 * Check if power limits are available. Two cases when they are not available:
1251 * 1. Locked by BIOS, in this case we still provide read-only access so that
1252 * users can see what limit is set by the BIOS.
1253 * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not
1254 * exist at all. In this case, we do not show the contraints in powercap.
1256 * Called after domains are detected and initialized.
1258 static void rapl_detect_powerlimit(struct rapl_domain *rd)
1263 /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */
1264 if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) {
1266 pr_info("RAPL %s domain %s locked by BIOS\n",
1267 rd->rp->name, rd->name);
1268 rd->state |= DOMAIN_STATE_BIOS_LOCKED;
1271 /* check if power limit MSRs exists, otherwise domain is monitoring only */
1272 for (i = 0; i < NR_POWER_LIMITS; i++) {
1273 int prim = rd->rpl[i].prim_id;
1274 if (rapl_read_data_raw(rd, prim, false, &val64))
1275 rd->rpl[i].name = NULL;
1279 /* Detect active and valid domains for the given CPU, caller must
1280 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1282 static int rapl_detect_domains(struct rapl_package *rp, int cpu)
1284 struct rapl_domain *rd;
1287 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1288 /* use physical package id to read counters */
1289 if (!rapl_check_domain(cpu, i, rp)) {
1290 rp->domain_map |= 1 << i;
1291 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1294 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
1295 if (!rp->nr_domains) {
1296 pr_debug("no valid rapl domains found in %s\n", rp->name);
1299 pr_debug("found %d domains on %s\n", rp->nr_domains, rp->name);
1301 rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
1306 rapl_init_domains(rp);
1308 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++)
1309 rapl_detect_powerlimit(rd);
1314 /* called from CPU hotplug notifier, hotplug lock held */
1315 static void rapl_remove_package(struct rapl_package *rp)
1317 struct rapl_domain *rd, *rd_package = NULL;
1319 package_power_limit_irq_restore(rp);
1321 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1322 rapl_write_data_raw(rd, PL1_ENABLE, 0);
1323 rapl_write_data_raw(rd, PL1_CLAMP, 0);
1324 if (find_nr_power_limit(rd) > 1) {
1325 rapl_write_data_raw(rd, PL2_ENABLE, 0);
1326 rapl_write_data_raw(rd, PL2_CLAMP, 0);
1328 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1332 pr_debug("remove package, undo power limit on %s: %s\n",
1333 rp->name, rd->name);
1334 powercap_unregister_zone(rp->priv->control_type, &rd->power_zone);
1336 /* do parent zone last */
1337 powercap_unregister_zone(rp->priv->control_type, &rd_package->power_zone);
1338 list_del(&rp->plist);
1342 /* called from CPU hotplug notifier, hotplug lock held */
1343 static struct rapl_package *rapl_add_package(int cpu, struct rapl_if_priv *priv)
1345 int id = topology_logical_die_id(cpu);
1346 struct rapl_package *rp;
1347 struct cpuinfo_x86 *c = &cpu_data(cpu);
1350 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
1352 return ERR_PTR(-ENOMEM);
1354 /* add the new package to the list */
1359 if (topology_max_die_per_package() > 1)
1360 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH,
1361 "package-%d-die-%d", c->phys_proc_id, c->cpu_die_id);
1363 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d",
1366 /* check if the package contains valid domains */
1367 if (rapl_detect_domains(rp, cpu) ||
1368 rapl_defaults->check_unit(rp, cpu)) {
1370 goto err_free_package;
1372 ret = rapl_package_register_powercap(rp);
1374 INIT_LIST_HEAD(&rp->plist);
1375 list_add(&rp->plist, &rapl_packages);
1382 return ERR_PTR(ret);
1385 /* Handles CPU hotplug on multi-socket systems.
1386 * If a CPU goes online as the first CPU of the physical package
1387 * we add the RAPL package to the system. Similarly, when the last
1388 * CPU of the package is removed, we remove the RAPL package and its
1389 * associated domains. Cooling devices are handled accordingly at
1392 static int rapl_cpu_online(unsigned int cpu)
1394 struct rapl_package *rp;
1396 rp = rapl_find_package_domain(cpu, &rapl_msr_priv);
1398 rp = rapl_add_package(cpu, &rapl_msr_priv);
1402 cpumask_set_cpu(cpu, &rp->cpumask);
1406 static int rapl_cpu_down_prep(unsigned int cpu)
1408 struct rapl_package *rp;
1411 rp = rapl_find_package_domain(cpu, &rapl_msr_priv);
1415 cpumask_clear_cpu(cpu, &rp->cpumask);
1416 lead_cpu = cpumask_first(&rp->cpumask);
1417 if (lead_cpu >= nr_cpu_ids)
1418 rapl_remove_package(rp);
1419 else if (rp->lead_cpu == cpu)
1420 rp->lead_cpu = lead_cpu;
1424 static void power_limit_state_save(void)
1426 struct rapl_package *rp;
1427 struct rapl_domain *rd;
1431 list_for_each_entry(rp, &rapl_packages, plist) {
1432 if (!rp->power_zone)
1434 rd = power_zone_to_rapl_domain(rp->power_zone);
1435 nr_pl = find_nr_power_limit(rd);
1436 for (i = 0; i < nr_pl; i++) {
1437 switch (rd->rpl[i].prim_id) {
1439 ret = rapl_read_data_raw(rd,
1442 &rd->rpl[i].last_power_limit);
1444 rd->rpl[i].last_power_limit = 0;
1447 ret = rapl_read_data_raw(rd,
1450 &rd->rpl[i].last_power_limit);
1452 rd->rpl[i].last_power_limit = 0;
1460 static void power_limit_state_restore(void)
1462 struct rapl_package *rp;
1463 struct rapl_domain *rd;
1467 list_for_each_entry(rp, &rapl_packages, plist) {
1468 if (!rp->power_zone)
1470 rd = power_zone_to_rapl_domain(rp->power_zone);
1471 nr_pl = find_nr_power_limit(rd);
1472 for (i = 0; i < nr_pl; i++) {
1473 switch (rd->rpl[i].prim_id) {
1475 if (rd->rpl[i].last_power_limit)
1476 rapl_write_data_raw(rd,
1478 rd->rpl[i].last_power_limit);
1481 if (rd->rpl[i].last_power_limit)
1482 rapl_write_data_raw(rd,
1484 rd->rpl[i].last_power_limit);
1492 static int rapl_pm_callback(struct notifier_block *nb,
1493 unsigned long mode, void *_unused)
1496 case PM_SUSPEND_PREPARE:
1497 power_limit_state_save();
1499 case PM_POST_SUSPEND:
1500 power_limit_state_restore();
1506 static struct notifier_block rapl_pm_notifier = {
1507 .notifier_call = rapl_pm_callback,
1510 static int __init rapl_init(void)
1512 const struct x86_cpu_id *id;
1515 id = x86_match_cpu(rapl_ids);
1517 pr_err("driver does not support CPU family %d model %d\n",
1518 boot_cpu_data.x86, boot_cpu_data.x86_model);
1523 rapl_defaults = (struct rapl_defaults *)id->driver_data;
1525 ret = rapl_register_powercap();
1529 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online",
1530 rapl_cpu_online, rapl_cpu_down_prep);
1533 rapl_msr_priv.pcap_rapl_online = ret;
1535 /* Don't bail out if PSys is not supported */
1536 rapl_register_psys();
1538 ret = register_pm_notifier(&rapl_pm_notifier);
1545 cpuhp_remove_state(rapl_msr_priv.pcap_rapl_online);
1548 rapl_unregister_powercap();
1552 static void __exit rapl_exit(void)
1554 unregister_pm_notifier(&rapl_pm_notifier);
1555 cpuhp_remove_state(rapl_msr_priv.pcap_rapl_online);
1556 rapl_unregister_powercap();
1559 module_init(rapl_init);
1560 module_exit(rapl_exit);
1562 MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
1563 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
1564 MODULE_LICENSE("GPL v2");