drivers/power/reset/oxnas-restart.c

   1 // SPDX-License-Identifier: (GPL-2.0)
   2 /*
   3  * oxnas SoC reset driver
   4  * based on:
   5  * Microsemi MIPS SoC reset driver
   6  * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
   7  *
   8  * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
   9  * Copyright (c) 2017 Microsemi Corporation
  10  * Copyright (c) 2020 Daniel Golle <daniel@makrotopia.org>
  11  */
  12 #include <linux/delay.h>
  13 #include <linux/io.h>
  14 #include <linux/notifier.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/reboot.h>
  18 #include <linux/regmap.h>
  19
  20 /* bit numbers of reset control register */
  21 #define OX820_SYS_CTRL_RST_SCU                0
  22 #define OX820_SYS_CTRL_RST_COPRO              1
  23 #define OX820_SYS_CTRL_RST_ARM0               2
  24 #define OX820_SYS_CTRL_RST_ARM1               3
  25 #define OX820_SYS_CTRL_RST_USBHS              4
  26 #define OX820_SYS_CTRL_RST_USBHSPHYA          5
  27 #define OX820_SYS_CTRL_RST_MACA               6
  28 #define OX820_SYS_CTRL_RST_MAC                OX820_SYS_CTRL_RST_MACA
  29 #define OX820_SYS_CTRL_RST_PCIEA              7
  30 #define OX820_SYS_CTRL_RST_SGDMA              8
  31 #define OX820_SYS_CTRL_RST_CIPHER             9
  32 #define OX820_SYS_CTRL_RST_DDR                10
  33 #define OX820_SYS_CTRL_RST_SATA               11
  34 #define OX820_SYS_CTRL_RST_SATA_LINK          12
  35 #define OX820_SYS_CTRL_RST_SATA_PHY           13
  36 #define OX820_SYS_CTRL_RST_PCIEPHY            14
  37 #define OX820_SYS_CTRL_RST_STATIC             15
  38 #define OX820_SYS_CTRL_RST_GPIO               16
  39 #define OX820_SYS_CTRL_RST_UART1              17
  40 #define OX820_SYS_CTRL_RST_UART2              18
  41 #define OX820_SYS_CTRL_RST_MISC               19
  42 #define OX820_SYS_CTRL_RST_I2S                20
  43 #define OX820_SYS_CTRL_RST_SD                 21
  44 #define OX820_SYS_CTRL_RST_MACB               22
  45 #define OX820_SYS_CTRL_RST_PCIEB              23
  46 #define OX820_SYS_CTRL_RST_VIDEO              24
  47 #define OX820_SYS_CTRL_RST_DDR_PHY            25
  48 #define OX820_SYS_CTRL_RST_USBHSPHYB          26
  49 #define OX820_SYS_CTRL_RST_USBDEV             27
  50 #define OX820_SYS_CTRL_RST_ARMDBG             29
  51 #define OX820_SYS_CTRL_RST_PLLA               30
  52 #define OX820_SYS_CTRL_RST_PLLB               31
  53
  54 /* bit numbers of clock control register */
  55 #define OX820_SYS_CTRL_CLK_COPRO              0
  56 #define OX820_SYS_CTRL_CLK_DMA                1
  57 #define OX820_SYS_CTRL_CLK_CIPHER             2
  58 #define OX820_SYS_CTRL_CLK_SD                 3
  59 #define OX820_SYS_CTRL_CLK_SATA               4
  60 #define OX820_SYS_CTRL_CLK_I2S                5
  61 #define OX820_SYS_CTRL_CLK_USBHS              6
  62 #define OX820_SYS_CTRL_CLK_MACA               7
  63 #define OX820_SYS_CTRL_CLK_MAC                OX820_SYS_CTRL_CLK_MACA
  64 #define OX820_SYS_CTRL_CLK_PCIEA              8
  65 #define OX820_SYS_CTRL_CLK_STATIC             9
  66 #define OX820_SYS_CTRL_CLK_MACB               10
  67 #define OX820_SYS_CTRL_CLK_PCIEB              11
  68 #define OX820_SYS_CTRL_CLK_REF600             12
  69 #define OX820_SYS_CTRL_CLK_USBDEV             13
  70 #define OX820_SYS_CTRL_CLK_DDR                14
  71 #define OX820_SYS_CTRL_CLK_DDRPHY             15
  72 #define OX820_SYS_CTRL_CLK_DDRCK              16
  73
  74 /* Regmap offsets */
  75 #define OX820_CLK_SET_REGOFFSET               0x2c
  76 #define OX820_CLK_CLR_REGOFFSET               0x30
  77 #define OX820_RST_SET_REGOFFSET               0x34
  78 #define OX820_RST_CLR_REGOFFSET               0x38
  79 #define OX820_SECONDARY_SEL_REGOFFSET         0x14
  80 #define OX820_TERTIARY_SEL_REGOFFSET          0x8c
  81 #define OX820_QUATERNARY_SEL_REGOFFSET        0x94
  82 #define OX820_DEBUG_SEL_REGOFFSET             0x9c
  83 #define OX820_ALTERNATIVE_SEL_REGOFFSET       0xa4
  84 #define OX820_PULLUP_SEL_REGOFFSET            0xac
  85 #define OX820_SEC_SECONDARY_SEL_REGOFFSET     0x100014
  86 #define OX820_SEC_TERTIARY_SEL_REGOFFSET      0x10008c
  87 #define OX820_SEC_QUATERNARY_SEL_REGOFFSET    0x100094
  88 #define OX820_SEC_DEBUG_SEL_REGOFFSET         0x10009c
  89 #define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET   0x1000a4
  90 #define OX820_SEC_PULLUP_SEL_REGOFFSET        0x1000ac
  91
  92 struct oxnas_restart_context {
  93         struct regmap *sys_ctrl;
  94         struct notifier_block restart_handler;
  95 };
  96
  97 static int ox820_restart_handle(struct notifier_block *this,
  98                                  unsigned long mode, void *cmd)
  99 {
 100         struct oxnas_restart_context *ctx = container_of(this, struct
 101                                                         oxnas_restart_context,
 102                                                         restart_handler);
 103         u32 value;
 104
 105         /*
 106          * Assert reset to cores as per power on defaults
 107          * Don't touch the DDR interface as things will come to an impromptu
 108          * stop NB Possibly should be asserting reset for PLLB, but there are
 109          * timing concerns here according to the docs
 110          */
 111         value = BIT(OX820_SYS_CTRL_RST_COPRO)           |
 112                 BIT(OX820_SYS_CTRL_RST_USBHS)           |
 113                 BIT(OX820_SYS_CTRL_RST_USBHSPHYA)       |
 114                 BIT(OX820_SYS_CTRL_RST_MACA)            |
 115                 BIT(OX820_SYS_CTRL_RST_PCIEA)           |
 116                 BIT(OX820_SYS_CTRL_RST_SGDMA)           |
 117                 BIT(OX820_SYS_CTRL_RST_CIPHER)          |
 118                 BIT(OX820_SYS_CTRL_RST_SATA)            |
 119                 BIT(OX820_SYS_CTRL_RST_SATA_LINK)       |
 120                 BIT(OX820_SYS_CTRL_RST_SATA_PHY)        |
 121                 BIT(OX820_SYS_CTRL_RST_PCIEPHY)         |
 122                 BIT(OX820_SYS_CTRL_RST_STATIC)          |
 123                 BIT(OX820_SYS_CTRL_RST_UART1)           |
 124                 BIT(OX820_SYS_CTRL_RST_UART2)           |
 125                 BIT(OX820_SYS_CTRL_RST_MISC)            |
 126                 BIT(OX820_SYS_CTRL_RST_I2S)             |
 127                 BIT(OX820_SYS_CTRL_RST_SD)              |
 128                 BIT(OX820_SYS_CTRL_RST_MACB)            |
 129                 BIT(OX820_SYS_CTRL_RST_PCIEB)           |
 130                 BIT(OX820_SYS_CTRL_RST_VIDEO)           |
 131                 BIT(OX820_SYS_CTRL_RST_USBHSPHYB)       |
 132                 BIT(OX820_SYS_CTRL_RST_USBDEV);
 133
 134         regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
 135
 136         /* Release reset to cores as per power on defaults */
 137         regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET,
 138                         BIT(OX820_SYS_CTRL_RST_GPIO));
 139
 140         /*
 141          * Disable clocks to cores as per power-on defaults - must leave DDR
 142          * related clocks enabled otherwise we'll stop rather abruptly.
 143          */
 144         value = BIT(OX820_SYS_CTRL_CLK_COPRO)           |
 145                 BIT(OX820_SYS_CTRL_CLK_DMA)             |
 146                 BIT(OX820_SYS_CTRL_CLK_CIPHER)          |
 147                 BIT(OX820_SYS_CTRL_CLK_SD)              |
 148                 BIT(OX820_SYS_CTRL_CLK_SATA)            |
 149                 BIT(OX820_SYS_CTRL_CLK_I2S)             |
 150                 BIT(OX820_SYS_CTRL_CLK_USBHS)           |
 151                 BIT(OX820_SYS_CTRL_CLK_MAC)             |
 152                 BIT(OX820_SYS_CTRL_CLK_PCIEA)           |
 153                 BIT(OX820_SYS_CTRL_CLK_STATIC)          |
 154                 BIT(OX820_SYS_CTRL_CLK_MACB)            |
 155                 BIT(OX820_SYS_CTRL_CLK_PCIEB)           |
 156                 BIT(OX820_SYS_CTRL_CLK_REF600)          |
 157                 BIT(OX820_SYS_CTRL_CLK_USBDEV);
 158
 159         regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value);
 160
 161         /* Enable clocks to cores as per power-on defaults */
 162
 163         /* Set sys-control pin mux'ing as per power-on defaults */
 164         regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0);
 165         regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0);
 166         regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0);
 167         regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0);
 168         regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0);
 169         regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0);
 170
 171         regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0);
 172         regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0);
 173         regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0);
 174         regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0);
 175         regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
 176         regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0);
 177
 178         /*
 179          * No need to save any state, as the ROM loader can determine whether
 180          * reset is due to power cycling or programatic action, just hit the
 181          * (self-clearing) CPU reset bit of the block reset register
 182          */
 183         value =
 184                 BIT(OX820_SYS_CTRL_RST_SCU) |
 185                 BIT(OX820_SYS_CTRL_RST_ARM0) |
 186                 BIT(OX820_SYS_CTRL_RST_ARM1);
 187
 188         regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
 189
 190         pr_emerg("Unable to restart system\n");
 191         return NOTIFY_DONE;
 192 }
 193
 194 static int ox820_restart_probe(struct platform_device *pdev)
 195 {
 196         struct oxnas_restart_context *ctx;
 197         struct regmap *sys_ctrl;
 198         struct device *dev = &pdev->dev;
 199         int err = 0;
 200
 201         sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node);
 202         if (IS_ERR(sys_ctrl))
 203                 return PTR_ERR(sys_ctrl);
 204
 205         ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
 206         if (!ctx)
 207                 return -ENOMEM;
 208
 209         ctx->sys_ctrl = sys_ctrl;
 210         ctx->restart_handler.notifier_call = ox820_restart_handle;
 211         ctx->restart_handler.priority = 192;
 212         err = register_restart_handler(&ctx->restart_handler);
 213         if (err)
 214                 dev_err(dev, "can't register restart notifier (err=%d)\n", err);
 215
 216         return err;
 217 }
 218
 219 static const struct of_device_id ox820_restart_of_match[] = {
 220         { .compatible = "oxsemi,ox820-sys-ctrl" },
 221         {}
 222 };
 223
 224 static struct platform_driver ox820_restart_driver = {
 225         .probe = ox820_restart_probe,
 226         .driver = {
 227                 .name = "ox820-chip-reset",
 228                 .of_match_table = ox820_restart_of_match,
 229         },
 230 };
 231 builtin_platform_driver(ox820_restart_driver);