1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
6 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c:
7 * Copyright (C) 2012 rockchips
8 * zyw <zyw@rock-chips.com>
15 #include <power/rk8xx_pmic.h>
16 #include <power/pmic.h>
17 #include <power/regulator.h>
19 #ifndef CONFIG_SPL_BUILD
23 /* Not used or exisit register and configure */
26 /* Field Definitions */
27 #define RK808_BUCK_VSEL_MASK 0x3f
28 #define RK808_BUCK4_VSEL_MASK 0xf
29 #define RK808_LDO_VSEL_MASK 0x1f
32 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1)
33 #define RK809_BUCK5_VSEL_MASK 0x07
36 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * ((n) - 1))
37 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * ((n) - 1))
38 #define RK817_BUCK_VSEL_MASK 0x7f
39 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3)
42 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * ((n) - 1))
43 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * ((n) - 1))
44 #define RK817_LDO_VSEL_MASK 0x7f
47 #define RK817_POWER_EN(n) (0xb1 + (n))
48 #define RK817_POWER_SLP_EN(n) (0xb5 + (n))
50 #define RK818_BUCK_VSEL_MASK 0x3f
51 #define RK818_BUCK4_VSEL_MASK 0x1f
52 #define RK818_LDO_VSEL_MASK 0x1f
53 #define RK818_LDO3_ON_VSEL_MASK 0xf
54 #define RK818_BOOST_ON_VSEL_MASK 0xe0
55 #define RK818_USB_ILIM_SEL_MASK 0x0f
56 #define RK818_USB_CHG_SD_VSEL_MASK 0x70
61 #define RK805_RAMP_RATE_OFFSET 3
62 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET)
63 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET)
64 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET)
65 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET)
66 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET)
68 #define RK808_RAMP_RATE_OFFSET 3
69 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET)
70 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET)
71 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET)
72 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET)
73 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET)
75 #define RK817_RAMP_RATE_OFFSET 6
76 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET)
77 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET)
78 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET)
79 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET)
80 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET)
82 struct rk8xx_reg_info {
92 static const struct rk8xx_reg_info rk808_buck[] = {
93 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, },
94 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, },
95 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, },
96 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, },
99 static const struct rk8xx_reg_info rk816_buck[] = {
101 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
102 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
103 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
105 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
106 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
107 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
109 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
111 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
114 static const struct rk8xx_reg_info rk809_buck5[] = {
116 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, },
117 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, },
118 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, },
119 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, },
122 static const struct rk8xx_reg_info rk817_buck[] = {
124 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, },
125 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, },
126 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, },
128 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, },
129 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, },
130 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, },
132 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, },
133 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, },
134 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, },
136 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, },
137 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, },
138 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, },
141 static const struct rk8xx_reg_info rk818_buck[] = {
142 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, },
143 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, },
144 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
145 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
149 static const struct rk8xx_reg_info rk808_ldo[] = {
150 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
151 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
152 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, },
153 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
154 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
155 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
156 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
157 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
160 static const struct rk8xx_reg_info rk816_ldo[] = {
161 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
162 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
163 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
164 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
165 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
166 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
169 static const struct rk8xx_reg_info rk817_ldo[] = {
171 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, },
172 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, },
174 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, },
175 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, },
177 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, },
178 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, },
180 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, },
181 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, },
183 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, },
184 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, },
186 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, },
187 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, },
189 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, },
190 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, },
192 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, },
193 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, },
195 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, },
196 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, },
199 static const struct rk8xx_reg_info rk818_ldo[] = {
200 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
201 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
202 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, },
203 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
204 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
205 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
206 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
207 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
211 static const u16 rk818_chrg_cur_input_array[] = {
212 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
215 static const uint rk818_chrg_shutdown_vsel_array[] = {
216 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000
219 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
222 struct rk8xx_priv *priv = dev_get_priv(pmic);
224 switch (priv->variant) {
230 if (uvolt <= 1450000)
231 return &rk816_buck[num * 3 + 0];
232 else if (uvolt <= 2200000)
233 return &rk816_buck[num * 3 + 1];
235 return &rk816_buck[num * 3 + 2];
237 return &rk816_buck[num + 4];
245 return &rk817_buck[num * 3 + 0];
246 else if (uvolt < 2400000)
247 return &rk817_buck[num * 3 + 1];
249 return &rk817_buck[num * 3 + 2];
252 return &rk817_buck[num * 3 + 0];
253 else if (uvolt < 3400000)
254 return &rk817_buck[num * 3 + 1];
256 return &rk817_buck[num * 3 + 2];
257 /* BUCK5 for RK809 */
260 return &rk809_buck5[0];
261 else if (uvolt < 2800000)
262 return &rk809_buck5[1];
263 else if (uvolt < 3300000)
264 return &rk809_buck5[2];
266 return &rk809_buck5[3];
269 return &rk818_buck[num];
271 return &rk808_buck[num];
275 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
277 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
278 struct rk8xx_priv *priv = dev_get_priv(pmic);
279 int mask = info->vsel_mask;
282 if (info->vsel_reg == NA)
285 if (info->step_uv == 0) /* Fixed voltage */
288 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
290 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
291 __func__, uvolt, buck + 1, info->vsel_reg, mask, val);
293 if (priv->variant == RK816_ID) {
294 pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
295 return pmic_clrsetbits(pmic, RK816_REG_DCDC_EN2,
298 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
302 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
304 uint mask, value, en_reg;
306 struct rk8xx_priv *priv = dev_get_priv(pmic);
308 switch (priv->variant) {
313 en_reg = RK816_REG_DCDC_EN2;
315 en_reg = RK816_REG_DCDC_EN1;
318 value = ((1 << buck) | (1 << (buck + 4)));
320 value = ((0 << buck) | (1 << (buck + 4)));
321 ret = pmic_reg_write(pmic, en_reg, value);
328 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX,
333 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask,
340 value = ((1 << buck) | (1 << (buck + 4)));
342 value = ((0 << buck) | (1 << (buck + 4)));
343 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value);
344 /* BUCK5 for RK809 */
347 value = ((1 << 1) | (1 << 5));
349 value = ((0 << 1) | (1 << 5));
350 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value);
361 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
363 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
364 int mask = info->vsel_mask;
367 if (info->vsel_sleep_reg == NA)
370 if (info->step_uv == 0)
373 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
375 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
376 __func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val);
378 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
381 static int _buck_get_enable(struct udevice *pmic, int buck)
383 struct rk8xx_priv *priv = dev_get_priv(pmic);
387 switch (priv->variant) {
391 mask = 1 << (buck - 4);
392 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2);
395 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1);
401 ret = pmic_reg_read(pmic, REG_DCDC_EN);
409 ret = pmic_reg_read(pmic, RK817_POWER_EN(0));
410 /* BUCK5 for RK809 */
413 ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
421 return ret & mask ? true : false;
424 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
428 struct rk8xx_priv *priv = dev_get_priv(pmic);
430 switch (priv->variant) {
434 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask,
440 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask,
448 mask = 1 << 5; /* BUCK5 for RK809 */
449 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
459 static int _buck_get_suspend_enable(struct udevice *pmic, int buck)
461 struct rk8xx_priv *priv = dev_get_priv(pmic);
465 switch (priv->variant) {
469 val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN);
472 ret = val & mask ? 1 : 0;
477 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1);
480 ret = val & mask ? 0 : 1;
487 mask = 1 << 5; /* BUCK5 for RK809 */
489 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
492 ret = val & mask ? 1 : 0;
501 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
504 struct rk8xx_priv *priv = dev_get_priv(pmic);
506 switch (priv->variant) {
509 return &rk816_ldo[num];
513 return &rk817_ldo[num * 2 + 0];
515 return &rk817_ldo[num * 2 + 1];
517 return &rk818_ldo[num];
519 return &rk808_ldo[num];
523 static int _ldo_get_enable(struct udevice *pmic, int ldo)
525 struct rk8xx_priv *priv = dev_get_priv(pmic);
529 switch (priv->variant) {
533 mask = 1 << (ldo - 4);
534 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2);
537 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1);
543 ret = pmic_reg_read(pmic, REG_LDO_EN);
551 ret = pmic_reg_read(pmic, RK817_POWER_EN(1));
552 } else if (ldo < 8) {
553 mask = 1 << (ldo - 4);
554 ret = pmic_reg_read(pmic, RK817_POWER_EN(2));
555 } else if (ldo == 8) {
557 ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
567 return ret & mask ? true : false;
570 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable)
572 struct rk8xx_priv *priv = dev_get_priv(pmic);
573 uint mask, value, en_reg;
576 switch (priv->variant) {
581 en_reg = RK816_REG_LDO_EN2;
583 en_reg = RK816_REG_LDO_EN1;
586 value = ((1 << ldo) | (1 << (ldo + 4)));
588 value = ((0 << ldo) | (1 << (ldo + 4)));
590 ret = pmic_reg_write(pmic, en_reg, value);
595 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask,
601 en_reg = RK817_POWER_EN(1);
602 } else if (ldo < 8) {
604 en_reg = RK817_POWER_EN(2);
605 } else if (ldo == 8) {
607 en_reg = RK817_POWER_EN(3);
612 value = ((1 << ldo) | (1 << (ldo + 4)));
614 value = ((0 << ldo) | (1 << (ldo + 4)));
615 ret = pmic_reg_write(pmic, en_reg, value);
622 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
624 struct rk8xx_priv *priv = dev_get_priv(pmic);
628 switch (priv->variant) {
632 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask,
638 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask,
644 mask = 1 << 4; /* LDO9 */
645 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
649 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask,
658 static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo)
660 struct rk8xx_priv *priv = dev_get_priv(pmic);
664 switch (priv->variant) {
668 val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN);
671 ret = val & mask ? 1 : 0;
676 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2);
679 ret = val & mask ? 0 : 1;
684 mask = 1 << 4; /* LDO9 */
685 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
688 ret = val & mask ? 1 : 0;
691 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1));
694 ret = val & mask ? 1 : 0;
702 static int buck_get_value(struct udevice *dev)
704 int buck = dev->driver_data - 1;
705 /* We assume level-1 voltage is enough for usage in U-Boot */
706 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
707 int mask = info->vsel_mask;
710 if (info->vsel_reg == NA)
713 ret = pmic_reg_read(dev->parent, info->vsel_reg);
718 return info->min_uv + val * info->step_uv;
721 static int buck_set_value(struct udevice *dev, int uvolt)
723 int buck = dev->driver_data - 1;
725 return _buck_set_value(dev->parent, buck, uvolt);
728 static int buck_get_suspend_value(struct udevice *dev)
730 int buck = dev->driver_data - 1;
731 /* We assume level-1 voltage is enough for usage in U-Boot */
732 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
733 int mask = info->vsel_mask;
736 if (info->vsel_sleep_reg == NA)
739 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
745 return info->min_uv + val * info->step_uv;
748 static int buck_set_suspend_value(struct udevice *dev, int uvolt)
750 int buck = dev->driver_data - 1;
752 return _buck_set_suspend_value(dev->parent, buck, uvolt);
755 static int buck_set_enable(struct udevice *dev, bool enable)
757 int buck = dev->driver_data - 1;
759 return _buck_set_enable(dev->parent, buck, enable);
762 static int buck_set_suspend_enable(struct udevice *dev, bool enable)
764 int buck = dev->driver_data - 1;
766 return _buck_set_suspend_enable(dev->parent, buck, enable);
769 static int buck_get_suspend_enable(struct udevice *dev)
771 int buck = dev->driver_data - 1;
773 return _buck_get_suspend_enable(dev->parent, buck);
776 static int buck_get_enable(struct udevice *dev)
778 int buck = dev->driver_data - 1;
780 return _buck_get_enable(dev->parent, buck);
783 static int ldo_get_value(struct udevice *dev)
785 int ldo = dev->driver_data - 1;
786 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
787 int mask = info->vsel_mask;
790 if (info->vsel_reg == NA)
792 ret = pmic_reg_read(dev->parent, info->vsel_reg);
797 return info->min_uv + val * info->step_uv;
800 static int ldo_set_value(struct udevice *dev, int uvolt)
802 int ldo = dev->driver_data - 1;
803 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
804 int mask = info->vsel_mask;
807 if (info->vsel_reg == NA)
810 if (info->step_uv == 0)
813 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
815 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
816 __func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
818 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
821 static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
823 int ldo = dev->driver_data - 1;
824 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
825 int mask = info->vsel_mask;
828 if (info->vsel_sleep_reg == NA)
831 if (info->step_uv == 0)
834 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
836 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
837 __func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val);
839 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
842 static int ldo_get_suspend_value(struct udevice *dev)
844 int ldo = dev->driver_data - 1;
845 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
846 int mask = info->vsel_mask;
849 if (info->vsel_sleep_reg == NA)
852 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
858 return info->min_uv + val * info->step_uv;
861 static int ldo_set_enable(struct udevice *dev, bool enable)
863 int ldo = dev->driver_data - 1;
865 return _ldo_set_enable(dev->parent, ldo, enable);
868 static int ldo_set_suspend_enable(struct udevice *dev, bool enable)
870 int ldo = dev->driver_data - 1;
872 return _ldo_set_suspend_enable(dev->parent, ldo, enable);
875 static int ldo_get_suspend_enable(struct udevice *dev)
877 int ldo = dev->driver_data - 1;
879 return _ldo_get_suspend_enable(dev->parent, ldo);
882 static int ldo_get_enable(struct udevice *dev)
884 int ldo = dev->driver_data - 1;
886 return _ldo_get_enable(dev->parent, ldo);
889 static int switch_set_enable(struct udevice *dev, bool enable)
891 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
892 int ret = 0, sw = dev->driver_data - 1;
895 switch (priv->variant) {
897 mask = 1 << (sw + 5);
898 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
902 mask = (1 << (sw + 2)) | (1 << (sw + 6));
903 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask,
908 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
913 debug("%s: switch%d, enable=%d, mask=0x%x\n",
914 __func__, sw + 1, enable, mask);
919 static int switch_get_enable(struct udevice *dev)
921 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
922 int ret = 0, sw = dev->driver_data - 1;
925 switch (priv->variant) {
927 mask = 1 << (sw + 5);
928 ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
931 mask = 1 << (sw + 2);
932 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3));
936 ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
943 return ret & mask ? true : false;
946 static int switch_set_suspend_value(struct udevice *dev, int uvolt)
951 static int switch_get_suspend_value(struct udevice *dev)
956 static int switch_set_suspend_enable(struct udevice *dev, bool enable)
958 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
959 int ret = 0, sw = dev->driver_data - 1;
962 switch (priv->variant) {
964 mask = 1 << (sw + 5);
965 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
969 mask = 1 << (sw + 6);
970 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask,
975 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
980 debug("%s: switch%d, enable=%d, mask=0x%x\n",
981 __func__, sw + 1, enable, mask);
986 static int switch_get_suspend_enable(struct udevice *dev)
988 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
989 int val, ret = 0, sw = dev->driver_data - 1;
992 switch (priv->variant) {
994 mask = 1 << (sw + 5);
995 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
998 ret = val & mask ? 0 : 1;
1001 mask = 1 << (sw + 6);
1002 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
1005 ret = val & mask ? 1 : 0;
1009 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
1012 ret = val & mask ? 0 : 1;
1020 * RK8xx switch does not need to set the voltage,
1021 * but if dts set regulator-min-microvolt/regulator-max-microvolt,
1022 * will cause regulator set value fail and not to enable this switch.
1023 * So add an empty function to return success.
1025 static int switch_get_value(struct udevice *dev)
1030 static int switch_set_value(struct udevice *dev, int uvolt)
1035 static int rk8xx_buck_probe(struct udevice *dev)
1037 struct dm_regulator_uclass_plat *uc_pdata;
1039 uc_pdata = dev_get_uclass_plat(dev);
1041 uc_pdata->type = REGULATOR_TYPE_BUCK;
1042 uc_pdata->mode_count = 0;
1047 static int rk8xx_ldo_probe(struct udevice *dev)
1049 struct dm_regulator_uclass_plat *uc_pdata;
1051 uc_pdata = dev_get_uclass_plat(dev);
1053 uc_pdata->type = REGULATOR_TYPE_LDO;
1054 uc_pdata->mode_count = 0;
1059 static int rk8xx_switch_probe(struct udevice *dev)
1061 struct dm_regulator_uclass_plat *uc_pdata;
1063 uc_pdata = dev_get_uclass_plat(dev);
1065 uc_pdata->type = REGULATOR_TYPE_FIXED;
1066 uc_pdata->mode_count = 0;
1071 static const struct dm_regulator_ops rk8xx_buck_ops = {
1072 .get_value = buck_get_value,
1073 .set_value = buck_set_value,
1074 .set_suspend_value = buck_set_suspend_value,
1075 .get_suspend_value = buck_get_suspend_value,
1076 .get_enable = buck_get_enable,
1077 .set_enable = buck_set_enable,
1078 .set_suspend_enable = buck_set_suspend_enable,
1079 .get_suspend_enable = buck_get_suspend_enable,
1082 static const struct dm_regulator_ops rk8xx_ldo_ops = {
1083 .get_value = ldo_get_value,
1084 .set_value = ldo_set_value,
1085 .set_suspend_value = ldo_set_suspend_value,
1086 .get_suspend_value = ldo_get_suspend_value,
1087 .get_enable = ldo_get_enable,
1088 .set_enable = ldo_set_enable,
1089 .set_suspend_enable = ldo_set_suspend_enable,
1090 .get_suspend_enable = ldo_get_suspend_enable,
1093 static const struct dm_regulator_ops rk8xx_switch_ops = {
1094 .get_value = switch_get_value,
1095 .set_value = switch_set_value,
1096 .get_enable = switch_get_enable,
1097 .set_enable = switch_set_enable,
1098 .set_suspend_enable = switch_set_suspend_enable,
1099 .get_suspend_enable = switch_get_suspend_enable,
1100 .set_suspend_value = switch_set_suspend_value,
1101 .get_suspend_value = switch_get_suspend_value,
1104 U_BOOT_DRIVER(rk8xx_buck) = {
1105 .name = "rk8xx_buck",
1106 .id = UCLASS_REGULATOR,
1107 .ops = &rk8xx_buck_ops,
1108 .probe = rk8xx_buck_probe,
1111 U_BOOT_DRIVER(rk8xx_ldo) = {
1112 .name = "rk8xx_ldo",
1113 .id = UCLASS_REGULATOR,
1114 .ops = &rk8xx_ldo_ops,
1115 .probe = rk8xx_ldo_probe,
1118 U_BOOT_DRIVER(rk8xx_switch) = {
1119 .name = "rk8xx_switch",
1120 .id = UCLASS_REGULATOR,
1121 .ops = &rk8xx_switch_ops,
1122 .probe = rk8xx_switch_probe,
1126 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
1130 ret = _buck_set_value(pmic, buck, uvolt);
1134 return _buck_set_enable(pmic, buck, true);
1137 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma)
1141 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++)
1142 if (current_ma <= rk818_chrg_cur_input_array[i])
1145 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i);
1148 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
1152 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++)
1153 if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
1156 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,