drivers/power/domain/meson-ee-pwrc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2019 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <power-domain-uclass.h>
  12 #include <regmap.h>
  13 #include <syscon.h>
  14 #include <reset.h>
  15 #include <clk.h>
  16 #include <dt-bindings/power/meson-g12a-power.h>
  17 #include <dt-bindings/power/meson-sm1-power.h>
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21
  22 /* AO Offsets */
  23
  24 #define AO_RTI_GEN_PWR_SLEEP0           (0x3a << 2)
  25 #define AO_RTI_GEN_PWR_ISO0             (0x3b << 2)
  26
  27 /* HHI Offsets */
  28
  29 #define HHI_MEM_PD_REG0                 (0x40 << 2)
  30 #define HHI_VPU_MEM_PD_REG0             (0x41 << 2)
  31 #define HHI_VPU_MEM_PD_REG1             (0x42 << 2)
  32 #define HHI_VPU_MEM_PD_REG3             (0x43 << 2)
  33 #define HHI_VPU_MEM_PD_REG4             (0x44 << 2)
  34 #define HHI_AUDIO_MEM_PD_REG0           (0x45 << 2)
  35 #define HHI_NANOQ_MEM_PD_REG0           (0x46 << 2)
  36 #define HHI_NANOQ_MEM_PD_REG1           (0x47 << 2)
  37 #define HHI_VPU_MEM_PD_REG2             (0x4d << 2)
  38
  39 struct meson_ee_pwrc;
  40 struct meson_ee_pwrc_domain;
  41
  42 struct meson_ee_pwrc_mem_domain {
  43         unsigned int reg;
  44         unsigned int mask;
  45 };
  46
  47 struct meson_ee_pwrc_top_domain {
  48         unsigned int sleep_reg;
  49         unsigned int sleep_mask;
  50         unsigned int iso_reg;
  51         unsigned int iso_mask;
  52 };
  53
  54 struct meson_ee_pwrc_domain_desc {
  55         char *name;
  56         unsigned int reset_names_count;
  57         unsigned int clk_names_count;
  58         struct meson_ee_pwrc_top_domain *top_pd;
  59         unsigned int mem_pd_count;
  60         struct meson_ee_pwrc_mem_domain *mem_pd;
  61         bool (*get_power)(struct power_domain *power_domain);
  62 };
  63
  64 struct meson_ee_pwrc_domain_data {
  65         unsigned int count;
  66         struct meson_ee_pwrc_domain_desc *domains;
  67 };
  68
  69 /* TOP Power Domains */
  70
  71 static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
  72         .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
  73         .sleep_mask = BIT(8),
  74         .iso_reg = AO_RTI_GEN_PWR_SLEEP0,
  75         .iso_mask = BIT(9),
  76 };
  77
  78 #define SM1_EE_PD(__bit)                                        \
  79         {                                                       \
  80                 .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,             \
  81                 .sleep_mask = BIT(__bit),                       \
  82                 .iso_reg = AO_RTI_GEN_PWR_ISO0,                 \
  83                 .iso_mask = BIT(__bit),                         \
  84         }
  85
  86 static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
  87 static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
  88 static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
  89 static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
  90 static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
  91
  92 /* Memory PD Domains */
  93
  94 #define VPU_MEMPD(__reg)                                        \
  95         { __reg, GENMASK(1, 0) },                               \
  96         { __reg, GENMASK(3, 2) },                               \
  97         { __reg, GENMASK(5, 4) },                               \
  98         { __reg, GENMASK(7, 6) },                               \
  99         { __reg, GENMASK(9, 8) },                               \
 100         { __reg, GENMASK(11, 10) },                             \
 101         { __reg, GENMASK(13, 12) },                             \
 102         { __reg, GENMASK(15, 14) },                             \
 103         { __reg, GENMASK(17, 16) },                             \
 104         { __reg, GENMASK(19, 18) },                             \
 105         { __reg, GENMASK(21, 20) },                             \
 106         { __reg, GENMASK(23, 22) },                             \
 107         { __reg, GENMASK(25, 24) },                             \
 108         { __reg, GENMASK(27, 26) },                             \
 109         { __reg, GENMASK(29, 28) },                             \
 110         { __reg, GENMASK(31, 30) }
 111
 112 #define VPU_HHI_MEMPD(__reg)                                    \
 113         { __reg, BIT(8) },                                      \
 114         { __reg, BIT(9) },                                      \
 115         { __reg, BIT(10) },                                     \
 116         { __reg, BIT(11) },                                     \
 117         { __reg, BIT(12) },                                     \
 118         { __reg, BIT(13) },                                     \
 119         { __reg, BIT(14) },                                     \
 120         { __reg, BIT(15) }
 121
 122 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
 123         VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
 124         VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
 125         VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
 126         VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
 127 };
 128
 129 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
 130         { HHI_MEM_PD_REG0, GENMASK(3, 2) },
 131 };
 132
 133 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
 134         VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
 135         VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
 136         VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
 137         VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
 138         { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
 139         { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
 140         { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
 141         { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
 142         VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
 143 };
 144
 145 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
 146         { HHI_NANOQ_MEM_PD_REG0, 0xff },
 147         { HHI_NANOQ_MEM_PD_REG1, 0xff },
 148 };
 149
 150 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
 151         { HHI_MEM_PD_REG0, GENMASK(31, 30) },
 152 };
 153
 154 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
 155         { HHI_MEM_PD_REG0, GENMASK(29, 26) },
 156 };
 157
 158 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
 159         { HHI_MEM_PD_REG0, GENMASK(25, 18) },
 160 };
 161
 162 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
 163         { HHI_MEM_PD_REG0, GENMASK(5, 4) },
 164         { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
 165         { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
 166         { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
 167         { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
 168         { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
 169         { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
 170         { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
 171         { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
 172         { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
 173         { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
 174         { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
 175         { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
 176 };
 177
 178 #define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks)  \
 179         {                                                               \
 180                 .name = __name,                                         \
 181                 .reset_names_count = __resets,                          \
 182                 .clk_names_count = __clks,                              \
 183                 .top_pd = __top_pd,                                     \
 184                 .mem_pd_count = ARRAY_SIZE(__mem),                      \
 185                 .mem_pd = __mem,                                        \
 186                 .get_power = __get_power,                               \
 187         }
 188
 189 #define TOP_PD(__name, __top_pd, __mem, __get_power)                    \
 190         {                                                               \
 191                 .name = __name,                                         \
 192                 .top_pd = __top_pd,                                     \
 193                 .mem_pd_count = ARRAY_SIZE(__mem),                      \
 194                 .mem_pd = __mem,                                        \
 195                 .get_power = __get_power,                               \
 196         }
 197
 198 #define MEM_PD(__name, __mem)                                           \
 199         TOP_PD(__name, NULL, __mem, NULL)
 200
 201 static bool pwrc_ee_get_power(struct power_domain *power_domain);
 202
 203 static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
 204         [PWRC_G12A_VPU_ID]  = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
 205                                      pwrc_ee_get_power, 11, 2),
 206         [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
 207 };
 208
 209 static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
 210         [PWRC_SM1_VPU_ID]  = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
 211                                     pwrc_ee_get_power, 11, 2),
 212         [PWRC_SM1_NNA_ID]  = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
 213                                     pwrc_ee_get_power),
 214         [PWRC_SM1_USB_ID]  = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
 215                                     pwrc_ee_get_power),
 216         [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
 217                                     pwrc_ee_get_power),
 218         [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
 219                                     pwrc_ee_get_power),
 220         [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
 221         [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
 222 };
 223
 224 struct meson_ee_pwrc_priv {
 225         struct regmap *regmap_ao;
 226         struct regmap *regmap_hhi;
 227         struct reset_ctl_bulk resets;
 228         struct clk_bulk clks;
 229         const struct meson_ee_pwrc_domain_data *data;
 230 };
 231
 232 static bool pwrc_ee_get_power(struct power_domain *power_domain)
 233 {
 234         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 235         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 236         u32 reg;
 237
 238         pwrc_domain = &priv->data->domains[power_domain->id];
 239
 240         regmap_read(priv->regmap_ao,
 241                     pwrc_domain->top_pd->sleep_reg, &reg);
 242
 243         return (reg & pwrc_domain->top_pd->sleep_mask);
 244 }
 245
 246 static int meson_ee_pwrc_request(struct power_domain *power_domain)
 247 {
 248         return 0;
 249 }
 250
 251 static int meson_ee_pwrc_free(struct power_domain *power_domain)
 252 {
 253         return 0;
 254 }
 255
 256 static int meson_ee_pwrc_off(struct power_domain *power_domain)
 257 {
 258         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 259         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 260         int i;
 261
 262         pwrc_domain = &priv->data->domains[power_domain->id];
 263
 264         if (pwrc_domain->top_pd)
 265                 regmap_update_bits(priv->regmap_ao,
 266                                    pwrc_domain->top_pd->sleep_reg,
 267                                    pwrc_domain->top_pd->sleep_mask,
 268                                    pwrc_domain->top_pd->sleep_mask);
 269         udelay(20);
 270
 271         for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
 272                 regmap_update_bits(priv->regmap_hhi,
 273                                    pwrc_domain->mem_pd[i].reg,
 274                                    pwrc_domain->mem_pd[i].mask,
 275                                    pwrc_domain->mem_pd[i].mask);
 276
 277         udelay(20);
 278
 279         if (pwrc_domain->top_pd)
 280                 regmap_update_bits(priv->regmap_ao,
 281                                    pwrc_domain->top_pd->iso_reg,
 282                                    pwrc_domain->top_pd->iso_mask,
 283                                    pwrc_domain->top_pd->iso_mask);
 284
 285         if (pwrc_domain->clk_names_count) {
 286                 mdelay(20);
 287                 clk_disable_bulk(&priv->clks);
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int meson_ee_pwrc_on(struct power_domain *power_domain)
 294 {
 295         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 296         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 297         int i, ret;
 298
 299         pwrc_domain = &priv->data->domains[power_domain->id];
 300
 301         if (pwrc_domain->top_pd)
 302                 regmap_update_bits(priv->regmap_ao,
 303                                    pwrc_domain->top_pd->sleep_reg,
 304                                    pwrc_domain->top_pd->sleep_mask, 0);
 305         udelay(20);
 306
 307         for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
 308                 regmap_update_bits(priv->regmap_hhi,
 309                                    pwrc_domain->mem_pd[i].reg,
 310                                    pwrc_domain->mem_pd[i].mask, 0);
 311
 312         udelay(20);
 313
 314         if (pwrc_domain->reset_names_count) {
 315                 ret = reset_assert_bulk(&priv->resets);
 316                 if (ret)
 317                         return ret;
 318         }
 319
 320         if (pwrc_domain->top_pd)
 321                 regmap_update_bits(priv->regmap_ao,
 322                                    pwrc_domain->top_pd->iso_reg,
 323                                    pwrc_domain->top_pd->iso_mask, 0);
 324
 325         if (pwrc_domain->reset_names_count) {
 326                 ret = reset_deassert_bulk(&priv->resets);
 327                 if (ret)
 328                         return ret;
 329         }
 330
 331         if (pwrc_domain->clk_names_count)
 332                 return clk_enable_bulk(&priv->clks);
 333
 334         return 0;
 335 }
 336
 337 static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain,
 338                                   struct ofnode_phandle_args *args)
 339 {
 340         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 341
 342         /* #power-domain-cells is 1 */
 343
 344         if (args->args_count < 1) {
 345                 debug("Invalid args_count: %d\n", args->args_count);
 346                 return -EINVAL;
 347         }
 348
 349         power_domain->id = args->args[0];
 350
 351         if (power_domain->id >= priv->data->count) {
 352                 debug("Invalid domain ID: %lu\n", power_domain->id);
 353                 return -EINVAL;
 354         }
 355
 356         return 0;
 357 }
 358
 359 struct power_domain_ops meson_ee_pwrc_ops = {
 360         .rfree = meson_ee_pwrc_free,
 361         .off = meson_ee_pwrc_off,
 362         .on = meson_ee_pwrc_on,
 363         .request = meson_ee_pwrc_request,
 364         .of_xlate = meson_ee_pwrc_of_xlate,
 365 };
 366
 367 static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
 368         .count = ARRAY_SIZE(g12a_pwrc_domains),
 369         .domains = g12a_pwrc_domains,
 370 };
 371
 372 static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
 373         .count = ARRAY_SIZE(sm1_pwrc_domains),
 374         .domains = sm1_pwrc_domains,
 375 };
 376
 377 static const struct udevice_id meson_ee_pwrc_ids[] = {
 378         {
 379                 .compatible = "amlogic,meson-g12a-pwrc",
 380                 .data = (unsigned long)&meson_ee_g12a_pwrc_data,
 381         },
 382         {
 383                 .compatible = "amlogic,meson-sm1-pwrc",
 384                 .data = (unsigned long)&meson_ee_sm1_pwrc_data,
 385         },
 386         { }
 387 };
 388
 389 static int meson_ee_pwrc_probe(struct udevice *dev)
 390 {
 391         struct meson_ee_pwrc_priv *priv = dev_get_priv(dev);
 392         u32 ao_phandle;
 393         ofnode ao_node;
 394         int ret;
 395
 396         priv->data = (void *)dev_get_driver_data(dev);
 397         if (!priv->data)
 398                 return -EINVAL;
 399
 400         priv->regmap_hhi = syscon_node_to_regmap(dev_get_parent(dev)->node);
 401         if (IS_ERR(priv->regmap_hhi))
 402                 return PTR_ERR(priv->regmap_hhi);
 403
 404         ret = ofnode_read_u32(dev->node, "amlogic,ao-sysctrl",
 405                               &ao_phandle);
 406         if (ret)
 407                 return ret;
 408
 409         ao_node = ofnode_get_by_phandle(ao_phandle);
 410         if (!ofnode_valid(ao_node))
 411                 return -EINVAL;
 412
 413         priv->regmap_ao = syscon_node_to_regmap(ao_node);
 414         if (IS_ERR(priv->regmap_ao))
 415                 return PTR_ERR(priv->regmap_ao);
 416
 417         ret = reset_get_bulk(dev, &priv->resets);
 418         if (ret)
 419                 return ret;
 420
 421         ret = clk_get_bulk(dev, &priv->clks);
 422         if (ret)
 423                 return ret;
 424
 425         return 0;
 426 }
 427
 428 U_BOOT_DRIVER(meson_ee_pwrc) = {
 429         .name = "meson_ee_pwrc",
 430         .id = UCLASS_POWER_DOMAIN,
 431         .of_match = meson_ee_pwrc_ids,
 432         .probe = meson_ee_pwrc_probe,
 433         .ops = &meson_ee_pwrc_ops,
 434         .priv_auto      = sizeof(struct meson_ee_pwrc_priv),
 435 };