drivers/platform/x86/intel/pmc/cnp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file contains platform specific structure definitions
   4  * and init function used by Cannon Lake Point PCH.
   5  *
   6  * Copyright (c) 2022, Intel Corporation.
   7  * All Rights Reserved.
   8  *
   9  */
  10
  11 #include "core.h"
  12
  13 /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
  14 const struct pmc_bit_map cnp_pfear_map[] = {
  15         {"PMC",                 BIT(0)},
  16         {"OPI-DMI",             BIT(1)},
  17         {"SPI/eSPI",            BIT(2)},
  18         {"XHCI",                BIT(3)},
  19         {"SPA",                 BIT(4)},
  20         {"SPB",                 BIT(5)},
  21         {"SPC",                 BIT(6)},
  22         {"GBE",                 BIT(7)},
  23
  24         {"SATA",                BIT(0)},
  25         {"HDA_PGD0",            BIT(1)},
  26         {"HDA_PGD1",            BIT(2)},
  27         {"HDA_PGD2",            BIT(3)},
  28         {"HDA_PGD3",            BIT(4)},
  29         {"SPD",                 BIT(5)},
  30         {"LPSS",                BIT(6)},
  31         {"LPC",                 BIT(7)},
  32
  33         {"SMB",                 BIT(0)},
  34         {"ISH",                 BIT(1)},
  35         {"P2SB",                BIT(2)},
  36         {"NPK_VNN",             BIT(3)},
  37         {"SDX",                 BIT(4)},
  38         {"SPE",                 BIT(5)},
  39         {"Fuse",                BIT(6)},
  40         {"SBR8",                BIT(7)},
  41
  42         {"CSME_FSC",            BIT(0)},
  43         {"USB3_OTG",            BIT(1)},
  44         {"EXI",                 BIT(2)},
  45         {"CSE",                 BIT(3)},
  46         {"CSME_KVM",            BIT(4)},
  47         {"CSME_PMT",            BIT(5)},
  48         {"CSME_CLINK",          BIT(6)},
  49         {"CSME_PTIO",           BIT(7)},
  50
  51         {"CSME_USBR",           BIT(0)},
  52         {"CSME_SUSRAM",         BIT(1)},
  53         {"CSME_SMT1",           BIT(2)},
  54         {"CSME_SMT4",           BIT(3)},
  55         {"CSME_SMS2",           BIT(4)},
  56         {"CSME_SMS1",           BIT(5)},
  57         {"CSME_RTC",            BIT(6)},
  58         {"CSME_PSF",            BIT(7)},
  59
  60         {"SBR0",                BIT(0)},
  61         {"SBR1",                BIT(1)},
  62         {"SBR2",                BIT(2)},
  63         {"SBR3",                BIT(3)},
  64         {"SBR4",                BIT(4)},
  65         {"SBR5",                BIT(5)},
  66         {"CSME_PECI",           BIT(6)},
  67         {"PSF1",                BIT(7)},
  68
  69         {"PSF2",                BIT(0)},
  70         {"PSF3",                BIT(1)},
  71         {"PSF4",                BIT(2)},
  72         {"CNVI",                BIT(3)},
  73         {"UFS0",                BIT(4)},
  74         {"EMMC",                BIT(5)},
  75         {"SPF",                 BIT(6)},
  76         {"SBR6",                BIT(7)},
  77
  78         {"SBR7",                BIT(0)},
  79         {"NPK_AON",             BIT(1)},
  80         {"HDA_PGD4",            BIT(2)},
  81         {"HDA_PGD5",            BIT(3)},
  82         {"HDA_PGD6",            BIT(4)},
  83         {"PSF6",                BIT(5)},
  84         {"PSF7",                BIT(6)},
  85         {"PSF8",                BIT(7)},
  86         {}
  87 };
  88
  89 const struct pmc_bit_map *ext_cnp_pfear_map[] = {
  90         /*
  91          * Check intel_pmc_core_ids[] users of cnp_reg_map for
  92          * a list of core SoCs using this.
  93          */
  94         cnp_pfear_map,
  95         NULL
  96 };
  97
  98 const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
  99         {"AUDIO_D3",            BIT(0)},
 100         {"OTG_D3",              BIT(1)},
 101         {"XHCI_D3",             BIT(2)},
 102         {"LPIO_D3",             BIT(3)},
 103         {"SDX_D3",              BIT(4)},
 104         {"SATA_D3",             BIT(5)},
 105         {"UFS0_D3",             BIT(6)},
 106         {"UFS1_D3",             BIT(7)},
 107         {"EMMC_D3",             BIT(8)},
 108         {}
 109 };
 110
 111 const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
 112         {"SDIO_PLL_OFF",        BIT(0)},
 113         {"USB2_PLL_OFF",        BIT(1)},
 114         {"AUDIO_PLL_OFF",       BIT(2)},
 115         {"OC_PLL_OFF",          BIT(3)},
 116         {"MAIN_PLL_OFF",        BIT(4)},
 117         {"XOSC_OFF",            BIT(5)},
 118         {"LPC_CLKS_GATED",      BIT(6)},
 119         {"PCIE_CLKREQS_IDLE",   BIT(7)},
 120         {"AUDIO_ROSC_OFF",      BIT(8)},
 121         {"HPET_XOSC_CLK_REQ",   BIT(9)},
 122         {"PMC_ROSC_SLOW_CLK",   BIT(10)},
 123         {"AON2_ROSC_GATED",     BIT(11)},
 124         {"CLKACKS_DEASSERTED",  BIT(12)},
 125         {}
 126 };
 127
 128 const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
 129         {"MPHY_CORE_GATED",     BIT(0)},
 130         {"CSME_GATED",          BIT(1)},
 131         {"USB2_SUS_GATED",      BIT(2)},
 132         {"DYN_FLEX_IO_IDLE",    BIT(3)},
 133         {"GBE_NO_LINK",         BIT(4)},
 134         {"THERM_SEN_DISABLED",  BIT(5)},
 135         {"PCIE_LOW_POWER",      BIT(6)},
 136         {"ISH_VNNAON_REQ_ACT",  BIT(7)},
 137         {"ISH_VNN_REQ_ACT",     BIT(8)},
 138         {"CNV_VNNAON_REQ_ACT",  BIT(9)},
 139         {"CNV_VNN_REQ_ACT",     BIT(10)},
 140         {"NPK_VNNON_REQ_ACT",   BIT(11)},
 141         {"PMSYNC_STATE_IDLE",   BIT(12)},
 142         {"ALST_GT_THRES",       BIT(13)},
 143         {"PMC_ARC_PG_READY",    BIT(14)},
 144         {}
 145 };
 146
 147 const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
 148         cnp_slps0_dbg0_map,
 149         cnp_slps0_dbg1_map,
 150         cnp_slps0_dbg2_map,
 151         NULL
 152 };
 153
 154 const struct pmc_bit_map cnp_ltr_show_map[] = {
 155         {"SOUTHPORT_A",         CNP_PMC_LTR_SPA},
 156         {"SOUTHPORT_B",         CNP_PMC_LTR_SPB},
 157         {"SATA",                CNP_PMC_LTR_SATA},
 158         {"GIGABIT_ETHERNET",    CNP_PMC_LTR_GBE},
 159         {"XHCI",                CNP_PMC_LTR_XHCI},
 160         {"Reserved",            CNP_PMC_LTR_RESERVED},
 161         {"ME",                  CNP_PMC_LTR_ME},
 162         /* EVA is Enterprise Value Add, doesn't really exist on PCH */
 163         {"EVA",                 CNP_PMC_LTR_EVA},
 164         {"SOUTHPORT_C",         CNP_PMC_LTR_SPC},
 165         {"HD_AUDIO",            CNP_PMC_LTR_AZ},
 166         {"CNV",                 CNP_PMC_LTR_CNV},
 167         {"LPSS",                CNP_PMC_LTR_LPSS},
 168         {"SOUTHPORT_D",         CNP_PMC_LTR_SPD},
 169         {"SOUTHPORT_E",         CNP_PMC_LTR_SPE},
 170         {"CAMERA",              CNP_PMC_LTR_CAM},
 171         {"ESPI",                CNP_PMC_LTR_ESPI},
 172         {"SCC",                 CNP_PMC_LTR_SCC},
 173         {"ISH",                 CNP_PMC_LTR_ISH},
 174         {"UFSX2",               CNP_PMC_LTR_UFSX2},
 175         {"EMMC",                CNP_PMC_LTR_EMMC},
 176         /*
 177          * Check intel_pmc_core_ids[] users of cnp_reg_map for
 178          * a list of core SoCs using this.
 179          */
 180         {"WIGIG",               ICL_PMC_LTR_WIGIG},
 181         {"THC0",                TGL_PMC_LTR_THC0},
 182         {"THC1",                TGL_PMC_LTR_THC1},
 183         /* Below two cannot be used for LTR_IGNORE */
 184         {"CURRENT_PLATFORM",    CNP_PMC_LTR_CUR_PLT},
 185         {"AGGREGATED_SYSTEM",   CNP_PMC_LTR_CUR_ASLT},
 186         {}
 187 };
 188
 189 const struct pmc_reg_map cnp_reg_map = {
 190         .pfear_sts = ext_cnp_pfear_map,
 191         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 192         .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
 193         .slps0_dbg_maps = cnp_slps0_dbg_maps,
 194         .ltr_show_sts = cnp_ltr_show_map,
 195         .msr_sts = msr_map,
 196         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 197         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 198         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 199         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 200         .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
 201         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 202         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 203         .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
 204         .etr3_offset = ETR3_OFFSET,
 205 };
 206
 207 int cnp_core_init(struct pmc_dev *pmcdev)
 208 {
 209         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 210         int ret;
 211
 212         pmc->map = &cnp_reg_map;
 213         ret = get_primary_reg_base(pmc);
 214         if (ret)
 215                 return ret;
 216
 217         /* Due to a hardware limitation, the GBE LTR blocks PC10
 218          * when a cable is attached. Tell the PMC to ignore it.
 219          */
 220         dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n");
 221         pmc_core_send_ltr_ignore(pmcdev, 3);
 222
 223         return 0;
 224 }