Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[platform/kernel/linux-rpi.git] / drivers / platform / x86 / amd-pmc.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * AMD SoC Power Management Controller Driver
4  *
5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9  */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/acpi.h>
14 #include <linux/bitfield.h>
15 #include <linux/bits.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/suspend.h>
24 #include <linux/seq_file.h>
25 #include <linux/uaccess.h>
26
27 /* SMU communication registers */
28 #define AMD_PMC_REGISTER_MESSAGE        0x538
29 #define AMD_PMC_REGISTER_RESPONSE       0x980
30 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
31
32 /* Base address of SMU for mapping physical address to virtual address */
33 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
34 #define AMD_PMC_SMU_INDEX_DATA          0xBC
35 #define AMD_PMC_MAPPING_SIZE            0x01000
36 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
37 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
38 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
39 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
40 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
41
42 /* SMU Response Codes */
43 #define AMD_PMC_RESULT_OK                    0x01
44 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
45 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
46 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
47 #define AMD_PMC_RESULT_FAILED                0xFF
48
49 /* FCH SSC Registers */
50 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
51 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
52 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
53 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
54 #define FCH_SSC_MAPPING_SIZE            0x800
55 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
56 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
57
58 /* SMU Message Definations */
59 #define SMU_MSG_GETSMUVERSION           0x02
60 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
61 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
62 #define SMU_MSG_LOG_START               0x06
63 #define SMU_MSG_LOG_RESET               0x07
64 #define SMU_MSG_LOG_DUMP_DATA           0x08
65 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
66 /* List of supported CPU ids */
67 #define AMD_CPU_ID_RV                   0x15D0
68 #define AMD_CPU_ID_RN                   0x1630
69 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
70 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
71 #define AMD_CPU_ID_YC                   0x14B5
72
73 #define PMC_MSG_DELAY_MIN_US            100
74 #define RESPONSE_REGISTER_LOOP_MAX      20000
75
76 #define SOC_SUBSYSTEM_IP_MAX    12
77 #define DELAY_MIN_US            2000
78 #define DELAY_MAX_US            3000
79 enum amd_pmc_def {
80         MSG_TEST = 0x01,
81         MSG_OS_HINT_PCO,
82         MSG_OS_HINT_RN,
83 };
84
85 struct amd_pmc_bit_map {
86         const char *name;
87         u32 bit_mask;
88 };
89
90 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
91         {"DISPLAY",     BIT(0)},
92         {"CPU",         BIT(1)},
93         {"GFX",         BIT(2)},
94         {"VDD",         BIT(3)},
95         {"ACP",         BIT(4)},
96         {"VCN",         BIT(5)},
97         {"ISP",         BIT(6)},
98         {"NBIO",        BIT(7)},
99         {"DF",          BIT(8)},
100         {"USB0",        BIT(9)},
101         {"USB1",        BIT(10)},
102         {"LAPIC",       BIT(11)},
103         {}
104 };
105
106 struct amd_pmc_dev {
107         void __iomem *regbase;
108         void __iomem *smu_virt_addr;
109         void __iomem *fch_virt_addr;
110         u32 base_addr;
111         u32 cpu_id;
112         u32 active_ips;
113         struct device *dev;
114         struct mutex lock; /* generic mutex lock */
115 #if IS_ENABLED(CONFIG_DEBUG_FS)
116         struct dentry *dbgfs_dir;
117 #endif /* CONFIG_DEBUG_FS */
118 };
119
120 static struct amd_pmc_dev pmc;
121 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret);
122
123 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
124 {
125         return ioread32(dev->regbase + reg_offset);
126 }
127
128 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
129 {
130         iowrite32(val, dev->regbase + reg_offset);
131 }
132
133 struct smu_metrics {
134         u32 table_version;
135         u32 hint_count;
136         u32 s0i3_cyclecount;
137         u32 timein_s0i2;
138         u64 timeentering_s0i3_lastcapture;
139         u64 timeentering_s0i3_totaltime;
140         u64 timeto_resume_to_os_lastcapture;
141         u64 timeto_resume_to_os_totaltime;
142         u64 timein_s0i3_lastcapture;
143         u64 timein_s0i3_totaltime;
144         u64 timein_swdrips_lastcapture;
145         u64 timein_swdrips_totaltime;
146         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
147         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
148 } __packed;
149
150 #ifdef CONFIG_DEBUG_FS
151 static int smu_fw_info_show(struct seq_file *s, void *unused)
152 {
153         struct amd_pmc_dev *dev = s->private;
154         struct smu_metrics table;
155         int idx;
156
157         if (dev->cpu_id == AMD_CPU_ID_PCO)
158                 return -EINVAL;
159
160         memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));
161
162         seq_puts(s, "\n=== SMU Statistics ===\n");
163         seq_printf(s, "Table Version: %d\n", table.table_version);
164         seq_printf(s, "Hint Count: %d\n", table.hint_count);
165         seq_printf(s, "S0i3 Cycle Count: %d\n", table.s0i3_cyclecount);
166         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
167         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
168
169         seq_puts(s, "\n=== Active time (in us) ===\n");
170         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
171                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
172                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
173                                    table.timecondition_notmet_lastcapture[idx]);
174         }
175
176         return 0;
177 }
178 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
179
180 static int s0ix_stats_show(struct seq_file *s, void *unused)
181 {
182         struct amd_pmc_dev *dev = s->private;
183         u64 entry_time, exit_time, residency;
184
185         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
186         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
187
188         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
189         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
190
191         /* It's in 48MHz. We need to convert it */
192         residency = exit_time - entry_time;
193         do_div(residency, 48);
194
195         seq_puts(s, "=== S0ix statistics ===\n");
196         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
197         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
198         seq_printf(s, "Residency Time: %lld\n", residency);
199
200         return 0;
201 }
202 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
203
204 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
205 {
206         debugfs_remove_recursive(dev->dbgfs_dir);
207 }
208
209 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
210 {
211         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
212         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
213                             &smu_fw_info_fops);
214         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
215                             &s0ix_stats_fops);
216 }
217 #else
218 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
219 {
220 }
221
222 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
223 {
224 }
225 #endif /* CONFIG_DEBUG_FS */
226
227 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
228 {
229         u32 phys_addr_low, phys_addr_hi;
230         u64 smu_phys_addr;
231
232         if (dev->cpu_id == AMD_CPU_ID_PCO)
233                 return -EINVAL;
234
235         /* Get Active devices list from SMU */
236         amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
237
238         /* Get dram address */
239         amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
240         amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
241         smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
242
243         dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
244         if (!dev->smu_virt_addr)
245                 return -ENOMEM;
246
247         /* Start the logging */
248         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
249
250         return 0;
251 }
252
253 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
254 {
255         u32 value;
256
257         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE);
258         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
259
260         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
261         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
262
263         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE);
264         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
265 }
266
267 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret)
268 {
269         int rc;
270         u32 val;
271
272         mutex_lock(&dev->lock);
273         /* Wait until we get a valid response */
274         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
275                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
276                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
277         if (rc) {
278                 dev_err(dev->dev, "failed to talk to SMU\n");
279                 goto out_unlock;
280         }
281
282         /* Write zero to response register */
283         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0);
284
285         /* Write argument into response register */
286         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);
287
288         /* Write message ID to message ID register */
289         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
290
291         /* Wait until we get a valid response */
292         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
293                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
294                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
295         if (rc) {
296                 dev_err(dev->dev, "SMU response timed out\n");
297                 goto out_unlock;
298         }
299
300         switch (val) {
301         case AMD_PMC_RESULT_OK:
302                 if (ret) {
303                         /* PMFW may take longer time to return back the data */
304                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
305                         *data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
306                 }
307                 break;
308         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
309                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
310                 rc = -EBUSY;
311                 goto out_unlock;
312         case AMD_PMC_RESULT_CMD_UNKNOWN:
313                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
314                 rc = -EINVAL;
315                 goto out_unlock;
316         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
317         case AMD_PMC_RESULT_FAILED:
318         default:
319                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
320                 rc = -EIO;
321                 goto out_unlock;
322         }
323
324 out_unlock:
325         mutex_unlock(&dev->lock);
326         amd_pmc_dump_registers(dev);
327         return rc;
328 }
329
330 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
331 {
332         switch (dev->cpu_id) {
333         case AMD_CPU_ID_PCO:
334                 return MSG_OS_HINT_PCO;
335         case AMD_CPU_ID_RN:
336         case AMD_CPU_ID_YC:
337                 return MSG_OS_HINT_RN;
338         }
339         return -EINVAL;
340 }
341
342 static int __maybe_unused amd_pmc_suspend(struct device *dev)
343 {
344         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
345         int rc;
346         u8 msg;
347
348         /* Reset and Start SMU logging - to monitor the s0i3 stats */
349         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
350         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
351
352         msg = amd_pmc_get_os_hint(pdev);
353         rc = amd_pmc_send_cmd(pdev, 1, NULL, msg, 0);
354         if (rc)
355                 dev_err(pdev->dev, "suspend failed\n");
356
357         return rc;
358 }
359
360 static int __maybe_unused amd_pmc_resume(struct device *dev)
361 {
362         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
363         int rc;
364         u8 msg;
365
366         /* Let SMU know that we are looking for stats */
367         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
368
369         msg = amd_pmc_get_os_hint(pdev);
370         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
371         if (rc)
372                 dev_err(pdev->dev, "resume failed\n");
373
374         return 0;
375 }
376
377 static const struct dev_pm_ops amd_pmc_pm_ops = {
378         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(amd_pmc_suspend, amd_pmc_resume)
379 };
380
381 static const struct pci_device_id pmc_pci_ids[] = {
382         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
383         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
384         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
385         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
386         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
387         { }
388 };
389
390 static int amd_pmc_probe(struct platform_device *pdev)
391 {
392         struct amd_pmc_dev *dev = &pmc;
393         struct pci_dev *rdev;
394         u32 base_addr_lo, base_addr_hi;
395         u64 base_addr, fch_phys_addr;
396         int err;
397         u32 val;
398
399         dev->dev = &pdev->dev;
400
401         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
402         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
403                 pci_dev_put(rdev);
404                 return -ENODEV;
405         }
406
407         dev->cpu_id = rdev->device;
408         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
409         if (err) {
410                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
411                 pci_dev_put(rdev);
412                 return pcibios_err_to_errno(err);
413         }
414
415         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
416         if (err) {
417                 pci_dev_put(rdev);
418                 return pcibios_err_to_errno(err);
419         }
420
421         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
422
423         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
424         if (err) {
425                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
426                 pci_dev_put(rdev);
427                 return pcibios_err_to_errno(err);
428         }
429
430         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
431         if (err) {
432                 pci_dev_put(rdev);
433                 return pcibios_err_to_errno(err);
434         }
435
436         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
437         pci_dev_put(rdev);
438         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
439
440         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
441                                     AMD_PMC_MAPPING_SIZE);
442         if (!dev->regbase)
443                 return -ENOMEM;
444
445         mutex_init(&dev->lock);
446
447         /* Use FCH registers to get the S0ix stats */
448         base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
449         base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
450         fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
451         dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
452         if (!dev->fch_virt_addr)
453                 return -ENOMEM;
454
455         /* Use SMU to get the s0i3 debug stats */
456         err = amd_pmc_setup_smu_logging(dev);
457         if (err)
458                 dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
459
460         platform_set_drvdata(pdev, dev);
461         amd_pmc_dbgfs_register(dev);
462         return 0;
463 }
464
465 static int amd_pmc_remove(struct platform_device *pdev)
466 {
467         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
468
469         amd_pmc_dbgfs_unregister(dev);
470         mutex_destroy(&dev->lock);
471         return 0;
472 }
473
474 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
475         {"AMDI0005", 0},
476         {"AMDI0006", 0},
477         {"AMDI0007", 0},
478         {"AMD0004", 0},
479         {"AMD0005", 0},
480         { }
481 };
482 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
483
484 static struct platform_driver amd_pmc_driver = {
485         .driver = {
486                 .name = "amd_pmc",
487                 .acpi_match_table = amd_pmc_acpi_ids,
488                 .pm = &amd_pmc_pm_ops,
489         },
490         .probe = amd_pmc_probe,
491         .remove = amd_pmc_remove,
492 };
493 module_platform_driver(amd_pmc_driver);
494
495 MODULE_LICENSE("GPL v2");
496 MODULE_DESCRIPTION("AMD PMC Driver");