drivers/platform/x86/amd-pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/limits.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/rtc.h>
  25 #include <linux/suspend.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/uaccess.h>
  28
  29 /* SMU communication registers */
  30 #define AMD_PMC_REGISTER_MESSAGE        0x538
  31 #define AMD_PMC_REGISTER_RESPONSE       0x980
  32 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  33
  34 /* PMC Scratch Registers */
  35 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  36 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  37
  38 /* STB Registers */
  39 #define AMD_PMC_STB_INDEX_ADDRESS       0xF8
  40 #define AMD_PMC_STB_INDEX_DATA          0xFC
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_PREDEF              0xC6000001
  43
  44 /* STB S2D(Spill to DRAM) has different message port offset */
  45 #define STB_SPILL_TO_DRAM               0xBE
  46 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  47 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  48 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  49
  50 /* STB Spill to DRAM Parameters */
  51 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  52 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  53
  54 /* Base address of SMU for mapping physical address to virtual address */
  55 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  56 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  57 #define AMD_PMC_MAPPING_SIZE            0x01000
  58 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  59 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  60 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  61 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  62 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  63
  64 /* SMU Response Codes */
  65 #define AMD_PMC_RESULT_OK                    0x01
  66 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  67 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  68 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  69 #define AMD_PMC_RESULT_FAILED                0xFF
  70
  71 /* FCH SSC Registers */
  72 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  73 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  74 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  75 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  76 #define FCH_SSC_MAPPING_SIZE            0x800
  77 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  78 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  79
  80 /* SMU Message Definations */
  81 #define SMU_MSG_GETSMUVERSION           0x02
  82 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  83 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  84 #define SMU_MSG_LOG_START               0x06
  85 #define SMU_MSG_LOG_RESET               0x07
  86 #define SMU_MSG_LOG_DUMP_DATA           0x08
  87 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  88 /* List of supported CPU ids */
  89 #define AMD_CPU_ID_RV                   0x15D0
  90 #define AMD_CPU_ID_RN                   0x1630
  91 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  92 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  93 #define AMD_CPU_ID_YC                   0x14B5
  94
  95 #define PMC_MSG_DELAY_MIN_US            50
  96 #define RESPONSE_REGISTER_LOOP_MAX      20000
  97
  98 #define SOC_SUBSYSTEM_IP_MAX    12
  99 #define DELAY_MIN_US            2000
 100 #define DELAY_MAX_US            3000
 101 #define FIFO_SIZE               4096
 102 enum amd_pmc_def {
 103         MSG_TEST = 0x01,
 104         MSG_OS_HINT_PCO,
 105         MSG_OS_HINT_RN,
 106 };
 107
 108 enum s2d_arg {
 109         S2D_TELEMETRY_SIZE = 0x01,
 110         S2D_PHYS_ADDR_LOW,
 111         S2D_PHYS_ADDR_HIGH,
 112 };
 113
 114 struct amd_pmc_bit_map {
 115         const char *name;
 116         u32 bit_mask;
 117 };
 118
 119 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 120         {"DISPLAY",     BIT(0)},
 121         {"CPU",         BIT(1)},
 122         {"GFX",         BIT(2)},
 123         {"VDD",         BIT(3)},
 124         {"ACP",         BIT(4)},
 125         {"VCN",         BIT(5)},
 126         {"ISP",         BIT(6)},
 127         {"NBIO",        BIT(7)},
 128         {"DF",          BIT(8)},
 129         {"USB0",        BIT(9)},
 130         {"USB1",        BIT(10)},
 131         {"LAPIC",       BIT(11)},
 132         {}
 133 };
 134
 135 struct amd_pmc_dev {
 136         void __iomem *regbase;
 137         void __iomem *smu_virt_addr;
 138         void __iomem *stb_virt_addr;
 139         void __iomem *fch_virt_addr;
 140         bool msg_port;
 141         u32 base_addr;
 142         u32 cpu_id;
 143         u32 active_ips;
 144 /* SMU version information */
 145         u8 smu_program;
 146         u8 major;
 147         u8 minor;
 148         u8 rev;
 149         struct device *dev;
 150         struct pci_dev *rdev;
 151         struct mutex lock; /* generic mutex lock */
 152 #if IS_ENABLED(CONFIG_DEBUG_FS)
 153         struct dentry *dbgfs_dir;
 154 #endif /* CONFIG_DEBUG_FS */
 155 };
 156
 157 static bool enable_stb;
 158 module_param(enable_stb, bool, 0644);
 159 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 160
 161 static struct amd_pmc_dev pmc;
 162 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 163 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 164 #ifdef CONFIG_SUSPEND
 165 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 166 #endif
 167 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev);
 168
 169 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 170 {
 171         return ioread32(dev->regbase + reg_offset);
 172 }
 173
 174 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 175 {
 176         iowrite32(val, dev->regbase + reg_offset);
 177 }
 178
 179 struct smu_metrics {
 180         u32 table_version;
 181         u32 hint_count;
 182         u32 s0i3_last_entry_status;
 183         u32 timein_s0i2;
 184         u64 timeentering_s0i3_lastcapture;
 185         u64 timeentering_s0i3_totaltime;
 186         u64 timeto_resume_to_os_lastcapture;
 187         u64 timeto_resume_to_os_totaltime;
 188         u64 timein_s0i3_lastcapture;
 189         u64 timein_s0i3_totaltime;
 190         u64 timein_swdrips_lastcapture;
 191         u64 timein_swdrips_totaltime;
 192         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 193         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 194 } __packed;
 195
 196 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 197 {
 198         int rc;
 199         u32 val;
 200
 201         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 202         if (rc)
 203                 return rc;
 204
 205         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 206         dev->major = (val >> 16) & GENMASK(7, 0);
 207         dev->minor = (val >> 8) & GENMASK(7, 0);
 208         dev->rev = (val >> 0) & GENMASK(7, 0);
 209
 210         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 211                 dev->smu_program, dev->major, dev->minor, dev->rev);
 212
 213         return 0;
 214 }
 215
 216 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 217 {
 218         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 219         u32 size = FIFO_SIZE * sizeof(u32);
 220         u32 *buf;
 221         int rc;
 222
 223         buf = kzalloc(size, GFP_KERNEL);
 224         if (!buf)
 225                 return -ENOMEM;
 226
 227         rc = amd_pmc_read_stb(dev, buf);
 228         if (rc) {
 229                 kfree(buf);
 230                 return rc;
 231         }
 232
 233         filp->private_data = buf;
 234         return rc;
 235 }
 236
 237 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 238                                         loff_t *pos)
 239 {
 240         if (!filp->private_data)
 241                 return -EINVAL;
 242
 243         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 244                                        FIFO_SIZE * sizeof(u32));
 245 }
 246
 247 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 248 {
 249         kfree(filp->private_data);
 250         return 0;
 251 }
 252
 253 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 254         .owner = THIS_MODULE,
 255         .open = amd_pmc_stb_debugfs_open,
 256         .read = amd_pmc_stb_debugfs_read,
 257         .release = amd_pmc_stb_debugfs_release,
 258 };
 259
 260 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 261 {
 262         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 263         u32 *buf;
 264
 265         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 266         if (!buf)
 267                 return -ENOMEM;
 268
 269         memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
 270         filp->private_data = buf;
 271
 272         return 0;
 273 }
 274
 275 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 276                                            loff_t *pos)
 277 {
 278         if (!filp->private_data)
 279                 return -EINVAL;
 280
 281         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 282                                         S2D_TELEMETRY_BYTES_MAX);
 283 }
 284
 285 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 286 {
 287         kfree(filp->private_data);
 288         return 0;
 289 }
 290
 291 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 292         .owner = THIS_MODULE,
 293         .open = amd_pmc_stb_debugfs_open_v2,
 294         .read = amd_pmc_stb_debugfs_read_v2,
 295         .release = amd_pmc_stb_debugfs_release_v2,
 296 };
 297
 298 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 299                                  struct seq_file *s)
 300 {
 301         u32 val;
 302
 303         switch (pdev->cpu_id) {
 304         case AMD_CPU_ID_CZN:
 305                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 306                 break;
 307         case AMD_CPU_ID_YC:
 308                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 309                 break;
 310         default:
 311                 return -EINVAL;
 312         }
 313
 314         if (dev)
 315                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 316
 317         if (s)
 318                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 319
 320         return 0;
 321 }
 322
 323 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 324 {
 325         if (!pdev->smu_virt_addr) {
 326                 int ret = amd_pmc_setup_smu_logging(pdev);
 327
 328                 if (ret)
 329                         return ret;
 330         }
 331
 332         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 333                 return -ENODEV;
 334         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 335         return 0;
 336 }
 337
 338 #ifdef CONFIG_SUSPEND
 339 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 340 {
 341         struct smu_metrics table;
 342
 343         if (get_metrics_table(pdev, &table))
 344                 return;
 345
 346         if (!table.s0i3_last_entry_status)
 347                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 348         else
 349                 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
 350                          table.timein_s0i3_lastcapture);
 351 }
 352 #endif
 353
 354 #ifdef CONFIG_DEBUG_FS
 355 static int smu_fw_info_show(struct seq_file *s, void *unused)
 356 {
 357         struct amd_pmc_dev *dev = s->private;
 358         struct smu_metrics table;
 359         int idx;
 360
 361         if (get_metrics_table(dev, &table))
 362                 return -EINVAL;
 363
 364         seq_puts(s, "\n=== SMU Statistics ===\n");
 365         seq_printf(s, "Table Version: %d\n", table.table_version);
 366         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 367         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 368                    "Unknown/Fail");
 369         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 370         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 371         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 372                    table.timeto_resume_to_os_lastcapture);
 373
 374         seq_puts(s, "\n=== Active time (in us) ===\n");
 375         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 376                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 377                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 378                                    table.timecondition_notmet_lastcapture[idx]);
 379         }
 380
 381         return 0;
 382 }
 383 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 384
 385 static int s0ix_stats_show(struct seq_file *s, void *unused)
 386 {
 387         struct amd_pmc_dev *dev = s->private;
 388         u64 entry_time, exit_time, residency;
 389
 390         /* Use FCH registers to get the S0ix stats */
 391         if (!dev->fch_virt_addr) {
 392                 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 393                 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 394                 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 395
 396                 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 397                 if (!dev->fch_virt_addr)
 398                         return -ENOMEM;
 399         }
 400
 401         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 402         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 403
 404         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 405         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 406
 407         /* It's in 48MHz. We need to convert it */
 408         residency = exit_time - entry_time;
 409         do_div(residency, 48);
 410
 411         seq_puts(s, "=== S0ix statistics ===\n");
 412         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 413         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 414         seq_printf(s, "Residency Time: %lld\n", residency);
 415
 416         return 0;
 417 }
 418 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 419
 420 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 421 {
 422         struct amd_pmc_dev *dev = s->private;
 423         int rc;
 424
 425         if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
 426                 rc = amd_pmc_idlemask_read(dev, NULL, s);
 427                 if (rc)
 428                         return rc;
 429         } else {
 430                 seq_puts(s, "Unsupported SMU version for Idlemask\n");
 431         }
 432
 433         return 0;
 434 }
 435 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 436
 437 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 438 {
 439         debugfs_remove_recursive(dev->dbgfs_dir);
 440 }
 441
 442 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 443 {
 444         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 445         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 446                             &smu_fw_info_fops);
 447         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 448                             &s0ix_stats_fops);
 449         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 450                             &amd_pmc_idlemask_fops);
 451         /* Enable STB only when the module_param is set */
 452         if (enable_stb) {
 453                 if (dev->cpu_id == AMD_CPU_ID_YC)
 454                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 455                                             &amd_pmc_stb_debugfs_fops_v2);
 456                 else
 457                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 458                                             &amd_pmc_stb_debugfs_fops);
 459         }
 460 }
 461 #else
 462 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 463 {
 464 }
 465
 466 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 467 {
 468 }
 469 #endif /* CONFIG_DEBUG_FS */
 470
 471 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 472 {
 473         if (dev->cpu_id == AMD_CPU_ID_PCO) {
 474                 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
 475                 return -EINVAL;
 476         }
 477
 478         /* Get Active devices list from SMU */
 479         if (!dev->active_ips)
 480                 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 481
 482         /* Get dram address */
 483         if (!dev->smu_virt_addr) {
 484                 u32 phys_addr_low, phys_addr_hi;
 485                 u64 smu_phys_addr;
 486
 487                 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 488                 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 489                 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 490
 491                 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
 492                                                   sizeof(struct smu_metrics));
 493                 if (!dev->smu_virt_addr)
 494                         return -ENOMEM;
 495         }
 496
 497         /* Start the logging */
 498         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 499         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 500
 501         return 0;
 502 }
 503
 504 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 505 {
 506         u32 value, message, argument, response;
 507
 508         if (dev->msg_port) {
 509                 message = AMD_S2D_REGISTER_MESSAGE;
 510                 argument = AMD_S2D_REGISTER_ARGUMENT;
 511                 response = AMD_S2D_REGISTER_RESPONSE;
 512         } else {
 513                 message = AMD_PMC_REGISTER_MESSAGE;
 514                 argument = AMD_PMC_REGISTER_ARGUMENT;
 515                 response = AMD_PMC_REGISTER_RESPONSE;
 516         }
 517
 518         value = amd_pmc_reg_read(dev, response);
 519         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
 520
 521         value = amd_pmc_reg_read(dev, argument);
 522         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
 523
 524         value = amd_pmc_reg_read(dev, message);
 525         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
 526 }
 527
 528 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 529 {
 530         int rc;
 531         u32 val, message, argument, response;
 532
 533         mutex_lock(&dev->lock);
 534
 535         if (dev->msg_port) {
 536                 message = AMD_S2D_REGISTER_MESSAGE;
 537                 argument = AMD_S2D_REGISTER_ARGUMENT;
 538                 response = AMD_S2D_REGISTER_RESPONSE;
 539         } else {
 540                 message = AMD_PMC_REGISTER_MESSAGE;
 541                 argument = AMD_PMC_REGISTER_ARGUMENT;
 542                 response = AMD_PMC_REGISTER_RESPONSE;
 543         }
 544
 545         /* Wait until we get a valid response */
 546         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 547                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 548                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 549         if (rc) {
 550                 dev_err(dev->dev, "failed to talk to SMU\n");
 551                 goto out_unlock;
 552         }
 553
 554         /* Write zero to response register */
 555         amd_pmc_reg_write(dev, response, 0);
 556
 557         /* Write argument into response register */
 558         amd_pmc_reg_write(dev, argument, arg);
 559
 560         /* Write message ID to message ID register */
 561         amd_pmc_reg_write(dev, message, msg);
 562
 563         /* Wait until we get a valid response */
 564         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 565                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 566                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 567         if (rc) {
 568                 dev_err(dev->dev, "SMU response timed out\n");
 569                 goto out_unlock;
 570         }
 571
 572         switch (val) {
 573         case AMD_PMC_RESULT_OK:
 574                 if (ret) {
 575                         /* PMFW may take longer time to return back the data */
 576                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 577                         *data = amd_pmc_reg_read(dev, argument);
 578                 }
 579                 break;
 580         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 581                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 582                 rc = -EBUSY;
 583                 goto out_unlock;
 584         case AMD_PMC_RESULT_CMD_UNKNOWN:
 585                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 586                 rc = -EINVAL;
 587                 goto out_unlock;
 588         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 589         case AMD_PMC_RESULT_FAILED:
 590         default:
 591                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 592                 rc = -EIO;
 593                 goto out_unlock;
 594         }
 595
 596 out_unlock:
 597         mutex_unlock(&dev->lock);
 598         amd_pmc_dump_registers(dev);
 599         return rc;
 600 }
 601
 602 #ifdef CONFIG_SUSPEND
 603 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 604 {
 605         switch (dev->cpu_id) {
 606         case AMD_CPU_ID_PCO:
 607                 return MSG_OS_HINT_PCO;
 608         case AMD_CPU_ID_RN:
 609         case AMD_CPU_ID_YC:
 610                 return MSG_OS_HINT_RN;
 611         }
 612         return -EINVAL;
 613 }
 614
 615 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 616 {
 617         struct rtc_device *rtc_device;
 618         time64_t then, now, duration;
 619         struct rtc_wkalrm alarm;
 620         struct rtc_time tm;
 621         int rc;
 622
 623         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 624                 return 0;
 625
 626         rtc_device = rtc_class_open("rtc0");
 627         if (!rtc_device)
 628                 return 0;
 629         rc = rtc_read_alarm(rtc_device, &alarm);
 630         if (rc)
 631                 return rc;
 632         if (!alarm.enabled) {
 633                 dev_dbg(pdev->dev, "alarm not enabled\n");
 634                 return 0;
 635         }
 636         rc = rtc_read_time(rtc_device, &tm);
 637         if (rc)
 638                 return rc;
 639         then = rtc_tm_to_time64(&alarm.time);
 640         now = rtc_tm_to_time64(&tm);
 641         duration = then-now;
 642
 643         /* in the past */
 644         if (then < now)
 645                 return 0;
 646
 647         /* will be stored in upper 16 bits of s0i3 hint argument,
 648          * so timer wakeup from s0i3 is limited to ~18 hours or less
 649          */
 650         if (duration <= 4 || duration > U16_MAX)
 651                 return -EINVAL;
 652
 653         *arg |= (duration << 16);
 654         rc = rtc_alarm_irq_enable(rtc_device, 0);
 655         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 656
 657         return rc;
 658 }
 659
 660 static void amd_pmc_s2idle_prepare(void)
 661 {
 662         struct amd_pmc_dev *pdev = &pmc;
 663         int rc;
 664         u8 msg;
 665         u32 arg = 1;
 666
 667         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 668         amd_pmc_setup_smu_logging(pdev);
 669
 670         /* Activate CZN specific RTC functionality */
 671         if (pdev->cpu_id == AMD_CPU_ID_CZN) {
 672                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 673                 if (rc) {
 674                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 675                         return;
 676                 }
 677         }
 678
 679         /* Dump the IdleMask before we send hint to SMU */
 680         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 681         msg = amd_pmc_get_os_hint(pdev);
 682         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 683         if (rc) {
 684                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 685                 return;
 686         }
 687
 688         if (enable_stb) {
 689                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);
 690                 if (rc)
 691                         dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 692         }
 693 }
 694
 695 static void amd_pmc_s2idle_restore(void)
 696 {
 697         struct amd_pmc_dev *pdev = &pmc;
 698         int rc;
 699         u8 msg;
 700
 701         msg = amd_pmc_get_os_hint(pdev);
 702         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 703         if (rc)
 704                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 705
 706         /* Let SMU know that we are looking for stats */
 707         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 708
 709         /* Dump the IdleMask to see the blockers */
 710         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 711
 712         /* Write data incremented by 1 to distinguish in stb_read */
 713         if (enable_stb) {
 714                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);
 715                 if (rc)
 716                         dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 717         }
 718
 719         /* Notify on failed entry */
 720         amd_pmc_validate_deepest(pdev);
 721 }
 722
 723 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 724         .prepare = amd_pmc_s2idle_prepare,
 725         .restore = amd_pmc_s2idle_restore,
 726 };
 727 #endif
 728
 729 static const struct pci_device_id pmc_pci_ids[] = {
 730         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 731         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 732         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 733         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 734         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 735         { }
 736 };
 737
 738 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 739 {
 740         u32 phys_addr_low, phys_addr_hi;
 741         u64 stb_phys_addr;
 742         u32 size = 0;
 743
 744         /* Spill to DRAM feature uses separate SMU message port */
 745         dev->msg_port = 1;
 746
 747         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
 748         if (size != S2D_TELEMETRY_BYTES_MAX)
 749                 return -EIO;
 750
 751         /* Get STB DRAM address */
 752         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
 753         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
 754
 755         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 756
 757         /* Clear msg_port for other SMU operation */
 758         dev->msg_port = 0;
 759
 760         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
 761         if (!dev->stb_virt_addr)
 762                 return -ENOMEM;
 763
 764         return 0;
 765 }
 766
 767 #ifdef CONFIG_SUSPEND
 768 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 769 {
 770         int err;
 771
 772         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 773         if (err) {
 774                 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
 775                         AMD_PMC_STB_INDEX_ADDRESS);
 776                 return pcibios_err_to_errno(err);
 777         }
 778
 779         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
 780         if (err) {
 781                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
 782                         AMD_PMC_STB_INDEX_DATA);
 783                 return pcibios_err_to_errno(err);
 784         }
 785
 786         return 0;
 787 }
 788 #endif
 789
 790 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 791 {
 792         int i, err;
 793
 794         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 795         if (err) {
 796                 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
 797                         AMD_PMC_STB_INDEX_ADDRESS);
 798                 return pcibios_err_to_errno(err);
 799         }
 800
 801         for (i = 0; i < FIFO_SIZE; i++) {
 802                 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
 803                 if (err) {
 804                         dev_err(dev->dev, "error reading data from stb: 0x%X\n",
 805                                 AMD_PMC_STB_INDEX_DATA);
 806                         return pcibios_err_to_errno(err);
 807                 }
 808         }
 809
 810         return 0;
 811 }
 812
 813 static int amd_pmc_probe(struct platform_device *pdev)
 814 {
 815         struct amd_pmc_dev *dev = &pmc;
 816         struct pci_dev *rdev;
 817         u32 base_addr_lo, base_addr_hi;
 818         u64 base_addr;
 819         int err;
 820         u32 val;
 821
 822         dev->dev = &pdev->dev;
 823
 824         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 825         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 826                 err = -ENODEV;
 827                 goto err_pci_dev_put;
 828         }
 829
 830         dev->cpu_id = rdev->device;
 831         dev->rdev = rdev;
 832         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 833         if (err) {
 834                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 835                 err = pcibios_err_to_errno(err);
 836                 goto err_pci_dev_put;
 837         }
 838
 839         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 840         if (err) {
 841                 err = pcibios_err_to_errno(err);
 842                 goto err_pci_dev_put;
 843         }
 844
 845         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 846
 847         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 848         if (err) {
 849                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 850                 err = pcibios_err_to_errno(err);
 851                 goto err_pci_dev_put;
 852         }
 853
 854         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 855         if (err) {
 856                 err = pcibios_err_to_errno(err);
 857                 goto err_pci_dev_put;
 858         }
 859
 860         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 861         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 862
 863         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 864                                     AMD_PMC_MAPPING_SIZE);
 865         if (!dev->regbase) {
 866                 err = -ENOMEM;
 867                 goto err_pci_dev_put;
 868         }
 869
 870         mutex_init(&dev->lock);
 871
 872         if (enable_stb && dev->cpu_id == AMD_CPU_ID_YC) {
 873                 err = amd_pmc_s2d_init(dev);
 874                 if (err)
 875                         return err;
 876         }
 877
 878         amd_pmc_get_smu_version(dev);
 879         platform_set_drvdata(pdev, dev);
 880 #ifdef CONFIG_SUSPEND
 881         err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
 882         if (err)
 883                 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
 884 #endif
 885
 886         amd_pmc_dbgfs_register(dev);
 887         return 0;
 888
 889 err_pci_dev_put:
 890         pci_dev_put(rdev);
 891         return err;
 892 }
 893
 894 static int amd_pmc_remove(struct platform_device *pdev)
 895 {
 896         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
 897
 898 #ifdef CONFIG_SUSPEND
 899         acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
 900 #endif
 901         amd_pmc_dbgfs_unregister(dev);
 902         pci_dev_put(dev->rdev);
 903         mutex_destroy(&dev->lock);
 904         return 0;
 905 }
 906
 907 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 908         {"AMDI0005", 0},
 909         {"AMDI0006", 0},
 910         {"AMDI0007", 0},
 911         {"AMD0004", 0},
 912         {"AMD0005", 0},
 913         { }
 914 };
 915 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
 916
 917 static struct platform_driver amd_pmc_driver = {
 918         .driver = {
 919                 .name = "amd_pmc",
 920                 .acpi_match_table = amd_pmc_acpi_ids,
 921         },
 922         .probe = amd_pmc_probe,
 923         .remove = amd_pmc_remove,
 924 };
 925 module_platform_driver(amd_pmc_driver);
 926
 927 MODULE_LICENSE("GPL v2");
 928 MODULE_DESCRIPTION("AMD PMC Driver");