drivers/platform/x86/amd-pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/limits.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/rtc.h>
  25 #include <linux/suspend.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/uaccess.h>
  28
  29 /* SMU communication registers */
  30 #define AMD_PMC_REGISTER_MESSAGE        0x538
  31 #define AMD_PMC_REGISTER_RESPONSE       0x980
  32 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  33
  34 /* PMC Scratch Registers */
  35 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  36 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  37
  38 /* STB Registers */
  39 #define AMD_PMC_STB_INDEX_ADDRESS       0xF8
  40 #define AMD_PMC_STB_INDEX_DATA          0xFC
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_PREDEF              0xC6000001
  43
  44 /* Base address of SMU for mapping physical address to virtual address */
  45 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  46 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  47 #define AMD_PMC_MAPPING_SIZE            0x01000
  48 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  49 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  50 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  51 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  52 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  53
  54 /* SMU Response Codes */
  55 #define AMD_PMC_RESULT_OK                    0x01
  56 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  57 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  58 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  59 #define AMD_PMC_RESULT_FAILED                0xFF
  60
  61 /* FCH SSC Registers */
  62 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  63 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  64 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  65 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  66 #define FCH_SSC_MAPPING_SIZE            0x800
  67 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  68 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  69
  70 /* SMU Message Definations */
  71 #define SMU_MSG_GETSMUVERSION           0x02
  72 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  73 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  74 #define SMU_MSG_LOG_START               0x06
  75 #define SMU_MSG_LOG_RESET               0x07
  76 #define SMU_MSG_LOG_DUMP_DATA           0x08
  77 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  78 /* List of supported CPU ids */
  79 #define AMD_CPU_ID_RV                   0x15D0
  80 #define AMD_CPU_ID_RN                   0x1630
  81 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  82 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  83 #define AMD_CPU_ID_YC                   0x14B5
  84
  85 #define PMC_MSG_DELAY_MIN_US            50
  86 #define RESPONSE_REGISTER_LOOP_MAX      20000
  87
  88 #define SOC_SUBSYSTEM_IP_MAX    12
  89 #define DELAY_MIN_US            2000
  90 #define DELAY_MAX_US            3000
  91 #define FIFO_SIZE               4096
  92 enum amd_pmc_def {
  93         MSG_TEST = 0x01,
  94         MSG_OS_HINT_PCO,
  95         MSG_OS_HINT_RN,
  96 };
  97
  98 struct amd_pmc_bit_map {
  99         const char *name;
 100         u32 bit_mask;
 101 };
 102
 103 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 104         {"DISPLAY",     BIT(0)},
 105         {"CPU",         BIT(1)},
 106         {"GFX",         BIT(2)},
 107         {"VDD",         BIT(3)},
 108         {"ACP",         BIT(4)},
 109         {"VCN",         BIT(5)},
 110         {"ISP",         BIT(6)},
 111         {"NBIO",        BIT(7)},
 112         {"DF",          BIT(8)},
 113         {"USB0",        BIT(9)},
 114         {"USB1",        BIT(10)},
 115         {"LAPIC",       BIT(11)},
 116         {}
 117 };
 118
 119 struct amd_pmc_dev {
 120         void __iomem *regbase;
 121         void __iomem *smu_virt_addr;
 122         void __iomem *fch_virt_addr;
 123         u32 base_addr;
 124         u32 cpu_id;
 125         u32 active_ips;
 126 /* SMU version information */
 127         u8 smu_program;
 128         u8 major;
 129         u8 minor;
 130         u8 rev;
 131         struct device *dev;
 132         struct pci_dev *rdev;
 133         struct mutex lock; /* generic mutex lock */
 134 #if IS_ENABLED(CONFIG_DEBUG_FS)
 135         struct dentry *dbgfs_dir;
 136 #endif /* CONFIG_DEBUG_FS */
 137 };
 138
 139 static bool enable_stb;
 140 module_param(enable_stb, bool, 0644);
 141 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 142
 143 static struct amd_pmc_dev pmc;
 144 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 145 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 146 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 147
 148 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 149 {
 150         return ioread32(dev->regbase + reg_offset);
 151 }
 152
 153 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 154 {
 155         iowrite32(val, dev->regbase + reg_offset);
 156 }
 157
 158 struct smu_metrics {
 159         u32 table_version;
 160         u32 hint_count;
 161         u32 s0i3_last_entry_status;
 162         u32 timein_s0i2;
 163         u64 timeentering_s0i3_lastcapture;
 164         u64 timeentering_s0i3_totaltime;
 165         u64 timeto_resume_to_os_lastcapture;
 166         u64 timeto_resume_to_os_totaltime;
 167         u64 timein_s0i3_lastcapture;
 168         u64 timein_s0i3_totaltime;
 169         u64 timein_swdrips_lastcapture;
 170         u64 timein_swdrips_totaltime;
 171         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 172         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 173 } __packed;
 174
 175 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 176 {
 177         int rc;
 178         u32 val;
 179
 180         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 181         if (rc)
 182                 return rc;
 183
 184         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 185         dev->major = (val >> 16) & GENMASK(7, 0);
 186         dev->minor = (val >> 8) & GENMASK(7, 0);
 187         dev->rev = (val >> 0) & GENMASK(7, 0);
 188
 189         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 190                 dev->smu_program, dev->major, dev->minor, dev->rev);
 191
 192         return 0;
 193 }
 194
 195 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 196 {
 197         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 198         u32 size = FIFO_SIZE * sizeof(u32);
 199         u32 *buf;
 200         int rc;
 201
 202         buf = kzalloc(size, GFP_KERNEL);
 203         if (!buf)
 204                 return -ENOMEM;
 205
 206         rc = amd_pmc_read_stb(dev, buf);
 207         if (rc) {
 208                 kfree(buf);
 209                 return rc;
 210         }
 211
 212         filp->private_data = buf;
 213         return rc;
 214 }
 215
 216 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 217                                         loff_t *pos)
 218 {
 219         if (!filp->private_data)
 220                 return -EINVAL;
 221
 222         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 223                                        FIFO_SIZE * sizeof(u32));
 224 }
 225
 226 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 227 {
 228         kfree(filp->private_data);
 229         return 0;
 230 }
 231
 232 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 233         .owner = THIS_MODULE,
 234         .open = amd_pmc_stb_debugfs_open,
 235         .read = amd_pmc_stb_debugfs_read,
 236         .release = amd_pmc_stb_debugfs_release,
 237 };
 238
 239 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 240                                  struct seq_file *s)
 241 {
 242         u32 val;
 243
 244         switch (pdev->cpu_id) {
 245         case AMD_CPU_ID_CZN:
 246                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 247                 break;
 248         case AMD_CPU_ID_YC:
 249                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 250                 break;
 251         default:
 252                 return -EINVAL;
 253         }
 254
 255         if (dev)
 256                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 257
 258         if (s)
 259                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 260
 261         return 0;
 262 }
 263
 264 #ifdef CONFIG_DEBUG_FS
 265 static int smu_fw_info_show(struct seq_file *s, void *unused)
 266 {
 267         struct amd_pmc_dev *dev = s->private;
 268         struct smu_metrics table;
 269         int idx;
 270
 271         if (dev->cpu_id == AMD_CPU_ID_PCO)
 272                 return -EINVAL;
 273
 274         memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));
 275
 276         seq_puts(s, "\n=== SMU Statistics ===\n");
 277         seq_printf(s, "Table Version: %d\n", table.table_version);
 278         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 279         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 280                    "Unknown/Fail");
 281         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 282         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 283         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 284                    table.timeto_resume_to_os_lastcapture);
 285
 286         seq_puts(s, "\n=== Active time (in us) ===\n");
 287         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 288                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 289                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 290                                    table.timecondition_notmet_lastcapture[idx]);
 291         }
 292
 293         return 0;
 294 }
 295 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 296
 297 static int s0ix_stats_show(struct seq_file *s, void *unused)
 298 {
 299         struct amd_pmc_dev *dev = s->private;
 300         u64 entry_time, exit_time, residency;
 301
 302         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 303         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 304
 305         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 306         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 307
 308         /* It's in 48MHz. We need to convert it */
 309         residency = exit_time - entry_time;
 310         do_div(residency, 48);
 311
 312         seq_puts(s, "=== S0ix statistics ===\n");
 313         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 314         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 315         seq_printf(s, "Residency Time: %lld\n", residency);
 316
 317         return 0;
 318 }
 319 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 320
 321 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 322 {
 323         struct amd_pmc_dev *dev = s->private;
 324         int rc;
 325
 326         if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
 327                 rc = amd_pmc_idlemask_read(dev, NULL, s);
 328                 if (rc)
 329                         return rc;
 330         } else {
 331                 seq_puts(s, "Unsupported SMU version for Idlemask\n");
 332         }
 333
 334         return 0;
 335 }
 336 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 337
 338 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 339 {
 340         debugfs_remove_recursive(dev->dbgfs_dir);
 341 }
 342
 343 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 344 {
 345         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 346         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 347                             &smu_fw_info_fops);
 348         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 349                             &s0ix_stats_fops);
 350         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 351                             &amd_pmc_idlemask_fops);
 352         /* Enable STB only when the module_param is set */
 353         if (enable_stb)
 354                 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 355                                     &amd_pmc_stb_debugfs_fops);
 356 }
 357 #else
 358 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 359 {
 360 }
 361
 362 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 363 {
 364 }
 365 #endif /* CONFIG_DEBUG_FS */
 366
 367 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 368 {
 369         u32 phys_addr_low, phys_addr_hi;
 370         u64 smu_phys_addr;
 371
 372         if (dev->cpu_id == AMD_CPU_ID_PCO)
 373                 return -EINVAL;
 374
 375         /* Get Active devices list from SMU */
 376         amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 377
 378         /* Get dram address */
 379         amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 380         amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 381         smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 382
 383         dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
 384         if (!dev->smu_virt_addr)
 385                 return -ENOMEM;
 386
 387         /* Start the logging */
 388         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 389
 390         return 0;
 391 }
 392
 393 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 394 {
 395         u32 value;
 396
 397         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE);
 398         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
 399
 400         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
 401         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
 402
 403         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE);
 404         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
 405 }
 406
 407 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 408 {
 409         int rc;
 410         u32 val;
 411
 412         mutex_lock(&dev->lock);
 413         /* Wait until we get a valid response */
 414         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
 415                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 416                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 417         if (rc) {
 418                 dev_err(dev->dev, "failed to talk to SMU\n");
 419                 goto out_unlock;
 420         }
 421
 422         /* Write zero to response register */
 423         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0);
 424
 425         /* Write argument into response register */
 426         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, arg);
 427
 428         /* Write message ID to message ID register */
 429         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
 430
 431         /* Wait until we get a valid response */
 432         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
 433                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 434                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 435         if (rc) {
 436                 dev_err(dev->dev, "SMU response timed out\n");
 437                 goto out_unlock;
 438         }
 439
 440         switch (val) {
 441         case AMD_PMC_RESULT_OK:
 442                 if (ret) {
 443                         /* PMFW may take longer time to return back the data */
 444                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 445                         *data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
 446                 }
 447                 break;
 448         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 449                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 450                 rc = -EBUSY;
 451                 goto out_unlock;
 452         case AMD_PMC_RESULT_CMD_UNKNOWN:
 453                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 454                 rc = -EINVAL;
 455                 goto out_unlock;
 456         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 457         case AMD_PMC_RESULT_FAILED:
 458         default:
 459                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 460                 rc = -EIO;
 461                 goto out_unlock;
 462         }
 463
 464 out_unlock:
 465         mutex_unlock(&dev->lock);
 466         amd_pmc_dump_registers(dev);
 467         return rc;
 468 }
 469
 470 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 471 {
 472         switch (dev->cpu_id) {
 473         case AMD_CPU_ID_PCO:
 474                 return MSG_OS_HINT_PCO;
 475         case AMD_CPU_ID_RN:
 476         case AMD_CPU_ID_YC:
 477                 return MSG_OS_HINT_RN;
 478         }
 479         return -EINVAL;
 480 }
 481
 482 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 483 {
 484         struct rtc_device *rtc_device;
 485         time64_t then, now, duration;
 486         struct rtc_wkalrm alarm;
 487         struct rtc_time tm;
 488         int rc;
 489
 490         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 491                 return 0;
 492
 493         rtc_device = rtc_class_open("rtc0");
 494         if (!rtc_device)
 495                 return 0;
 496         rc = rtc_read_alarm(rtc_device, &alarm);
 497         if (rc)
 498                 return rc;
 499         if (!alarm.enabled) {
 500                 dev_dbg(pdev->dev, "alarm not enabled\n");
 501                 return 0;
 502         }
 503         rc = rtc_read_time(rtc_device, &tm);
 504         if (rc)
 505                 return rc;
 506         then = rtc_tm_to_time64(&alarm.time);
 507         now = rtc_tm_to_time64(&tm);
 508         duration = then-now;
 509
 510         /* in the past */
 511         if (then < now)
 512                 return 0;
 513
 514         /* will be stored in upper 16 bits of s0i3 hint argument,
 515          * so timer wakeup from s0i3 is limited to ~18 hours or less
 516          */
 517         if (duration <= 4 || duration > U16_MAX)
 518                 return -EINVAL;
 519
 520         *arg |= (duration << 16);
 521         rc = rtc_alarm_irq_enable(rtc_device, 0);
 522         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 523
 524         return rc;
 525 }
 526
 527 static int __maybe_unused amd_pmc_suspend(struct device *dev)
 528 {
 529         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 530         int rc;
 531         u8 msg;
 532         u32 arg = 1;
 533
 534         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 535         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 536         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
 537
 538         /* Activate CZN specific RTC functionality */
 539         if (pdev->cpu_id == AMD_CPU_ID_CZN) {
 540                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 541                 if (rc < 0)
 542                         return rc;
 543         }
 544
 545         /* Dump the IdleMask before we send hint to SMU */
 546         amd_pmc_idlemask_read(pdev, dev, NULL);
 547         msg = amd_pmc_get_os_hint(pdev);
 548         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 549         if (rc)
 550                 dev_err(pdev->dev, "suspend failed\n");
 551
 552         if (enable_stb)
 553                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);
 554         if (rc) {
 555                 dev_err(pdev->dev, "error writing to STB\n");
 556                 return rc;
 557         }
 558
 559         return rc;
 560 }
 561
 562 static int __maybe_unused amd_pmc_resume(struct device *dev)
 563 {
 564         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 565         int rc;
 566         u8 msg;
 567
 568         msg = amd_pmc_get_os_hint(pdev);
 569         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 570         if (rc)
 571                 dev_err(pdev->dev, "resume failed\n");
 572
 573         /* Let SMU know that we are looking for stats */
 574         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 575
 576         /* Dump the IdleMask to see the blockers */
 577         amd_pmc_idlemask_read(pdev, dev, NULL);
 578
 579         /* Write data incremented by 1 to distinguish in stb_read */
 580         if (enable_stb)
 581                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);
 582         if (rc) {
 583                 dev_err(pdev->dev, "error writing to STB\n");
 584                 return rc;
 585         }
 586
 587         return 0;
 588 }
 589
 590 static const struct dev_pm_ops amd_pmc_pm_ops = {
 591         .suspend_noirq = amd_pmc_suspend,
 592         .resume_noirq = amd_pmc_resume,
 593 };
 594
 595 static const struct pci_device_id pmc_pci_ids[] = {
 596         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 597         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 598         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 599         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 600         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 601         { }
 602 };
 603
 604 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 605 {
 606         int err;
 607
 608         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 609         if (err) {
 610                 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
 611                         AMD_PMC_STB_INDEX_ADDRESS);
 612                 return pcibios_err_to_errno(err);
 613         }
 614
 615         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
 616         if (err) {
 617                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
 618                         AMD_PMC_STB_INDEX_DATA);
 619                 return pcibios_err_to_errno(err);
 620         }
 621
 622         return 0;
 623 }
 624
 625 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 626 {
 627         int i, err;
 628
 629         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 630         if (err) {
 631                 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
 632                         AMD_PMC_STB_INDEX_ADDRESS);
 633                 return pcibios_err_to_errno(err);
 634         }
 635
 636         for (i = 0; i < FIFO_SIZE; i++) {
 637                 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
 638                 if (err) {
 639                         dev_err(dev->dev, "error reading data from stb: 0x%X\n",
 640                                 AMD_PMC_STB_INDEX_DATA);
 641                         return pcibios_err_to_errno(err);
 642                 }
 643         }
 644
 645         return 0;
 646 }
 647
 648 static int amd_pmc_probe(struct platform_device *pdev)
 649 {
 650         struct amd_pmc_dev *dev = &pmc;
 651         struct pci_dev *rdev;
 652         u32 base_addr_lo, base_addr_hi;
 653         u64 base_addr, fch_phys_addr;
 654         int err;
 655         u32 val;
 656
 657         dev->dev = &pdev->dev;
 658
 659         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 660         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 661                 err = -ENODEV;
 662                 goto err_pci_dev_put;
 663         }
 664
 665         dev->cpu_id = rdev->device;
 666         dev->rdev = rdev;
 667         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 668         if (err) {
 669                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 670                 err = pcibios_err_to_errno(err);
 671                 goto err_pci_dev_put;
 672         }
 673
 674         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 675         if (err) {
 676                 err = pcibios_err_to_errno(err);
 677                 goto err_pci_dev_put;
 678         }
 679
 680         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 681
 682         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 683         if (err) {
 684                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 685                 err = pcibios_err_to_errno(err);
 686                 goto err_pci_dev_put;
 687         }
 688
 689         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 690         if (err) {
 691                 err = pcibios_err_to_errno(err);
 692                 goto err_pci_dev_put;
 693         }
 694
 695         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 696         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 697
 698         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 699                                     AMD_PMC_MAPPING_SIZE);
 700         if (!dev->regbase) {
 701                 err = -ENOMEM;
 702                 goto err_pci_dev_put;
 703         }
 704
 705         mutex_init(&dev->lock);
 706
 707         /* Use FCH registers to get the S0ix stats */
 708         base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 709         base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 710         fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 711         dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 712         if (!dev->fch_virt_addr) {
 713                 err = -ENOMEM;
 714                 goto err_pci_dev_put;
 715         }
 716
 717         /* Use SMU to get the s0i3 debug stats */
 718         err = amd_pmc_setup_smu_logging(dev);
 719         if (err)
 720                 dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
 721
 722         amd_pmc_get_smu_version(dev);
 723         platform_set_drvdata(pdev, dev);
 724         amd_pmc_dbgfs_register(dev);
 725         return 0;
 726
 727 err_pci_dev_put:
 728         pci_dev_put(rdev);
 729         return err;
 730 }
 731
 732 static int amd_pmc_remove(struct platform_device *pdev)
 733 {
 734         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
 735
 736         amd_pmc_dbgfs_unregister(dev);
 737         pci_dev_put(dev->rdev);
 738         mutex_destroy(&dev->lock);
 739         return 0;
 740 }
 741
 742 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 743         {"AMDI0005", 0},
 744         {"AMDI0006", 0},
 745         {"AMDI0007", 0},
 746         {"AMD0004", 0},
 747         {"AMD0005", 0},
 748         { }
 749 };
 750 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
 751
 752 static struct platform_driver amd_pmc_driver = {
 753         .driver = {
 754                 .name = "amd_pmc",
 755                 .acpi_match_table = amd_pmc_acpi_ids,
 756                 .pm = &amd_pmc_pm_ops,
 757         },
 758         .probe = amd_pmc_probe,
 759         .remove = amd_pmc_remove,
 760 };
 761 module_platform_driver(amd_pmc_driver);
 762
 763 MODULE_LICENSE("GPL v2");
 764 MODULE_DESCRIPTION("AMD PMC Driver");