drivers/platform/x86/amd/pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/limits.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/rtc.h>
  25 #include <linux/serio.h>
  26 #include <linux/suspend.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/uaccess.h>
  29
  30 /* SMU communication registers */
  31 #define AMD_PMC_REGISTER_MESSAGE        0x538
  32 #define AMD_PMC_REGISTER_RESPONSE       0x980
  33 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  34
  35 /* PMC Scratch Registers */
  36 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  37 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  38
  39 /* STB Registers */
  40 #define AMD_PMC_STB_INDEX_ADDRESS       0xF8
  41 #define AMD_PMC_STB_INDEX_DATA          0xFC
  42 #define AMD_PMC_STB_PMI_0               0x03E30600
  43 #define AMD_PMC_STB_S2IDLE_PREPARE      0xC6000001
  44 #define AMD_PMC_STB_S2IDLE_RESTORE      0xC6000002
  45 #define AMD_PMC_STB_S2IDLE_CHECK        0xC6000003
  46 #define AMD_PMC_STB_DUMMY_PC            0xC6000007
  47
  48 /* STB S2D(Spill to DRAM) has different message port offset */
  49 #define STB_SPILL_TO_DRAM               0xBE
  50 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  51 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  52 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  53
  54 /* STB Spill to DRAM Parameters */
  55 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  56 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  57
  58 /* Base address of SMU for mapping physical address to virtual address */
  59 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  60 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  61 #define AMD_PMC_MAPPING_SIZE            0x01000
  62 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  63 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  64 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  65 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  66 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  67
  68 /* SMU Response Codes */
  69 #define AMD_PMC_RESULT_OK                    0x01
  70 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  71 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  72 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  73 #define AMD_PMC_RESULT_FAILED                0xFF
  74
  75 /* FCH SSC Registers */
  76 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  77 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  78 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  79 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  80 #define FCH_SSC_MAPPING_SIZE            0x800
  81 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  82 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  83
  84 /* SMU Message Definations */
  85 #define SMU_MSG_GETSMUVERSION           0x02
  86 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  87 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  88 #define SMU_MSG_LOG_START               0x06
  89 #define SMU_MSG_LOG_RESET               0x07
  90 #define SMU_MSG_LOG_DUMP_DATA           0x08
  91 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  92 /* List of supported CPU ids */
  93 #define AMD_CPU_ID_RV                   0x15D0
  94 #define AMD_CPU_ID_RN                   0x1630
  95 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  96 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  97 #define AMD_CPU_ID_YC                   0x14B5
  98 #define AMD_CPU_ID_CB                   0x14D8
  99 #define AMD_CPU_ID_PS                   0x14E8
 100
 101 #define PMC_MSG_DELAY_MIN_US            50
 102 #define RESPONSE_REGISTER_LOOP_MAX      20000
 103
 104 #define SOC_SUBSYSTEM_IP_MAX    12
 105 #define DELAY_MIN_US            2000
 106 #define DELAY_MAX_US            3000
 107 #define FIFO_SIZE               4096
 108
 109 enum amd_pmc_def {
 110         MSG_TEST = 0x01,
 111         MSG_OS_HINT_PCO,
 112         MSG_OS_HINT_RN,
 113 };
 114
 115 enum s2d_arg {
 116         S2D_TELEMETRY_SIZE = 0x01,
 117         S2D_PHYS_ADDR_LOW,
 118         S2D_PHYS_ADDR_HIGH,
 119         S2D_NUM_SAMPLES,
 120 };
 121
 122 struct amd_pmc_bit_map {
 123         const char *name;
 124         u32 bit_mask;
 125 };
 126
 127 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 128         {"DISPLAY",     BIT(0)},
 129         {"CPU",         BIT(1)},
 130         {"GFX",         BIT(2)},
 131         {"VDD",         BIT(3)},
 132         {"ACP",         BIT(4)},
 133         {"VCN",         BIT(5)},
 134         {"ISP",         BIT(6)},
 135         {"NBIO",        BIT(7)},
 136         {"DF",          BIT(8)},
 137         {"USB0",        BIT(9)},
 138         {"USB1",        BIT(10)},
 139         {"LAPIC",       BIT(11)},
 140         {}
 141 };
 142
 143 struct amd_pmc_dev {
 144         void __iomem *regbase;
 145         void __iomem *smu_virt_addr;
 146         void __iomem *stb_virt_addr;
 147         void __iomem *fch_virt_addr;
 148         bool msg_port;
 149         u32 base_addr;
 150         u32 cpu_id;
 151         u32 active_ips;
 152 /* SMU version information */
 153         u8 smu_program;
 154         u8 major;
 155         u8 minor;
 156         u8 rev;
 157         struct device *dev;
 158         struct pci_dev *rdev;
 159         struct mutex lock; /* generic mutex lock */
 160         struct dentry *dbgfs_dir;
 161 };
 162
 163 static bool enable_stb;
 164 module_param(enable_stb, bool, 0644);
 165 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 166
 167 static bool disable_workarounds;
 168 module_param(disable_workarounds, bool, 0644);
 169 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
 170
 171 static struct amd_pmc_dev pmc;
 172 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 173 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 174 #ifdef CONFIG_SUSPEND
 175 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 176 #endif
 177
 178 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 179 {
 180         return ioread32(dev->regbase + reg_offset);
 181 }
 182
 183 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 184 {
 185         iowrite32(val, dev->regbase + reg_offset);
 186 }
 187
 188 struct smu_metrics {
 189         u32 table_version;
 190         u32 hint_count;
 191         u32 s0i3_last_entry_status;
 192         u32 timein_s0i2;
 193         u64 timeentering_s0i3_lastcapture;
 194         u64 timeentering_s0i3_totaltime;
 195         u64 timeto_resume_to_os_lastcapture;
 196         u64 timeto_resume_to_os_totaltime;
 197         u64 timein_s0i3_lastcapture;
 198         u64 timein_s0i3_totaltime;
 199         u64 timein_swdrips_lastcapture;
 200         u64 timein_swdrips_totaltime;
 201         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 202         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 203 } __packed;
 204
 205 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 206 {
 207         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 208         u32 size = FIFO_SIZE * sizeof(u32);
 209         u32 *buf;
 210         int rc;
 211
 212         buf = kzalloc(size, GFP_KERNEL);
 213         if (!buf)
 214                 return -ENOMEM;
 215
 216         rc = amd_pmc_read_stb(dev, buf);
 217         if (rc) {
 218                 kfree(buf);
 219                 return rc;
 220         }
 221
 222         filp->private_data = buf;
 223         return rc;
 224 }
 225
 226 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 227                                         loff_t *pos)
 228 {
 229         if (!filp->private_data)
 230                 return -EINVAL;
 231
 232         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 233                                        FIFO_SIZE * sizeof(u32));
 234 }
 235
 236 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 237 {
 238         kfree(filp->private_data);
 239         return 0;
 240 }
 241
 242 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 243         .owner = THIS_MODULE,
 244         .open = amd_pmc_stb_debugfs_open,
 245         .read = amd_pmc_stb_debugfs_read,
 246         .release = amd_pmc_stb_debugfs_release,
 247 };
 248
 249 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 250 {
 251         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 252         u32 *buf, fsize, num_samples, stb_rdptr_offset = 0;
 253         int ret;
 254
 255         /* Write dummy postcode while reading the STB buffer */
 256         ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
 257         if (ret)
 258                 dev_err(dev->dev, "error writing to STB: %d\n", ret);
 259
 260         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 261         if (!buf)
 262                 return -ENOMEM;
 263
 264         /* Spill to DRAM num_samples uses separate SMU message port */
 265         dev->msg_port = 1;
 266
 267         /* Get the num_samples to calculate the last push location */
 268         ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, STB_SPILL_TO_DRAM, 1);
 269         /* Clear msg_port for other SMU operation */
 270         dev->msg_port = 0;
 271         if (ret) {
 272                 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
 273                 return ret;
 274         }
 275
 276         /* Start capturing data from the last push location */
 277         if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
 278                 fsize  = S2D_TELEMETRY_BYTES_MAX;
 279                 stb_rdptr_offset = num_samples - fsize;
 280         } else {
 281                 fsize = num_samples;
 282                 stb_rdptr_offset = 0;
 283         }
 284
 285         memcpy_fromio(buf, dev->stb_virt_addr + stb_rdptr_offset, fsize);
 286         filp->private_data = buf;
 287
 288         return 0;
 289 }
 290
 291 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 292                                            loff_t *pos)
 293 {
 294         if (!filp->private_data)
 295                 return -EINVAL;
 296
 297         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 298                                         S2D_TELEMETRY_BYTES_MAX);
 299 }
 300
 301 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 302 {
 303         kfree(filp->private_data);
 304         return 0;
 305 }
 306
 307 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 308         .owner = THIS_MODULE,
 309         .open = amd_pmc_stb_debugfs_open_v2,
 310         .read = amd_pmc_stb_debugfs_read_v2,
 311         .release = amd_pmc_stb_debugfs_release_v2,
 312 };
 313
 314 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 315 {
 316         if (dev->cpu_id == AMD_CPU_ID_PCO) {
 317                 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
 318                 return -EINVAL;
 319         }
 320
 321         /* Get Active devices list from SMU */
 322         if (!dev->active_ips)
 323                 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 324
 325         /* Get dram address */
 326         if (!dev->smu_virt_addr) {
 327                 u32 phys_addr_low, phys_addr_hi;
 328                 u64 smu_phys_addr;
 329
 330                 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 331                 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 332                 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 333
 334                 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
 335                                                   sizeof(struct smu_metrics));
 336                 if (!dev->smu_virt_addr)
 337                         return -ENOMEM;
 338         }
 339
 340         /* Start the logging */
 341         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 342         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 343
 344         return 0;
 345 }
 346
 347 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 348                                  struct seq_file *s)
 349 {
 350         u32 val;
 351
 352         switch (pdev->cpu_id) {
 353         case AMD_CPU_ID_CZN:
 354                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 355                 break;
 356         case AMD_CPU_ID_YC:
 357         case AMD_CPU_ID_CB:
 358         case AMD_CPU_ID_PS:
 359                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 360                 break;
 361         default:
 362                 return -EINVAL;
 363         }
 364
 365         if (dev)
 366                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 367
 368         if (s)
 369                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 370
 371         return 0;
 372 }
 373
 374 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 375 {
 376         if (!pdev->smu_virt_addr) {
 377                 int ret = amd_pmc_setup_smu_logging(pdev);
 378
 379                 if (ret)
 380                         return ret;
 381         }
 382
 383         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 384                 return -ENODEV;
 385         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 386         return 0;
 387 }
 388
 389 #ifdef CONFIG_SUSPEND
 390 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 391 {
 392         struct smu_metrics table;
 393
 394         if (get_metrics_table(pdev, &table))
 395                 return;
 396
 397         if (!table.s0i3_last_entry_status)
 398                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 399         else
 400                 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
 401                          table.timein_s0i3_lastcapture);
 402 }
 403 #endif
 404
 405 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 406 {
 407         int rc;
 408         u32 val;
 409
 410         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 411         if (rc)
 412                 return rc;
 413
 414         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 415         dev->major = (val >> 16) & GENMASK(7, 0);
 416         dev->minor = (val >> 8) & GENMASK(7, 0);
 417         dev->rev = (val >> 0) & GENMASK(7, 0);
 418
 419         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 420                 dev->smu_program, dev->major, dev->minor, dev->rev);
 421
 422         return 0;
 423 }
 424
 425 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
 426                                    char *buf)
 427 {
 428         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 429
 430         if (!dev->major) {
 431                 int rc = amd_pmc_get_smu_version(dev);
 432
 433                 if (rc)
 434                         return rc;
 435         }
 436         return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
 437 }
 438
 439 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
 440                                    char *buf)
 441 {
 442         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 443
 444         if (!dev->major) {
 445                 int rc = amd_pmc_get_smu_version(dev);
 446
 447                 if (rc)
 448                         return rc;
 449         }
 450         return sysfs_emit(buf, "%u\n", dev->smu_program);
 451 }
 452
 453 static DEVICE_ATTR_RO(smu_fw_version);
 454 static DEVICE_ATTR_RO(smu_program);
 455
 456 static struct attribute *pmc_attrs[] = {
 457         &dev_attr_smu_fw_version.attr,
 458         &dev_attr_smu_program.attr,
 459         NULL,
 460 };
 461 ATTRIBUTE_GROUPS(pmc);
 462
 463 static int smu_fw_info_show(struct seq_file *s, void *unused)
 464 {
 465         struct amd_pmc_dev *dev = s->private;
 466         struct smu_metrics table;
 467         int idx;
 468
 469         if (get_metrics_table(dev, &table))
 470                 return -EINVAL;
 471
 472         seq_puts(s, "\n=== SMU Statistics ===\n");
 473         seq_printf(s, "Table Version: %d\n", table.table_version);
 474         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 475         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 476                    "Unknown/Fail");
 477         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 478         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 479         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 480                    table.timeto_resume_to_os_lastcapture);
 481
 482         seq_puts(s, "\n=== Active time (in us) ===\n");
 483         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 484                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 485                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 486                                    table.timecondition_notmet_lastcapture[idx]);
 487         }
 488
 489         return 0;
 490 }
 491 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 492
 493 static int s0ix_stats_show(struct seq_file *s, void *unused)
 494 {
 495         struct amd_pmc_dev *dev = s->private;
 496         u64 entry_time, exit_time, residency;
 497
 498         /* Use FCH registers to get the S0ix stats */
 499         if (!dev->fch_virt_addr) {
 500                 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 501                 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 502                 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 503
 504                 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 505                 if (!dev->fch_virt_addr)
 506                         return -ENOMEM;
 507         }
 508
 509         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 510         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 511
 512         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 513         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 514
 515         /* It's in 48MHz. We need to convert it */
 516         residency = exit_time - entry_time;
 517         do_div(residency, 48);
 518
 519         seq_puts(s, "=== S0ix statistics ===\n");
 520         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 521         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 522         seq_printf(s, "Residency Time: %lld\n", residency);
 523
 524         return 0;
 525 }
 526 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 527
 528 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 529 {
 530         struct amd_pmc_dev *dev = s->private;
 531         int rc;
 532
 533         /* we haven't yet read SMU version */
 534         if (!dev->major) {
 535                 rc = amd_pmc_get_smu_version(dev);
 536                 if (rc)
 537                         return rc;
 538         }
 539
 540         if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
 541                 rc = amd_pmc_idlemask_read(dev, NULL, s);
 542                 if (rc)
 543                         return rc;
 544         } else {
 545                 seq_puts(s, "Unsupported SMU version for Idlemask\n");
 546         }
 547
 548         return 0;
 549 }
 550 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 551
 552 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 553 {
 554         debugfs_remove_recursive(dev->dbgfs_dir);
 555 }
 556
 557 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 558 {
 559         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 560         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 561                             &smu_fw_info_fops);
 562         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 563                             &s0ix_stats_fops);
 564         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 565                             &amd_pmc_idlemask_fops);
 566         /* Enable STB only when the module_param is set */
 567         if (enable_stb) {
 568                 if (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
 569                     dev->cpu_id == AMD_CPU_ID_PS)
 570                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 571                                             &amd_pmc_stb_debugfs_fops_v2);
 572                 else
 573                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 574                                             &amd_pmc_stb_debugfs_fops);
 575         }
 576 }
 577
 578 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 579 {
 580         u32 value, message, argument, response;
 581
 582         if (dev->msg_port) {
 583                 message = AMD_S2D_REGISTER_MESSAGE;
 584                 argument = AMD_S2D_REGISTER_ARGUMENT;
 585                 response = AMD_S2D_REGISTER_RESPONSE;
 586         } else {
 587                 message = AMD_PMC_REGISTER_MESSAGE;
 588                 argument = AMD_PMC_REGISTER_ARGUMENT;
 589                 response = AMD_PMC_REGISTER_RESPONSE;
 590         }
 591
 592         value = amd_pmc_reg_read(dev, response);
 593         dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 594
 595         value = amd_pmc_reg_read(dev, argument);
 596         dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 597
 598         value = amd_pmc_reg_read(dev, message);
 599         dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 600 }
 601
 602 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 603 {
 604         int rc;
 605         u32 val, message, argument, response;
 606
 607         mutex_lock(&dev->lock);
 608
 609         if (dev->msg_port) {
 610                 message = AMD_S2D_REGISTER_MESSAGE;
 611                 argument = AMD_S2D_REGISTER_ARGUMENT;
 612                 response = AMD_S2D_REGISTER_RESPONSE;
 613         } else {
 614                 message = AMD_PMC_REGISTER_MESSAGE;
 615                 argument = AMD_PMC_REGISTER_ARGUMENT;
 616                 response = AMD_PMC_REGISTER_RESPONSE;
 617         }
 618
 619         /* Wait until we get a valid response */
 620         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 621                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 622                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 623         if (rc) {
 624                 dev_err(dev->dev, "failed to talk to SMU\n");
 625                 goto out_unlock;
 626         }
 627
 628         /* Write zero to response register */
 629         amd_pmc_reg_write(dev, response, 0);
 630
 631         /* Write argument into response register */
 632         amd_pmc_reg_write(dev, argument, arg);
 633
 634         /* Write message ID to message ID register */
 635         amd_pmc_reg_write(dev, message, msg);
 636
 637         /* Wait until we get a valid response */
 638         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 639                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 640                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 641         if (rc) {
 642                 dev_err(dev->dev, "SMU response timed out\n");
 643                 goto out_unlock;
 644         }
 645
 646         switch (val) {
 647         case AMD_PMC_RESULT_OK:
 648                 if (ret) {
 649                         /* PMFW may take longer time to return back the data */
 650                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 651                         *data = amd_pmc_reg_read(dev, argument);
 652                 }
 653                 break;
 654         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 655                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 656                 rc = -EBUSY;
 657                 goto out_unlock;
 658         case AMD_PMC_RESULT_CMD_UNKNOWN:
 659                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 660                 rc = -EINVAL;
 661                 goto out_unlock;
 662         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 663         case AMD_PMC_RESULT_FAILED:
 664         default:
 665                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 666                 rc = -EIO;
 667                 goto out_unlock;
 668         }
 669
 670 out_unlock:
 671         mutex_unlock(&dev->lock);
 672         amd_pmc_dump_registers(dev);
 673         return rc;
 674 }
 675
 676 #ifdef CONFIG_SUSPEND
 677 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 678 {
 679         switch (dev->cpu_id) {
 680         case AMD_CPU_ID_PCO:
 681                 return MSG_OS_HINT_PCO;
 682         case AMD_CPU_ID_RN:
 683         case AMD_CPU_ID_YC:
 684         case AMD_CPU_ID_CB:
 685         case AMD_CPU_ID_PS:
 686                 return MSG_OS_HINT_RN;
 687         }
 688         return -EINVAL;
 689 }
 690
 691 static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev)
 692 {
 693         struct device *d;
 694         int rc;
 695
 696         if (!pdev->major) {
 697                 rc = amd_pmc_get_smu_version(pdev);
 698                 if (rc)
 699                         return rc;
 700         }
 701
 702         if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
 703                 return 0;
 704
 705         d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
 706         if (!d)
 707                 return 0;
 708         if (device_may_wakeup(d)) {
 709                 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
 710                 disable_irq_wake(1);
 711                 device_set_wakeup_enable(d, false);
 712         }
 713         put_device(d);
 714
 715         return 0;
 716 }
 717
 718 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 719 {
 720         struct rtc_device *rtc_device;
 721         time64_t then, now, duration;
 722         struct rtc_wkalrm alarm;
 723         struct rtc_time tm;
 724         int rc;
 725
 726         /* we haven't yet read SMU version */
 727         if (!pdev->major) {
 728                 rc = amd_pmc_get_smu_version(pdev);
 729                 if (rc)
 730                         return rc;
 731         }
 732
 733         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 734                 return 0;
 735
 736         rtc_device = rtc_class_open("rtc0");
 737         if (!rtc_device)
 738                 return 0;
 739         rc = rtc_read_alarm(rtc_device, &alarm);
 740         if (rc)
 741                 return rc;
 742         if (!alarm.enabled) {
 743                 dev_dbg(pdev->dev, "alarm not enabled\n");
 744                 return 0;
 745         }
 746         rc = rtc_read_time(rtc_device, &tm);
 747         if (rc)
 748                 return rc;
 749         then = rtc_tm_to_time64(&alarm.time);
 750         now = rtc_tm_to_time64(&tm);
 751         duration = then-now;
 752
 753         /* in the past */
 754         if (then < now)
 755                 return 0;
 756
 757         /* will be stored in upper 16 bits of s0i3 hint argument,
 758          * so timer wakeup from s0i3 is limited to ~18 hours or less
 759          */
 760         if (duration <= 4 || duration > U16_MAX)
 761                 return -EINVAL;
 762
 763         *arg |= (duration << 16);
 764         rc = rtc_alarm_irq_enable(rtc_device, 0);
 765         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 766
 767         return rc;
 768 }
 769
 770 static void amd_pmc_s2idle_prepare(void)
 771 {
 772         struct amd_pmc_dev *pdev = &pmc;
 773         int rc;
 774         u8 msg;
 775         u32 arg = 1;
 776
 777         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 778         amd_pmc_setup_smu_logging(pdev);
 779
 780         /* Activate CZN specific platform bug workarounds */
 781         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 782                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 783                 if (rc) {
 784                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 785                         return;
 786                 }
 787         }
 788
 789         msg = amd_pmc_get_os_hint(pdev);
 790         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 791         if (rc) {
 792                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 793                 return;
 794         }
 795
 796         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
 797         if (rc)
 798                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 799 }
 800
 801 static void amd_pmc_s2idle_check(void)
 802 {
 803         struct amd_pmc_dev *pdev = &pmc;
 804         struct smu_metrics table;
 805         int rc;
 806
 807         /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
 808         if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
 809             table.s0i3_last_entry_status)
 810                 usleep_range(10000, 20000);
 811
 812         /* Dump the IdleMask before we add to the STB */
 813         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 814
 815         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
 816         if (rc)
 817                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 818 }
 819
 820 static void amd_pmc_s2idle_restore(void)
 821 {
 822         struct amd_pmc_dev *pdev = &pmc;
 823         int rc;
 824         u8 msg;
 825
 826         msg = amd_pmc_get_os_hint(pdev);
 827         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 828         if (rc)
 829                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 830
 831         /* Let SMU know that we are looking for stats */
 832         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 833
 834         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
 835         if (rc)
 836                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 837
 838         /* Notify on failed entry */
 839         amd_pmc_validate_deepest(pdev);
 840 }
 841
 842 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 843         .prepare = amd_pmc_s2idle_prepare,
 844         .check = amd_pmc_s2idle_check,
 845         .restore = amd_pmc_s2idle_restore,
 846 };
 847
 848 static int __maybe_unused amd_pmc_suspend_handler(struct device *dev)
 849 {
 850         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 851
 852         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 853                 int rc = amd_pmc_czn_wa_irq1(pdev);
 854
 855                 if (rc) {
 856                         dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
 857                         return rc;
 858                 }
 859         }
 860
 861         return 0;
 862 }
 863
 864 static SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL);
 865
 866 #endif
 867
 868 static const struct pci_device_id pmc_pci_ids[] = {
 869         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
 870         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
 871         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 872         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 873         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 874         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 875         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 876         { }
 877 };
 878
 879 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 880 {
 881         u32 phys_addr_low, phys_addr_hi;
 882         u64 stb_phys_addr;
 883         u32 size = 0;
 884
 885         /* Spill to DRAM feature uses separate SMU message port */
 886         dev->msg_port = 1;
 887
 888         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
 889         if (size != S2D_TELEMETRY_BYTES_MAX)
 890                 return -EIO;
 891
 892         /* Get STB DRAM address */
 893         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
 894         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
 895
 896         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 897
 898         /* Clear msg_port for other SMU operation */
 899         dev->msg_port = 0;
 900
 901         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
 902         if (!dev->stb_virt_addr)
 903                 return -ENOMEM;
 904
 905         return 0;
 906 }
 907
 908 #ifdef CONFIG_SUSPEND
 909 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 910 {
 911         int err;
 912
 913         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 914         if (err) {
 915                 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
 916                         AMD_PMC_STB_INDEX_ADDRESS);
 917                 return pcibios_err_to_errno(err);
 918         }
 919
 920         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
 921         if (err) {
 922                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
 923                         AMD_PMC_STB_INDEX_DATA);
 924                 return pcibios_err_to_errno(err);
 925         }
 926
 927         return 0;
 928 }
 929 #endif
 930
 931 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 932 {
 933         int i, err;
 934
 935         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 936         if (err) {
 937                 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
 938                         AMD_PMC_STB_INDEX_ADDRESS);
 939                 return pcibios_err_to_errno(err);
 940         }
 941
 942         for (i = 0; i < FIFO_SIZE; i++) {
 943                 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
 944                 if (err) {
 945                         dev_err(dev->dev, "error reading data from stb: 0x%X\n",
 946                                 AMD_PMC_STB_INDEX_DATA);
 947                         return pcibios_err_to_errno(err);
 948                 }
 949         }
 950
 951         return 0;
 952 }
 953
 954 static int amd_pmc_probe(struct platform_device *pdev)
 955 {
 956         struct amd_pmc_dev *dev = &pmc;
 957         struct pci_dev *rdev;
 958         u32 base_addr_lo, base_addr_hi;
 959         u64 base_addr;
 960         int err;
 961         u32 val;
 962
 963         dev->dev = &pdev->dev;
 964
 965         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 966         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 967                 err = -ENODEV;
 968                 goto err_pci_dev_put;
 969         }
 970
 971         dev->cpu_id = rdev->device;
 972         dev->rdev = rdev;
 973         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 974         if (err) {
 975                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 976                 err = pcibios_err_to_errno(err);
 977                 goto err_pci_dev_put;
 978         }
 979
 980         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 981         if (err) {
 982                 err = pcibios_err_to_errno(err);
 983                 goto err_pci_dev_put;
 984         }
 985
 986         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 987
 988         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 989         if (err) {
 990                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 991                 err = pcibios_err_to_errno(err);
 992                 goto err_pci_dev_put;
 993         }
 994
 995         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 996         if (err) {
 997                 err = pcibios_err_to_errno(err);
 998                 goto err_pci_dev_put;
 999         }
1000
1001         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
1002         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
1003
1004         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
1005                                     AMD_PMC_MAPPING_SIZE);
1006         if (!dev->regbase) {
1007                 err = -ENOMEM;
1008                 goto err_pci_dev_put;
1009         }
1010
1011         mutex_init(&dev->lock);
1012
1013         if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
1014                 err = amd_pmc_s2d_init(dev);
1015                 if (err)
1016                         goto err_pci_dev_put;
1017         }
1018
1019         platform_set_drvdata(pdev, dev);
1020 #ifdef CONFIG_SUSPEND
1021         err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1022         if (err)
1023                 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1024 #endif
1025
1026         amd_pmc_dbgfs_register(dev);
1027         return 0;
1028
1029 err_pci_dev_put:
1030         pci_dev_put(rdev);
1031         return err;
1032 }
1033
1034 static int amd_pmc_remove(struct platform_device *pdev)
1035 {
1036         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1037
1038 #ifdef CONFIG_SUSPEND
1039         acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1040 #endif
1041         amd_pmc_dbgfs_unregister(dev);
1042         pci_dev_put(dev->rdev);
1043         mutex_destroy(&dev->lock);
1044         return 0;
1045 }
1046
1047 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1048         {"AMDI0005", 0},
1049         {"AMDI0006", 0},
1050         {"AMDI0007", 0},
1051         {"AMDI0008", 0},
1052         {"AMDI0009", 0},
1053         {"AMD0004", 0},
1054         {"AMD0005", 0},
1055         { }
1056 };
1057 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1058
1059 static struct platform_driver amd_pmc_driver = {
1060         .driver = {
1061                 .name = "amd_pmc",
1062                 .acpi_match_table = amd_pmc_acpi_ids,
1063                 .dev_groups = pmc_groups,
1064 #ifdef CONFIG_SUSPEND
1065                 .pm = &amd_pmc_pm,
1066 #endif
1067         },
1068         .probe = amd_pmc_probe,
1069         .remove = amd_pmc_remove,
1070 };
1071 module_platform_driver(amd_pmc_driver);
1072
1073 MODULE_LICENSE("GPL v2");
1074 MODULE_DESCRIPTION("AMD PMC Driver");