2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/clockchips.h>
19 #include <linux/spinlock.h>
20 #include <linux/bitops.h>
21 #include <linux/err.h>
23 #include <linux/sched.h>
24 #include <linux/clocksource.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
28 #include <asm/sched_clock.h>
29 #include <asm/localtimer.h>
30 #include <asm/mach/time.h>
32 #include <soc/sprd/hardware.h>
33 #include <soc/sprd/sci.h>
34 #include <soc/sprd/sci_glb_regs.h>
35 #include <mach/irqs.h>
36 #include <asm/mach/time.h>
37 #include <soc/sprd/sprd_persistent_clock.h>
39 static __iomem void *base_gptimer[4] = {
43 static int irq_nr[4] = {
46 static struct clock_event_device *local_evt[4] = { 0 };
49 #define TIMER_LOAD(ind, id) (base_gptimer[ind] + 0x20 * (id) + 0x0000)
50 #define TIMER_VALUE(ind, id) (base_gptimer[ind] + 0x20 * (id) + 0x0004)
51 #define TIMER_CTL(ind, id) (base_gptimer[ind] + 0x20 * (id) + 0x0008)
52 #define TIMER_INT(ind, id) (base_gptimer[ind] + 0x20 * (id) + 0x000C)
53 #define TIMER_CNT_RD(ind, id) (base_gptimer[ind] + 0x20 * (id) + 0x0010)
55 #define ONETIME_MODE (0 << 6)
56 #define PERIOD_MODE (1 << 6)
58 #define TIMER_DISABLE (0 << 7)
59 #define TIMER_ENABLE (1 << 7)
61 #define TIMER_INT_EN (1 << 0)
62 #define TIMER_INT_CLR (1 << 3)
63 #define TIMER_INT_BUSY (1 << 4)
64 #define TIMER_NEW (1 << 8)
66 * timer0 is used as clockevent,
67 * timer1 of aptimer0 is used as broadcast timer,
68 * timer1 is used as clocksource
72 #define SOURCE_TIMER 1
75 static int BC_IRQ = 0;
77 static __iomem void *base_syscnt = (__iomem void *)NULL;
79 #define SYSCNT_ALARM (base_syscnt + 0x0000)
80 #define SYSCNT_COUNT (base_syscnt + 0x0004)
81 #define SYSCNT_CTL (base_syscnt + 0x0008)
82 #define SYSCNT_SHADOW_CNT (base_syscnt + 0x000C)
84 static int sched_clock_source_freq;
85 static int gptimer_clock_source_freq;
87 /*only for 2713 charger*/
88 int sprd_request_timer(int timer_id, int sub_id, unsigned long *base)
90 if (1 == timer_id && 1 == sub_id) {
91 *base = (unsigned long)(base_gptimer[2] + 0x20);
97 static inline void __gptimer_ctl(int cpu, int timer_id, int enable, int mode)
99 __raw_writel(enable | mode, TIMER_CTL(cpu, timer_id));
102 static int __gptimer_set_next_event(unsigned long cycles,
103 struct clock_event_device *c)
105 int cpu = smp_processor_id();
107 while (TIMER_INT_BUSY & __raw_readl(TIMER_INT(cpu, EVENT_TIMER))) ;
108 __gptimer_ctl(cpu, EVENT_TIMER, TIMER_DISABLE, ONETIME_MODE);
109 __raw_writel(cycles, TIMER_LOAD(cpu, EVENT_TIMER));
110 __gptimer_ctl(cpu, EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE);
114 static void __gptimer_set_mode(enum clock_event_mode mode,
115 struct clock_event_device *c)
118 int cpu = smp_processor_id();
121 case CLOCK_EVT_MODE_PERIODIC:
122 __gptimer_ctl(cpu, EVENT_TIMER, TIMER_DISABLE, PERIOD_MODE);
123 __raw_writel(LATCH, TIMER_LOAD(cpu, EVENT_TIMER));
124 __gptimer_ctl(cpu, EVENT_TIMER, TIMER_ENABLE, PERIOD_MODE);
125 __raw_writel(TIMER_INT_EN, TIMER_INT(cpu, EVENT_TIMER));
127 case CLOCK_EVT_MODE_ONESHOT:
128 __raw_writel(LATCH, TIMER_LOAD(cpu, EVENT_TIMER));
129 __gptimer_ctl(cpu, EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE);
130 __raw_writel(TIMER_INT_EN, TIMER_INT(cpu, EVENT_TIMER));
132 case CLOCK_EVT_MODE_SHUTDOWN:
133 case CLOCK_EVT_MODE_UNUSED:
134 __raw_writel(TIMER_INT_CLR, TIMER_INT(cpu, EVENT_TIMER));
135 saved = __raw_readl(TIMER_CTL(cpu, EVENT_TIMER)) & PERIOD_MODE;
136 __gptimer_ctl(cpu, EVENT_TIMER, TIMER_DISABLE, saved);
138 case CLOCK_EVT_MODE_RESUME:
139 saved = __raw_readl(TIMER_CTL(cpu, EVENT_TIMER)) & PERIOD_MODE;
140 __gptimer_ctl(cpu, EVENT_TIMER, TIMER_ENABLE, saved);
145 static int __bctimer_set_next_event(unsigned long cycles,
146 struct clock_event_device *c)
148 while (TIMER_INT_BUSY & __raw_readl(TIMER_INT(BC_CPU, BC_TIMER))) ;
149 __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_DISABLE, ONETIME_MODE);
150 __raw_writel(cycles, TIMER_LOAD(BC_CPU, BC_TIMER));
151 __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, ONETIME_MODE);
155 static void __bctimer_set_mode(enum clock_event_mode mode,
156 struct clock_event_device *c)
161 case CLOCK_EVT_MODE_PERIODIC:
162 __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_DISABLE, PERIOD_MODE);
163 __raw_writel(LATCH, TIMER_LOAD(BC_CPU, BC_TIMER));
164 __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, PERIOD_MODE);
165 __raw_writel(TIMER_INT_EN, TIMER_INT(BC_CPU, BC_TIMER));
167 case CLOCK_EVT_MODE_ONESHOT:
168 __raw_writel(LATCH, TIMER_LOAD(BC_CPU, BC_TIMER));
169 __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, ONETIME_MODE);
170 __raw_writel(TIMER_INT_EN, TIMER_INT(BC_CPU, BC_TIMER));
172 case CLOCK_EVT_MODE_SHUTDOWN:
173 case CLOCK_EVT_MODE_UNUSED:
174 __raw_writel(TIMER_INT_CLR, TIMER_INT(BC_CPU, BC_TIMER));
175 saved = __raw_readl(TIMER_CTL(BC_CPU, BC_TIMER)) & PERIOD_MODE;
176 __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_DISABLE, saved);
178 case CLOCK_EVT_MODE_RESUME:
179 saved = __raw_readl(TIMER_CTL(BC_CPU, BC_TIMER)) & PERIOD_MODE;
180 __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, saved);
185 static struct clock_event_device bctimer_event = {
186 .features = CLOCK_EVT_FEAT_ONESHOT,
189 .set_next_event = __bctimer_set_next_event,
190 .set_mode = __bctimer_set_mode,
193 static irqreturn_t __gptimer_interrupt(int irq, void *dev_id);
194 #ifdef CONFIG_LOCAL_TIMERS
195 #if !defined (CONFIG_HAVE_ARM_ARCH_TIMER)
196 static int __cpuinit sprd_local_timer_setup(struct clock_event_device *evt)
198 int cpu = smp_processor_id();
200 evt->irq = irq_nr[cpu];
201 evt->name = "local_timer";
202 evt->features = CLOCK_EVT_FEAT_ONESHOT;
204 evt->set_mode = __gptimer_set_mode;
205 evt->set_next_event = __gptimer_set_next_event;
207 evt->mult = div_sc(32768, NSEC_PER_SEC, evt->shift);
208 evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
209 evt->min_delta_ns = clockevent_delta2ns(4, evt);
211 local_evt[cpu] = evt;
212 irq_set_affinity(evt->irq, cpumask_of(cpu));
214 clockevents_register_device(evt);
218 static void sprd_local_timer_stop(struct clock_event_device *evt)
220 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
223 static struct local_timer_ops sprd_local_timer_ops __cpuinitdata = {
224 .setup = sprd_local_timer_setup,
225 .stop = sprd_local_timer_stop,
228 #endif /* CONFIG_LOCAL_TIMERS */
230 static irqreturn_t __gptimer_interrupt(int irq, void *dev_id)
233 int cpu = smp_processor_id();
234 struct clock_event_device **evt = dev_id;
236 value = __raw_readl(TIMER_INT(cpu, EVENT_TIMER));
237 value |= TIMER_INT_CLR;
238 __raw_writel(value, TIMER_INT(cpu, EVENT_TIMER));
240 if (evt[cpu]->event_handler)
241 evt[cpu]->event_handler(evt[cpu]);
246 static irqreturn_t __bctimer_interrupt(int irq, void *dev_id)
249 struct clock_event_device *evt = dev_id;
251 value = __raw_readl(TIMER_INT(BC_CPU, BC_TIMER));
252 value |= TIMER_INT_CLR;
253 __raw_writel(value, TIMER_INT(BC_CPU, BC_TIMER));
255 if (evt->event_handler)
256 evt->event_handler(evt);
261 static struct irqaction bctimer_irq = {
263 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
264 .handler = __bctimer_interrupt,
265 .dev_id = &bctimer_event,
268 static void sprd_gptimer_clockevent_init(unsigned int irq, const char *name,
271 struct clock_event_device *evt = &bctimer_event;
274 __raw_writel(TIMER_DISABLE, TIMER_CTL(BC_CPU, BC_TIMER));
275 __raw_writel(TIMER_INT_CLR, TIMER_INT(BC_CPU, BC_TIMER));
279 evt->mult = div_sc(hz, NSEC_PER_SEC, evt->shift);
280 evt->max_delta_ns = clockevent_delta2ns(ULONG_MAX, evt);
281 evt->min_delta_ns = clockevent_delta2ns(2, evt);
282 evt->cpumask = cpu_all_mask;
284 ret = setup_irq(irq, &bctimer_irq);
287 clockevents_register_device(evt);
290 /* ****************************************************************** */
291 void __gptimer_clocksource_resume(struct clocksource *cs)
293 __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_ENABLE | TIMER_NEW,
295 pr_debug("%s: timer_val=0x%x\n", __FUNCTION__,
296 __raw_readl(TIMER_CNT_RD(e_cpu, SOURCE_TIMER)));
299 void __gptimer_clocksource_suspend(struct clocksource *cs)
301 __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_DISABLE, PERIOD_MODE);
302 pr_debug("%s: timer_val=0x%x\n", __FUNCTION__,
303 __raw_readl(TIMER_CNT_RD(e_cpu, SOURCE_TIMER)));
306 cycle_t __gptimer_clocksource_read(struct clocksource *cs)
308 return ~readl_relaxed(TIMER_CNT_RD(e_cpu, SOURCE_TIMER));
311 struct clocksource clocksource_sprd = {
312 .name = "aon_timer_timer1",
314 .read = __gptimer_clocksource_read,
315 .mask = CLOCKSOURCE_MASK(32),
316 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
317 .resume = __gptimer_clocksource_resume,
318 .suspend = __gptimer_clocksource_suspend,
321 static void __gptimer_clocksource_init(void)
323 /* disalbe irq since it's just a read source */
324 __raw_writel(0, TIMER_INT(e_cpu, SOURCE_TIMER));
326 __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_DISABLE | TIMER_NEW,
328 __raw_writel(ULONG_MAX, TIMER_LOAD(e_cpu, SOURCE_TIMER));
329 __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_NEW, PERIOD_MODE);
330 __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_ENABLE | TIMER_NEW,
333 if (clocksource_register_hz
334 (&clocksource_sprd, gptimer_clock_source_freq))
335 printk("%s: can't register clocksource\n",
336 clocksource_sprd.name);
339 static void __syscnt_clocksource_init(const char *name, unsigned long hz)
341 /* disable irq for syscnt */
342 __raw_writel(0, SYSCNT_CTL);
344 clocksource_mmio_init(SYSCNT_SHADOW_CNT, name,
345 hz, 200, 32, clocksource_mmio_readw_up);
348 /* ****************************************************************** */
349 static u32 notrace __update_sched_clock(void)
351 return ~(readl_relaxed(TIMER_CNT_RD(0, SOURCE_TIMER)));
354 static void __init __sched_clock_init(unsigned long rate)
356 setup_sched_clock(__update_sched_clock, 32, rate);
359 void __init sci_enable_timer_early(void)
361 /* enable timer & syscnt in global regs */
363 sci_glb_set(REG_AON_APB_APB_EB0,
364 BIT_AON_TMR_EB | BIT_AP_SYST_EB | BIT_AP_TMR0_EB);
365 #if defined CONFIG_LOCAL_TIMERS && !defined CONFIG_HAVE_ARM_ARCH_TIMER
366 sci_glb_set(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB);
367 for (i = 0; i < 4; i++) {
369 sci_glb_clr(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB);
370 for (i = 0; i < 2; i++) {
372 for (j = 0; j < 3; j++) {
373 __gptimer_ctl(i, j, TIMER_DISABLE, 0);
374 __raw_writel(TIMER_INT_CLR, TIMER_INT(i, j));
378 #if defined(CONFIG_ARCH_SCX30G) || defined(CONFIG_ARCH_SCX35L)
379 /*timer1 fixed 32768 clk */
380 sched_clock_source_freq = 32768;
381 #else /*timer2 clk source is from apb clk */
382 val = sci_glb_read(REG_AON_CLK_AON_APB_CFG, -1) & 0x3;
384 sched_clock_source_freq = 76800000;
386 sched_clock_source_freq = 96000000;
388 sched_clock_source_freq = 128000000;
390 sched_clock_source_freq = 26000000; /*default setting */
393 gptimer_clock_source_freq = sched_clock_source_freq;
394 #if !defined (CONFIG_HAVE_ARM_ARCH_TIMER)
395 __sched_clock_init(sched_clock_source_freq);
399 u32 get_sys_cnt(void)
402 val = __raw_readl(SYSCNT_SHADOW_CNT);
406 void set_ap_system_timer_expires(u32 expires_ms)
408 u32 val = get_sys_cnt();
409 val = val + expires_ms;
410 __raw_writel(val, SYSCNT_ALARM);
411 __raw_writel(1, SYSCNT_CTL);
414 static irqreturn_t sys_cnt_isr(int irq, void *dev_id)
416 __raw_writel(8, SYSCNT_CTL);
420 static struct timespec persistent_ts;
421 static u64 persistent_ms, last_persistent_ms;
422 static void sprd_read_persistent_clock(struct timespec *ts)
425 struct timespec *tsp = &persistent_ts;
427 last_persistent_ms = persistent_ms;
428 persistent_ms = get_sys_cnt();
429 delta = persistent_ms - last_persistent_ms;
431 timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
435 void __init sci_timer_init(void)
437 #ifdef CONFIG_LOCAL_TIMERS
438 #if !defined (CONFIG_HAVE_ARM_ARCH_TIMER)
440 local_timer_register(&sprd_local_timer_ops);
441 for (i = 0; i < CONFIG_NR_CPUS; i++) {
442 ret = request_irq(irq_nr[i], __gptimer_interrupt,
443 IRQF_TIMER | IRQF_NOBALANCING | IRQF_DISABLED
444 | IRQF_PERCPU, "local_timer", local_evt);
446 printk(KERN_ERR "request local timer irq %d failed\n",
452 /* setup aon timer timer1 and syscnt as clocksource */
453 __gptimer_clocksource_init();
454 __syscnt_clocksource_init("syscnt", 1000);
455 /* setup timer1 of aon timer as clockevent. */
456 sprd_gptimer_clockevent_init(BC_IRQ, "bctimer", 32768);
457 register_persistent_clock(NULL, sprd_read_persistent_clock);
459 printk(KERN_INFO "sci_timer_init\n");
462 #define LOCAL_TIMER_CNT 4
463 static void __init sprd_init_timer(struct device_node *np)
467 int syscnt_irqnr = 0;
469 printk("%s \n", __func__);
470 ret = of_address_to_resource(np, 0, &res);
472 panic("Can't get syscnt registers!\n");
474 base_syscnt = ioremap_nocache(res.start, res.end - res.start);
476 panic("ioremap_nocache failed!");
478 syscnt_irqnr = irq_of_parse_and_map(np, 5);
479 if (syscnt_irqnr < 0)
480 panic("Can't map ap system timer irq!\n");
482 ret = request_irq(syscnt_irqnr,
483 sys_cnt_isr, IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND,
486 panic("sys cnt isr register failed\n");
488 for (i = 0; i < LOCAL_TIMER_CNT; i++) {
490 ret = of_address_to_resource(np, i + 1, &res);
492 panic("Can't get timer %d registers for local timer",
495 vaddr = ioremap_nocache(res.start, resource_size(&res));
497 base_gptimer[i] = vaddr;
499 panic("ioremap_nocache failed!");
501 BC_IRQ = irq_of_parse_and_map(np, 0);
503 panic("Can't map bc irq");
505 for (i = 0; i < LOCAL_TIMER_CNT; i++) {
506 *(irq_nr + i) = irq_of_parse_and_map(np, i + 1);
507 if (*(irq_nr + i) < 0)
508 panic("Can't map bc irq");
511 sci_enable_timer_early();
515 CLOCKSOURCE_OF_DECLARE(scx35_timer, "sprd,scx35-timer", sprd_init_timer);