tizen 2.4 release
[profile/mobile/platform/kernel/linux-3.10-sc7730.git] / drivers / platform / sprd / cpufreq-scx35.c
1 /*
2  * Copyright (C) 2013 Spreadtrum Communications Inc.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/sched.h>
20 #include <linux/cpufreq.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26 #include <linux/debugfs.h>
27 #include <linux/cpu.h>
28 #include <linux/regulator/consumer.h>
29 //#include <asm/system.h>
30 #include <trace/events/power.h>
31
32 #include <soc/sprd/hardware.h>
33 #include <soc/sprd/regulator.h>
34 #include <soc/sprd/adi.h>
35 #include <soc/sprd/sci.h>
36 #include <soc/sprd/sci_glb_regs.h>
37 #include <soc/sprd/arch_misc.h>
38 #include <linux/pm_qos.h>
39 #include <linux/of_platform.h>
40
41 #if defined(CONFIG_ARCH_SC8825)
42 #define MHz                     (1000000)
43 #define GR_MPLL_REFIN_2M        (2 * MHz)
44 #define GR_MPLL_REFIN_4M        (4 * MHz)
45 #define GR_MPLL_REFIN_13M       (13 * MHz)
46 #define GR_MPLL_REFIN_SHIFT     16
47 #define GR_MPLL_REFIN_MASK      (0x3)
48 #define GR_MPLL_N_MASK          (0x7ff)
49 #define GR_MPLL_MN              (REG_GLB_M_PLL_CTL0)
50 #define GR_GEN1                 (REG_GLB_GEN1)
51 #endif
52
53 #define FREQ_TABLE_SIZE         10
54 #define DVFS_BOOT_TIME  (30 * HZ)
55 #define SHARK_TDPLL_FREQUENCY   (768000)
56 #define TRANSITION_LATENCY      (50 * 1000) /* ns */
57
58 static DEFINE_MUTEX(freq_lock);
59 struct cpufreq_freqs global_freqs;
60 unsigned int percpu_target[CONFIG_NR_CPUS] = {0};
61 static unsigned long boot_done;
62 static unsigned int sprd_top_frequency; /* khz */
63
64 struct cpufreq_conf {
65         struct clk                                      *clk;
66         struct clk                                      *mpllclk;
67         struct clk                                      *tdpllclk;
68         struct regulator                                *regulator;
69         struct cpufreq_frequency_table                  *freq_tbl;
70         unsigned int                                    *vddarm_mv;
71         unsigned int                                    max_axi_freq;
72 };
73
74 struct cpufreq_table_data {
75         struct cpufreq_frequency_table          freq_tbl[FREQ_TABLE_SIZE];
76         unsigned int                            vddarm_mv[FREQ_TABLE_SIZE];
77 };
78
79 struct cpufreq_conf *sprd_cpufreq_conf = NULL;
80 static struct mutex cpufreq_vddarm_lock;
81
82 #if defined(CONFIG_ARCH_SC8825)
83 static struct cpufreq_table_data sc8825_cpufreq_table_data = {
84         .freq_tbl =     {
85                 {0, 1000000},
86                 {1, 500000},
87                 {2, CPUFREQ_TABLE_END}
88         },
89         .vddarm_mv = {
90                 0
91         },
92 };
93
94 struct cpufreq_conf sc8825_cpufreq_conf = {
95         .clk = NULL,
96         .regulator = NULL,
97         .freq_tbl = sc8825_cpufreq_table_data.freq_tbl,
98         .vddarm_mv = sc8825_cpufreq_table_data.vddarm_mv,
99 };
100
101 static void set_mcu_clk_freq(u32 mcu_freq)
102 {
103         u32 val, rate, arm_clk_div, gr_gen1;
104
105         rate = mcu_freq / MHz;
106         switch(1000 / rate)
107         {
108                 case 1:
109                         arm_clk_div = 0;
110                         break;
111                 case 2:
112                         arm_clk_div = 1;
113                         break;
114                 default:
115                         panic("set_mcu_clk_freq fault\n");
116                         break;
117         }
118         pr_debug("%s --- before, AHB_ARM_CLK: %08x, rate = %d, div = %d\n",
119                 __func__, __raw_readl(REG_AHB_ARM_CLK), rate, arm_clk_div);
120
121         gr_gen1 =  __raw_readl(GR_GEN1);
122         gr_gen1 |= BIT(9);
123         __raw_writel(gr_gen1, GR_GEN1);
124
125         val = __raw_readl(REG_AHB_ARM_CLK);
126         val &= 0xfffffff8;
127         val |= arm_clk_div;
128         __raw_writel(val, REG_AHB_ARM_CLK);
129
130         gr_gen1 &= ~BIT(9);
131         __raw_writel(gr_gen1, GR_GEN1);
132
133         pr_debug("%s --- after, AHB_ARM_CLK: %08x, rate = %d, div = %d\n",
134                 __func__, __raw_readl(REG_AHB_ARM_CLK), rate, arm_clk_div);
135
136         return;
137 }
138
139 static unsigned int get_mcu_clk_freq(void)
140 {
141         u32 mpll_refin, mpll_n, mpll_cfg = 0, rate, val;
142
143         mpll_cfg = __raw_readl(GR_MPLL_MN);
144
145         mpll_refin = (mpll_cfg >> GR_MPLL_REFIN_SHIFT) & GR_MPLL_REFIN_MASK;
146         switch(mpll_refin){
147                 case 0:
148                         mpll_refin = GR_MPLL_REFIN_2M;
149                         break;
150                 case 1:
151                 case 2:
152                         mpll_refin = GR_MPLL_REFIN_4M;
153                         break;
154                 case 3:
155                         mpll_refin = GR_MPLL_REFIN_13M;
156                         break;
157                 default:
158                         pr_err("%s mpll_refin: %d\n", __FUNCTION__, mpll_refin);
159         }
160         mpll_n = mpll_cfg & GR_MPLL_N_MASK;
161         rate = mpll_refin * mpll_n;
162
163         /*find div */
164         val = __raw_readl(REG_AHB_ARM_CLK) & 0x7;
165         val += 1;
166         return rate / val;
167 }
168 #endif
169
170 static struct cpufreq_table_data sc8830_cpufreq_table_data_cs = {
171         .freq_tbl = {
172                 {0, 1200000},
173                 {1, 1000000},
174                 {2, SHARK_TDPLL_FREQUENCY},
175                 {3, 600000},
176                 {4, CPUFREQ_TABLE_END},
177         },
178         .vddarm_mv = {
179                 1300000,
180                 1200000,
181                 1150000,
182                 1100000,
183                 1000000,
184         },
185 };
186
187 /*
188 for 7715 test
189 */
190 static struct cpufreq_table_data sc7715_cpufreq_table_data = {
191         .freq_tbl = {
192                 {0, 1000000},
193                 {1, SHARK_TDPLL_FREQUENCY},
194                 {2, 600000},
195                 {3, SHARK_TDPLL_FREQUENCY/2},
196                 {4, CPUFREQ_TABLE_END},
197         },
198         .vddarm_mv = {
199                 1200000,
200                 1150000,
201                 1100000,
202                 1100000,
203                 1000000,
204         },
205 };
206
207
208 static struct cpufreq_table_data sc8830_cpufreq_table_data_es = {
209         .freq_tbl = {
210                 {0, 1000000},
211                 {1, SHARK_TDPLL_FREQUENCY},
212                 {2, CPUFREQ_TABLE_END},
213         },
214         .vddarm_mv = {
215                 1250000,
216                 1200000,
217                 1000000,
218         },
219 };
220
221 static struct cpufreq_table_data sc8830t_cpufreq_table_data_es = {
222         .freq_tbl = {
223                 {0, 1300000},
224                 {1, 1200000},
225                 {2, 1000000},
226                 {3, SHARK_TDPLL_FREQUENCY},
227                 {4, CPUFREQ_TABLE_END},
228         },
229         .vddarm_mv = {
230                 1050000,
231                 1000000,
232                 900000,
233                 900000,
234                 900000,
235         },
236 };
237
238 static struct cpufreq_table_data sc8830t_cpufreq_table_data_es_1300 = {
239         .freq_tbl = {
240                 {0, 1300000},
241                 {1, 1200000},
242                 {2, 1000000},
243                 {3, SHARK_TDPLL_FREQUENCY},
244                 {4, CPUFREQ_TABLE_END},
245         },
246         .vddarm_mv = {
247                 1050000,
248                 1000000,
249                 900000,
250                 900000,
251                 900000,
252         },
253 };
254
255 static struct cpufreq_table_data sc9630_cpufreq_table_data = {
256         .freq_tbl = {
257                 {0, 1500000},
258                 {1, 1350000},
259                 {2, 900000},
260                 {3, 768000},
261                 {4, CPUFREQ_TABLE_END},
262         },
263         .vddarm_mv = {
264                 1100000,
265                 1000000,
266                 900000,
267                 900000,
268                 900000,
269         },
270 };
271
272 static struct cpufreq_table_data sc7720_cpufreq_table_data = {
273         .freq_tbl = {
274                 {0, 1200000},
275                 {1, 813000},
276                 {2, CPUFREQ_TABLE_END},
277         },
278         .vddarm_mv = {
279                 1200000,
280                 1050000,
281                 1050000,
282         },
283 };
284
285 static struct cpufreq_table_data sc9631l64_cpufreq_table_data_es = {
286         .freq_tbl = {
287                 {0, 1300000},
288                 {1, 1000000},
289                 {2, SHARK_TDPLL_FREQUENCY},
290                 {3, CPUFREQ_TABLE_END},
291         },
292         .vddarm_mv = {
293                 1000000,
294                 900000,
295                 900000,
296                 900000,
297         },
298 };
299 static struct cpufreq_table_data sc9820_cpufreq_table_data = {
300         .freq_tbl = {
301                 {0, 1250000},
302                 {1, 800000},
303                 {2, CPUFREQ_TABLE_END},
304         },
305         .vddarm_mv = {
306                 1200000,
307                 1050000,
308                 1050000,
309         },
310 };
311 struct cpufreq_conf sc8830_cpufreq_conf = {
312         .clk = NULL,
313         .mpllclk = NULL,
314         .tdpllclk = NULL,
315         .regulator = NULL,
316         .freq_tbl = NULL,
317         .vddarm_mv = NULL,
318 };
319
320 int cpufreq_table_thermal_update(unsigned int freq, unsigned int voltage)
321 {
322         struct cpufreq_frequency_table *freq_tbl;
323         unsigned int *vddarm;
324         int i;
325
326         if (NULL == sprd_cpufreq_conf)
327                 return -1;
328         freq_tbl = sprd_cpufreq_conf->freq_tbl;
329         vddarm = sprd_cpufreq_conf->vddarm_mv;
330         if (NULL == freq_tbl && NULL == vddarm)
331                 return -1;
332
333         for (i = 0; freq_tbl[i].frequency != CPUFREQ_TABLE_END; ++i) {
334                 if (freq_tbl[i].frequency == freq)
335                         goto done;
336         }
337         pr_err(KERN_ERR "%s cpufreq %dMHz isn't find!\n", __func__, freq);
338         return -1;
339 done:
340         printk(KERN_ERR "%s: %dMHz voltage is %dmV\n",
341                 __func__, freq, voltage);
342         if (vddarm[i] == voltage)
343                 return 0;
344
345         mutex_lock(&cpufreq_vddarm_lock);
346         vddarm[i] = voltage;
347         mutex_unlock(&cpufreq_vddarm_lock);
348
349         return 0;
350 }
351
352 static unsigned int sprd_raw_get_cpufreq(void)
353 {
354 #if defined(CONFIG_ARCH_SCX35)
355         return clk_get_rate(sprd_cpufreq_conf->clk) / 1000;
356 #elif defined(CONFIG_ARCH_SC8825)
357         return get_mcu_clk_freq() / 1000;
358 #endif
359 }
360
361 unsigned int last_freq = 0;
362 static void dump_axi_cpu(unsigned int freq)
363 {
364         u32 div, axi_freq;
365
366 #ifndef CONFIG_ARCH_SCX35L
367         div = sci_glb_read(REG_AP_AHB_CA7_CKG_CFG, -1UL);
368         div &= (0x7<<8);
369         div >>= 8;
370         axi_freq = freq / (div + 1);
371 #elif defined CONFIG_ARCH_SCX35LT8
372         div = sci_glb_read(REG_AP_AHB_CA7_CKG_DIV_CFG, -1UL);
373         div &= (0x7<<8);
374         div >>= 8;
375         axi_freq = freq / (div + 1);
376 #endif
377         printk("%s(%d): cpu_freq %d, div %d, axi_freq %d\n", __func__, __LINE__,
378                 freq, div, axi_freq);
379 }
380
381 static inline int get_axi_div(unsigned int freq)
382 {
383         if (freq % sprd_cpufreq_conf->max_axi_freq)
384                 return (freq / sprd_cpufreq_conf->max_axi_freq) + 1;
385         else
386                 return freq / sprd_cpufreq_conf->max_axi_freq;
387 }
388
389 static void cpufreq_adjust_axi_clk(unsigned int freq)
390 {
391         struct clk *clk_axi = NULL;
392         int div = 0, div_old = 0;
393         int need_adjust = 0;
394         char clk_name[50] = {0};
395
396         if (last_freq == 0) {
397                 last_freq = freq;
398                 need_adjust = 1;
399         }
400
401 #ifndef CONFIG_ARCH_SCX35L
402         strcpy(clk_name, "clk_ca7_axi");
403 #else
404         // for T8, in cpufreq-dt-sprd.c ?
405 #endif
406         if (!clk_name[0]) {
407                 last_freq = freq;
408                 return;
409         }
410
411         div = get_axi_div(freq);
412         div_old = get_axi_div(last_freq);
413         if (!need_adjust && (div != div_old))
414                 need_adjust = 1;
415
416         if (!need_adjust) {
417                 last_freq = freq;
418                 return;
419         }
420         last_freq = freq;
421
422         clk_axi = clk_get_sys(NULL, clk_name);
423         if (IS_ERR_OR_NULL(clk_axi)) {
424                 pr_err("%s(%d) err: cannot find clock %s\n", __func__, __LINE__, clk_name);
425                 return;
426         }
427
428         if (clk_set_rate(clk_axi, freq * 1000 / div))
429                 pr_err("%s(%d) err: clk_set_rate failed\n", __func__, __LINE__);
430
431         clk_put(clk_axi);
432         //dump_axi_cpu(freq);
433 }
434
435 static void cpufreq_set_clock(unsigned int freq)
436 {
437         int ret;
438
439         ret = clk_set_parent(sprd_cpufreq_conf->clk, sprd_cpufreq_conf->tdpllclk);
440         if (ret)
441                 pr_err("Failed to set cpu parent to tdpll\n");
442         if (freq == SHARK_TDPLL_FREQUENCY/2) {
443                 //ca7 clk div
444                 #ifndef CONFIG_ARCH_SCX35L
445                 sci_glb_set(REG_AP_AHB_CA7_CKG_CFG, BITS_CA7_MCU_CKG_DIV(1));
446                 #else
447                 #ifndef CONFIG_ARCH_SCX35LT8    //TODO
448                 sci_glb_set(REG_AP_AHB_CA7_CKG_DIV_CFG, BITS_CA7_MCU_CKG_DIV(1));
449                 #endif
450                 #endif
451         } else if (freq == SHARK_TDPLL_FREQUENCY) {
452                 #ifndef CONFIG_ARCH_SCX35L
453                 sci_glb_clr(REG_AP_AHB_CA7_CKG_CFG, BITS_CA7_MCU_CKG_DIV(1));
454                 #else
455                 #ifndef CONFIG_ARCH_SCX35LT8    //TODO
456                 sci_glb_clr(REG_AP_AHB_CA7_CKG_DIV_CFG, BITS_CA7_MCU_CKG_DIV(1));
457                 #endif
458                 #endif
459         } else {
460         /*
461                 if (clk_get_parent(sprd_cpufreq_conf->clk) != sprd_cpufreq_conf->tdpllclk) {
462                         ret = clk_set_parent(sprd_cpufreq_conf->clk, sprd_cpufreq_conf->tdpllclk);
463                         if (ret)
464                                 pr_err("Failed to set cpu parent to tdpll\n");
465                 }
466                 */
467                 if (!(sci_glb_read(REG_PMU_APB_MPLL_REL_CFG, -1) & BIT_MPLL_AP_SEL)) {
468                         sci_glb_set(REG_PMU_APB_MPLL_REL_CFG, BIT_MPLL_AP_SEL);
469                         udelay(500);
470                 }
471                 ret = clk_set_rate(sprd_cpufreq_conf->mpllclk, (freq * 1000));
472                 if (ret)
473                         pr_err("Failed to set mpll rate\n");
474                 ret = clk_set_parent(sprd_cpufreq_conf->clk, sprd_cpufreq_conf->mpllclk);
475                 if (ret)
476                         pr_err("Failed to set cpu parent to mpll\n");
477                 #ifndef CONFIG_ARCH_SCX35L
478                 sci_glb_clr(REG_AP_AHB_CA7_CKG_CFG, BITS_CA7_MCU_CKG_DIV(1));
479                 #else
480                 #ifndef CONFIG_ARCH_SCX35LT8    //TODO
481                 sci_glb_clr(REG_AP_AHB_CA7_CKG_DIV_CFG, BITS_CA7_MCU_CKG_DIV(1));
482                 #endif
483                 #endif
484         }
485
486         cpufreq_adjust_axi_clk(freq);
487 }
488 static void sprd_raw_set_cpufreq(int cpu, struct cpufreq_freqs *freq, int index)
489 {
490 #if defined(CONFIG_ARCH_SCX35)
491         int ret;
492
493 #define CPUFREQ_SET_VOLTAGE() \
494         do { \
495                 mutex_lock(&cpufreq_vddarm_lock);       \
496             ret = regulator_set_voltage(sprd_cpufreq_conf->regulator, \
497                         sprd_cpufreq_conf->vddarm_mv[index], \
498                         sprd_cpufreq_conf->vddarm_mv[index]); \
499                         mutex_unlock(&cpufreq_vddarm_lock);     \
500                 if (ret) \
501                         pr_err("Failed to set vdd to %d mv\n", \
502                                 sprd_cpufreq_conf->vddarm_mv[index]); \
503         } while (0)
504 #define CPUFREQ_SET_CLOCK() \
505         do { \
506                 if (freq->new == SHARK_TDPLL_FREQUENCY) { \
507                         ret = clk_set_parent(sprd_cpufreq_conf->clk, sprd_cpufreq_conf->tdpllclk); \
508                         if (ret) \
509                                 pr_err("Failed to set cpu parent to tdpll\n"); \
510                 } else { \
511                         if (clk_get_parent(sprd_cpufreq_conf->clk) != sprd_cpufreq_conf->tdpllclk) { \
512                                 ret = clk_set_parent(sprd_cpufreq_conf->clk, sprd_cpufreq_conf->tdpllclk); \
513                                 if (ret) \
514                                         pr_err("Failed to set cpu parent to tdpll\n"); \
515                         } \
516                         ret = clk_set_rate(sprd_cpufreq_conf->mpllclk, (freq->new * 1000)); \
517                         if (ret) \
518                                 pr_err("Failed to set mpll rate\n"); \
519                         ret = clk_set_parent(sprd_cpufreq_conf->clk, sprd_cpufreq_conf->mpllclk); \
520                         if (ret) \
521                                 pr_err("Failed to set cpu parent to mpll\n"); \
522                 } \
523         } while (0)
524         trace_cpu_frequency(freq->new, cpu);
525
526         if (freq->new >= sprd_raw_get_cpufreq()) {
527                 CPUFREQ_SET_VOLTAGE();
528                 cpufreq_set_clock(freq->new);
529         } else {
530                 cpufreq_set_clock(freq->new);
531                 CPUFREQ_SET_VOLTAGE();
532         }
533
534         pr_debug("%u --> %u, real=%u, index=%d\n",
535                 freq->old, freq->new, sprd_raw_get_cpufreq(), index);
536
537 #undef CPUFREQ_SET_VOLTAGE
538 #undef CPUFREQ_SET_CLOCK
539
540 #elif defined(CONFIG_ARCH_SC8825)
541         set_mcu_clk_freq(freq->new * 1000);
542 #endif
543         return;
544 }
545
546 static void sprd_real_set_cpufreq(struct cpufreq_policy *policy, unsigned int new_speed, int index)
547 {
548         mutex_lock(&freq_lock);
549
550         if (global_freqs.old == new_speed) {
551                 pr_debug("do nothing for cpu%u, new=old=%u\n",
552                                 policy->cpu, new_speed);
553                 mutex_unlock(&freq_lock);
554                 return;
555         }
556 #if 0 //TODO
557         pr_info("--xing-- set %u khz for cpu%u\n",
558                 new_speed, policy->cpu);
559 #endif
560         global_freqs.cpu = policy->cpu;
561         global_freqs.new = new_speed;
562
563         cpufreq_notify_transition(policy, &global_freqs, CPUFREQ_PRECHANGE);
564
565         sprd_raw_set_cpufreq(policy->cpu, &global_freqs, index);
566
567         cpufreq_notify_transition(policy, &global_freqs, CPUFREQ_POSTCHANGE);
568
569         global_freqs.old = global_freqs.new;
570
571         mutex_unlock(&freq_lock);
572         return;
573 }
574
575 static void sprd_find_real_index(unsigned int new_speed, int *index)
576 {
577         int i;
578         struct cpufreq_frequency_table *pfreq = sprd_cpufreq_conf->freq_tbl;
579
580         *index = pfreq[0].index;
581         for (i = 0; (pfreq[i].frequency != CPUFREQ_TABLE_END); i++) {
582                 if (new_speed == pfreq[i].frequency) {
583                         *index = pfreq[i].index;
584                         break;
585                 }
586         }
587         return;
588 }
589
590 static int sprd_update_cpu_speed(struct cpufreq_policy *policy,
591         unsigned int target_speed, int index)
592 {
593         int i, real_index = 0;
594         unsigned int new_speed = 0;
595
596         /*
597          * CONFIG_NR_CPUS cores are always in the same voltage, at the same
598          * frequency. But, cpu load is calculated individual in each cores,
599          * So we remeber the original target frequency and voltage of core0,
600          * and use the higher one
601          */
602
603         for_each_online_cpu(i) {
604                 new_speed = max(new_speed, percpu_target[i]);
605         }
606
607         if (new_speed > sprd_top_frequency)
608                 new_speed = sprd_top_frequency;
609
610         if (new_speed != sprd_cpufreq_conf->freq_tbl[index].frequency)
611                 sprd_find_real_index(new_speed, &real_index);
612         else
613                 real_index = index;
614         sprd_real_set_cpufreq(policy, new_speed, real_index);
615         return 0;
616 }
617
618 static int sprd_cpufreq_verify_speed(struct cpufreq_policy *policy)
619 {
620         if (policy->cpu > CONFIG_NR_CPUS) {
621                 pr_err("%s no such cpu id %d\n", __func__, policy->cpu);
622                 return -EINVAL;
623         }
624
625         return cpufreq_frequency_table_verify(policy, sprd_cpufreq_conf->freq_tbl);
626 }
627
628 unsigned int cpufreq_min_limit = ULONG_MAX;
629 unsigned int cpufreq_max_limit = 0;
630 unsigned int dvfs_score_select = 5;
631 unsigned int dvfs_unplug_select = 2;
632 unsigned int dvfs_plug_select = 0;
633 unsigned int dvfs_score_hi[4] = {0};
634 unsigned int dvfs_score_mid[4] = {0};
635 unsigned int dvfs_score_critical[4] = {0};
636 extern unsigned int percpu_load[4];
637 extern unsigned int cur_window_size[4];
638 extern unsigned int cur_window_index[4];
639 extern unsigned int ga_percpu_total_load[4][8];
640
641 static DEFINE_SPINLOCK(cpufreq_state_lock);
642
643 static int sprd_cpufreq_target(struct cpufreq_policy *policy,
644                        unsigned int target_freq,
645                        unsigned int relation)
646 {
647         int ret = -EFAULT;
648         int index;
649         unsigned int new_speed;
650         struct cpufreq_frequency_table *table;
651         int max_freq = cpufreq_max_limit;
652         int min_freq = cpufreq_min_limit;
653         int cur_freq = 0;
654         unsigned long irq_flags;
655
656         /* delay 30s to enable dvfs&dynamic-hotplug,
657          * except requirment from termal-cooling device
658          */
659         if(time_before(jiffies, boot_done)){
660                 return 0;
661         }
662
663         if((target_freq < min_freq) || (target_freq > max_freq))
664         {
665                 pr_err("invalid target_freq: %d min_freq %d max_freq %d\n", target_freq,min_freq,max_freq);
666                 return -EINVAL;
667         }
668
669         target_freq = max(1000000, target_freq);
670         target_freq = max((unsigned int)pm_qos_request(PM_QOS_CPU_FREQ_MIN), target_freq);
671         target_freq = min((unsigned int)pm_qos_request(PM_QOS_CPU_FREQ_MAX), target_freq);
672
673         table = cpufreq_frequency_get_table(policy->cpu);
674
675         if (cpufreq_frequency_table_target(policy, table,
676                                         target_freq, relation, &index)) {
677                 pr_err("invalid target_freq: %d\n", target_freq);
678                 return -EINVAL;
679         }
680
681         pr_debug("CPU_%d target %d relation %d (%d-%d) selected %d\n",
682                         policy->cpu, target_freq, relation,
683                         policy->min, policy->max, table[index].frequency);
684
685         new_speed = table[index].frequency;
686
687         percpu_target[policy->cpu] = new_speed;
688         pr_debug("%s cpu:%d new_speed:%u on cpu%d\n",
689                         __func__, policy->cpu, new_speed, smp_processor_id());
690
691         ret = sprd_update_cpu_speed(policy, new_speed, index);
692
693         return ret;
694
695 }
696
697 static unsigned int sprd_cpufreq_getspeed(unsigned int cpu)
698 {
699         if (cpu > CONFIG_NR_CPUS) {
700                 pr_err("%s no such cpu id %d\n", __func__, cpu);
701                 return -EINVAL;
702         }
703
704         return sprd_raw_get_cpufreq();
705 }
706
707 static void sprd_set_cpureq_limit(void)
708 {
709         int i;
710         struct cpufreq_frequency_table *tmp = sprd_cpufreq_conf->freq_tbl;
711         for (i = 0; (tmp[i].frequency != CPUFREQ_TABLE_END); i++) {
712                 cpufreq_min_limit = min(tmp[i].frequency, cpufreq_min_limit);
713                 cpufreq_max_limit = max(tmp[i].frequency, cpufreq_max_limit);
714         }
715         pr_info("--xing-- %s max=%u min=%u\n", __func__, cpufreq_max_limit, cpufreq_min_limit);
716 }
717
718 #if defined(CONFIG_ARCH_SCX35LT8)
719 #define AON_APB_CHIP_ID         REG_AON_APB_CHIP_ID0
720 #else
721 #define AON_APB_CHIP_ID         REG_AON_APB_CHIP_ID
722 #endif
723 static int sprd_freq_table_init(void)
724 {
725         /* we init freq table here depends on which chip being used */
726         if (soc_is_scx35_v0()) {
727                 pr_info("%s es_chip\n", __func__);
728                 sprd_cpufreq_conf->freq_tbl =
729                         sc8830_cpufreq_table_data_es.freq_tbl;
730                 sprd_cpufreq_conf->vddarm_mv =
731                         sc8830_cpufreq_table_data_es.vddarm_mv;
732         } else if (soc_is_scx35_v1()) {
733                 pr_info("%s cs_chip\n", __func__);
734                 sprd_cpufreq_conf->freq_tbl =
735                         sc8830_cpufreq_table_data_cs.freq_tbl;
736                 sprd_cpufreq_conf->vddarm_mv =
737                         sc8830_cpufreq_table_data_cs.vddarm_mv;
738         } else if (soc_is_sc7715()) {
739                 sprd_cpufreq_conf->freq_tbl =
740                         sc7715_cpufreq_table_data.freq_tbl;
741                 sprd_cpufreq_conf->vddarm_mv =
742                         sc7715_cpufreq_table_data.vddarm_mv;
743         } else if (soc_is_scx35g_v0() || soc_is_scx30g2_v0()) {
744                 sprd_cpufreq_conf->freq_tbl =
745                         sc8830t_cpufreq_table_data_es.freq_tbl;
746                 sprd_cpufreq_conf->vddarm_mv =
747                         sc8830t_cpufreq_table_data_es.vddarm_mv;
748                 sprd_cpufreq_conf->max_axi_freq = 500000;
749         } else if (soc_is_scx9630_v0()) {
750                 sprd_cpufreq_conf->freq_tbl =
751                         sc9630_cpufreq_table_data.freq_tbl;
752                 sprd_cpufreq_conf->vddarm_mv =
753                         sc9630_cpufreq_table_data.vddarm_mv;
754         } else if (soc_is_scx9820_v0()) {
755                 sprd_cpufreq_conf->freq_tbl =
756                         sc9820_cpufreq_table_data.freq_tbl;
757                 sprd_cpufreq_conf->vddarm_mv =
758                         sc9820_cpufreq_table_data.vddarm_mv;
759         } else if (soc_is_scx7720_v0()) {
760                 sprd_cpufreq_conf->freq_tbl =
761                         sc7720_cpufreq_table_data.freq_tbl;
762                 sprd_cpufreq_conf->vddarm_mv =
763                         sc7720_cpufreq_table_data.vddarm_mv;
764 #if defined (CONFIG_ARCH_SCX35LT8)      //TODO
765         } else if(__raw_readl(REG_AON_APB_CHIP_ID0) == 0x96310000){
766                  sprd_cpufreq_conf->freq_tbl =
767                                         sc9631l64_cpufreq_table_data_es.freq_tbl;
768                  sprd_cpufreq_conf->vddarm_mv =
769                                         sc9631l64_cpufreq_table_data_es.vddarm_mv;
770 #else
771         } else if (__raw_readl(AON_APB_CHIP_ID) == 0x96310000) {
772                 sprd_cpufreq_conf->freq_tbl =
773                         sc9631l64_cpufreq_table_data_es.freq_tbl;
774                 sprd_cpufreq_conf->vddarm_mv =
775                         sc9631l64_cpufreq_table_data_es.vddarm_mv;
776 #endif
777         } else {
778 #if defined(CONFIG_ARCH_SCX35LT8)
779                 pr_info("D-die chip id = 0x%08X\n", __raw_readl(REG_AON_APB_CHIP_ID0));
780 #endif
781                 pr_err("%s error chip id\n", __func__);
782                 return -EINVAL;
783         }
784         pr_info("sprd_freq_table_init \n");
785         sprd_set_cpureq_limit();
786         return 0;
787 }
788
789 static int sprd_cpufreq_init(struct cpufreq_policy *policy)
790 {
791         int ret;
792
793         cpufreq_frequency_table_cpuinfo(policy, sprd_cpufreq_conf->freq_tbl);
794         policy->cur = sprd_raw_get_cpufreq(); /* current cpu frequency: KHz*/
795          /*
796           * transition_latency 5us is enough now
797           * but sampling too often, unbalance and irregular on each online cpu
798           * so we set 500us here.
799           */
800         policy->cpuinfo.transition_latency = TRANSITION_LATENCY;
801         policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
802
803         cpufreq_frequency_table_get_attr(sprd_cpufreq_conf->freq_tbl, policy->cpu);
804
805         percpu_target[policy->cpu] = policy->cur;
806
807         ret = cpufreq_frequency_table_cpuinfo(policy, sprd_cpufreq_conf->freq_tbl);
808         if (ret != 0)
809                 pr_err("%s Failed to config freq table: %d\n", __func__, ret);
810
811
812         pr_info("%s policy->cpu=%d, policy->cur=%u, ret=%d\n",
813                 __func__, policy->cpu, policy->cur, ret);
814
815        cpumask_setall(policy->cpus);
816
817         return ret;
818 }
819
820 static int sprd_cpufreq_exit(struct cpufreq_policy *policy)
821 {
822         return 0;
823 }
824
825 static struct freq_attr *sprd_cpufreq_attr[] = {
826         &cpufreq_freq_attr_scaling_available_freqs,
827         NULL,
828 };
829
830 static struct cpufreq_driver sprd_cpufreq_driver = {
831         .verify         = sprd_cpufreq_verify_speed,
832         .target         = sprd_cpufreq_target,
833         .get            = sprd_cpufreq_getspeed,
834         .init           = sprd_cpufreq_init,
835         .exit           = sprd_cpufreq_exit,
836         .name           = "sprd",
837         .attr           = sprd_cpufreq_attr,
838 #if defined(CONFIG_ARCH_SCX35)
839         .flags          = CPUFREQ_SHARED
840 #endif
841 };
842
843 static ssize_t cpufreq_min_limit_show(struct device *dev, struct device_attribute *attr,char *buf)
844 {
845         memcpy(buf,&cpufreq_min_limit,sizeof(int));
846         return sizeof(int);
847 }
848
849 static ssize_t cpufreq_max_limit_show(struct device *dev, struct device_attribute *attr,char *buf)
850 {
851         memcpy(buf,&cpufreq_max_limit,sizeof(int));
852         return sizeof(int);
853 }
854
855 static ssize_t cpufreq_min_limit_debug_show(struct device *dev, struct device_attribute *attr,char *buf)
856 {
857         snprintf(buf,10,"%d\n",cpufreq_min_limit);
858         return strlen(buf) + 1;
859 }
860
861 static ssize_t cpufreq_max_limit_debug_show(struct device *dev, struct device_attribute *attr,char *buf)
862 {
863         snprintf(buf,10,"%d\n",cpufreq_max_limit);
864         return strlen(buf) + 1;
865 }
866
867 static ssize_t cpufreq_max_axi_freq_show(struct device *dev, struct device_attribute *attr,char *buf)
868 {
869         snprintf(buf, 10, "%d\n", sprd_cpufreq_conf->max_axi_freq);
870         return strlen(buf) + 1;
871 }
872
873 static ssize_t cpufreq_max_axi_freq_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count)
874 {
875         int value, ret;
876         int temp,max_freq = 0;
877         int i,j;
878
879         ret = strict_strtoul(buf, 16, (long unsigned int *)&value);
880         if (ret < 0)
881                 return ret;
882         i = 0;
883         do{
884                 temp = value & 0xf;
885                 for(j = 0; j < i; j++)
886                         temp = temp * 10;
887                 max_freq += temp;
888                 value = value >> 4;
889                 i++;
890         } while(value);
891
892         sprd_cpufreq_conf->max_axi_freq = max_freq;
893         return count;
894 }
895
896 static ssize_t cpufreq_min_limit_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count)
897 {
898         int ret;
899         int value;
900         unsigned long irq_flags;
901
902         ret = strict_strtoul(buf,16,(long unsigned int *)&value);
903
904         spin_lock_irqsave(&cpufreq_state_lock, irq_flags);
905         /*
906            for debug use
907            echo 0xabcde258 > /sys/power/cpufreq_min_limit means set the minimum limit to 600Mhz
908          */
909         if((value & 0xfffff000) == 0xabcde000)
910         {
911                 cpufreq_min_limit = value & 0x00000fff;
912                 cpufreq_min_limit *= 1000;
913                 printk(KERN_ERR"cpufreq_min_limit value %s %d\n",buf,cpufreq_min_limit);
914         }
915         else
916         {
917                 cpufreq_min_limit = *(int *)buf;
918         }
919         spin_unlock_irqrestore(&cpufreq_state_lock, irq_flags);
920         return count;
921 }
922
923 static ssize_t cpufreq_max_limit_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count)
924 {
925         int ret;
926         int value;
927         unsigned long irq_flags;
928
929         ret = strict_strtoul(buf,16,(long unsigned int *)&value);
930
931         spin_lock_irqsave(&cpufreq_state_lock, irq_flags);
932
933         /*
934            for debug use
935            echo 0xabcde4b0 > /sys/power/cpufreq_max_limit means set the maximum limit to 1200Mhz
936          */
937         if((value & 0xfffff000) == 0xabcde000)
938         {
939                 cpufreq_max_limit = value & 0x00000fff;
940                 cpufreq_max_limit *= 1000;
941                 printk(KERN_ERR"cpufreq_max_limit value %s %d\n",buf,cpufreq_max_limit);
942         }
943         else
944         {
945                 cpufreq_max_limit = *(int *)buf;
946         }
947         spin_unlock_irqrestore(&cpufreq_state_lock, irq_flags);
948
949         return count;
950 }
951
952 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_SPRDEMAND
953 static ssize_t dvfs_score_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count)
954 {
955         int ret;
956         int value;
957         unsigned long irq_flags;
958
959         ret = strict_strtoul(buf,16,(long unsigned int *)&value);
960
961         printk(KERN_ERR"dvfs_score_input %x\n",value);
962
963         dvfs_score_select = (value >> 24) & 0x0f;
964         if(dvfs_score_select < 4)
965         {
966                 dvfs_score_critical[dvfs_score_select] = (value >> 16) & 0xff;
967                 dvfs_score_hi[dvfs_score_select] = (value >> 8) & 0xff;
968                 dvfs_score_mid[dvfs_score_select] = value & 0xff;
969         }
970
971
972         return count;
973 }
974
975 static ssize_t dvfs_score_show(struct device *dev, struct device_attribute *attr,char *buf)
976 {
977         int ret = 0;
978
979         ret = snprintf(buf + ret,50,"dvfs_score_select %d\n",dvfs_score_select);
980         ret += snprintf(buf + ret,200,"dvfs_score_critical[1] = %d dvfs_score_hi[1] = %d dvfs_score_mid[1] = %d\n",dvfs_score_critical[1],dvfs_score_hi[1],dvfs_score_mid[1]);
981         ret += snprintf(buf + ret,200,"dvfs_score_critical[2] = %d dvfs_score_hi[2] = %d dvfs_score_mid[2] = %d\n",dvfs_score_critical[2],dvfs_score_hi[2],dvfs_score_mid[2]);
982         ret += snprintf(buf + ret,200,"dvfs_score_critical[3] = %d dvfs_score_hi[3] = %d dvfs_score_mid[3] = %d\n",dvfs_score_critical[3],dvfs_score_hi[3],dvfs_score_mid[3]);
983
984         ret += snprintf(buf + ret,200,"percpu_total_load[0] = %d,%d->%d\n",
985                 percpu_load[0],ga_percpu_total_load[0][(cur_window_index[0] - 1 + 10) % 10],ga_percpu_total_load[0][cur_window_index[0]]);
986         ret += snprintf(buf + ret,200,"percpu_total_load[1] = %d,%d->%d\n",
987                 percpu_load[1],ga_percpu_total_load[1][(cur_window_index[1] - 1 + 10) % 10],ga_percpu_total_load[1][cur_window_index[1]]);
988         ret += snprintf(buf + ret,200,"percpu_total_load[2] = %d,%d->%d\n",
989                 percpu_load[2],ga_percpu_total_load[2][(cur_window_index[2] - 1 + 10) % 10],ga_percpu_total_load[2][cur_window_index[2]]);
990         ret += snprintf(buf + ret,200,"percpu_total_load[3] = %d,%d->%d\n",
991                 percpu_load[3],ga_percpu_total_load[3][(cur_window_index[3] - 1 + 10) % 10],ga_percpu_total_load[3][cur_window_index[3]]);
992
993         return strlen(buf) + 1;
994 }
995
996 static ssize_t dvfs_unplug_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count)
997 {
998         int ret;
999         int value;
1000         unsigned long irq_flags;
1001
1002         ret = strict_strtoul(buf,16,(long unsigned int *)&value);
1003
1004         printk(KERN_ERR"dvfs_score_input %x\n",value);
1005
1006         dvfs_unplug_select = (value >> 24) & 0x0f;
1007         if(dvfs_unplug_select > 7)
1008         {
1009                 cur_window_size[0]= (value >> 8) & 0xff;
1010                 cur_window_size[1]= (value >> 8) & 0xff;
1011                 cur_window_size[2]= (value >> 8) & 0xff;
1012                 cur_window_size[3]= (value >> 8) & 0xff;
1013         }
1014         return count;
1015 }
1016
1017 static ssize_t dvfs_unplug_show(struct device *dev, struct device_attribute *attr,char *buf)
1018 {
1019         int ret = 0;
1020
1021         ret = snprintf(buf + ret,50,"dvfs_unplug_select %d\n",dvfs_unplug_select);
1022         ret += snprintf(buf + ret,100,"cur_window_size[0] = %d\n",cur_window_size[0]);
1023         ret += snprintf(buf + ret,100,"cur_window_size[1] = %d\n",cur_window_size[1]);
1024         ret += snprintf(buf + ret,100,"cur_window_size[2] = %d\n",cur_window_size[2]);
1025         ret += snprintf(buf + ret,100,"cur_window_size[3] = %d\n",cur_window_size[3]);
1026
1027         return strlen(buf) + 1;
1028 }
1029
1030
1031 static ssize_t dvfs_plug_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count)
1032 {
1033         int ret;
1034         int value;
1035         unsigned long irq_flags;
1036
1037         ret = strict_strtoul(buf,16,(long unsigned int *)&value);
1038
1039         printk(KERN_ERR"dvfs_plug_select %x\n",value);
1040
1041         dvfs_plug_select = (value ) & 0x0f;
1042         return count;
1043 }
1044
1045
1046 static ssize_t dvfs_plug_show(struct device *dev, struct device_attribute *attr,char *buf)
1047 {
1048         int ret = 0;
1049
1050         ret = snprintf(buf + ret,50,"dvfs_plug_select %d\n",dvfs_plug_select);
1051
1052         return strlen(buf) + 1;
1053 }
1054 #endif
1055
1056 static ssize_t cpufreq_table_show(struct device *dev, struct device_attribute *attr,char *buf)
1057 {
1058         memcpy(buf,sprd_cpufreq_conf->freq_tbl,sizeof(* sprd_cpufreq_conf->freq_tbl));
1059         return sizeof(* sprd_cpufreq_conf->freq_tbl);
1060 }
1061
1062 static ssize_t dvfs_prop_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count)
1063 {
1064         int ret;
1065         int value;
1066         unsigned long irq_flags;
1067
1068         printk(KERN_ERR"dvfs_status %s\n",buf);
1069         ret = strict_strtoul(buf,16,(long unsigned int *)&value);
1070
1071         printk(KERN_ERR"dvfs_plug_select %x\n",value);
1072
1073         dvfs_plug_select = (value ) & 0x0f;
1074         return count;
1075 }
1076
1077 static ssize_t dvfs_prop_show(struct device *dev, struct device_attribute *attr,char *buf)
1078 {
1079         int ret = 0;
1080
1081         ret = snprintf(buf + ret,50,"dvfs_plug_select %d\n",dvfs_plug_select);
1082
1083         return strlen(buf) + 1;
1084 }
1085
1086 #ifdef CONFIG_SPRD_AVS_DEBUG
1087 extern unsigned int g_avs_log_flag;
1088
1089 static ssize_t avs_log_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count)
1090 {
1091         int ret;
1092         int value;
1093         unsigned long irq_flags;
1094
1095         printk(KERN_ERR"g_avs_log_flag %s\n",buf);
1096         ret = strict_strtoul(buf,16,(long unsigned int *)&value);
1097
1098         printk(KERN_ERR"g_avs_log_flag %x\n",value);
1099
1100         g_avs_log_flag = (value ) & 0x0f;
1101         return count;
1102 }
1103
1104 static ssize_t avs_log_show(struct device *dev, struct device_attribute *attr,char *buf)
1105 {
1106         int ret = 0;
1107
1108         ret = snprintf(buf + ret,50,"g_avs_log_flag %d\n",g_avs_log_flag);
1109
1110         return strlen(buf) + 1;
1111 }
1112 #endif
1113 static DEVICE_ATTR(cpufreq_min_limit, 0660, cpufreq_min_limit_show, cpufreq_min_limit_store);
1114 static DEVICE_ATTR(cpufreq_max_limit, 0660, cpufreq_max_limit_show, cpufreq_max_limit_store);
1115 static DEVICE_ATTR(cpufreq_min_limit_debug, 0440, cpufreq_min_limit_debug_show, NULL);
1116 static DEVICE_ATTR(cpufreq_max_limit_debug, 0440, cpufreq_max_limit_debug_show, NULL);
1117 static DEVICE_ATTR(cpufreq_table, 0440, cpufreq_table_show, NULL);
1118 static DEVICE_ATTR(cpufreq_max_axi_freq, 0660, cpufreq_max_axi_freq_show, cpufreq_max_axi_freq_store);
1119
1120 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_SPRDEMAND
1121 static DEVICE_ATTR(dvfs_score, 0660, dvfs_score_show, dvfs_score_store);
1122 static DEVICE_ATTR(dvfs_unplug, 0660, dvfs_unplug_show, dvfs_unplug_store);
1123 static DEVICE_ATTR(dvfs_plug, 0660, dvfs_plug_show, dvfs_plug_store);
1124 #endif
1125 static DEVICE_ATTR(dvfs_prop, 0660, dvfs_prop_show, dvfs_prop_store);
1126
1127 #ifdef CONFIG_SPRD_AVS_DEBUG
1128 static DEVICE_ATTR(avs_log, 0660, avs_log_show, avs_log_store);
1129 #endif
1130 static struct attribute *g[] = {
1131         &dev_attr_cpufreq_min_limit.attr,
1132         &dev_attr_cpufreq_max_limit.attr,
1133         &dev_attr_cpufreq_min_limit_debug.attr,
1134         &dev_attr_cpufreq_max_limit_debug.attr,
1135         &dev_attr_cpufreq_table.attr,
1136         &dev_attr_cpufreq_max_axi_freq.attr,
1137 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_SPRDEMAND
1138         &dev_attr_dvfs_score.attr,
1139         &dev_attr_dvfs_unplug.attr,
1140         &dev_attr_dvfs_plug.attr,
1141 #endif
1142         &dev_attr_dvfs_prop.attr,
1143 #ifdef CONFIG_SPRD_AVS_DEBUG
1144         &dev_attr_avs_log.attr,
1145 #endif
1146         NULL,
1147 };
1148
1149 static struct attribute_group attr_group = {
1150         .attrs = g,
1151 };
1152
1153 static int sprd_cpufreq_policy_notifier(
1154         struct notifier_block *nb, unsigned long event, void *data)
1155 {
1156         return NOTIFY_OK;
1157 }
1158
1159 static struct notifier_block sprd_cpufreq_policy_nb = {
1160         .notifier_call = sprd_cpufreq_policy_notifier,
1161 };
1162
1163
1164 static int sprd_cpufreq_min_qos_handler(struct notifier_block *b, unsigned long val, void *v)
1165 {
1166         int ret;
1167         struct cpufreq_policy *policy;
1168
1169         policy = cpufreq_cpu_get(0);
1170         if (!policy)
1171                 goto fail;
1172
1173         if (policy->cur >= val) {
1174                 cpufreq_cpu_put(policy);
1175                 goto success;
1176         }
1177
1178         ret = __cpufreq_driver_target(policy, val, CPUFREQ_RELATION_L);
1179
1180         cpufreq_cpu_put(policy);
1181
1182         if (ret < 0)
1183             goto fail;
1184
1185 success:
1186         return NOTIFY_OK;
1187 fail:
1188         return NOTIFY_BAD;
1189 }
1190
1191 static int sprd_cpufreq_max_qos_handler(struct notifier_block *b, unsigned long val, void *v)
1192 {
1193         int ret;
1194         struct cpufreq_policy *policy;
1195
1196         policy = cpufreq_cpu_get(0);
1197         if (!policy)
1198                         goto fail;
1199
1200         if (policy->cur <= val) {
1201                 cpufreq_cpu_put(policy);
1202                 goto success;
1203         }
1204
1205         ret = __cpufreq_driver_target(policy, val, CPUFREQ_RELATION_H);
1206
1207         cpufreq_cpu_put(policy);
1208
1209         if (ret < 0)
1210             goto fail;
1211
1212 success:
1213         return NOTIFY_OK;
1214 fail:
1215         return NOTIFY_BAD;
1216
1217 }
1218
1219 static struct notifier_block sprd_cpufreq_min_qos_notifier = {
1220         .notifier_call = sprd_cpufreq_min_qos_handler,
1221 };
1222
1223 static struct notifier_block sprd_cpufreq_max_qos_notifier = {
1224         .notifier_call = sprd_cpufreq_max_qos_handler,
1225 };
1226
1227 static int __init sprd_cpufreq_modinit(void)
1228 {
1229         int ret;
1230 #if defined(CONFIG_SPRD_CPUFREQ_DT_DRIVER)
1231         struct platform_device_info devinfo = { .name = "cpufreq-dt-sprd", };
1232
1233         platform_device_register_full(&devinfo);
1234
1235         return;
1236 #endif
1237
1238 #if defined(CONFIG_ARCH_SCX35)
1239         sprd_cpufreq_conf = &sc8830_cpufreq_conf;
1240 #elif defined(CONFIG_ARCH_SC8825)
1241         sprd_cpufreq_conf = &sc8825_cpufreq_conf;
1242 #endif
1243
1244 #if defined(CONFIG_ARCH_SCX35)
1245         ret = sprd_freq_table_init();
1246         if (ret)
1247                 return ret;
1248
1249         sprd_top_frequency = sprd_cpufreq_conf->freq_tbl[0].frequency;
1250         /* TODO:need verify for the initialization of limited max freq */
1251
1252         sprd_cpufreq_conf->clk = clk_get_sys(NULL, "clk_mcu");
1253         if (IS_ERR(sprd_cpufreq_conf->clk))
1254                 return PTR_ERR(sprd_cpufreq_conf->clk);
1255
1256         sprd_cpufreq_conf->mpllclk = clk_get_sys(NULL, "clk_mpll");
1257         if (IS_ERR(sprd_cpufreq_conf->mpllclk))
1258                 return PTR_ERR(sprd_cpufreq_conf->mpllclk);
1259
1260 #if !defined(CONFIG_ARCH_SCX35L) && !defined(CONFIG_ARCH_SCX20)
1261         sprd_cpufreq_conf->tdpllclk = clk_get_sys(NULL, "clk_tdpll");
1262         if (IS_ERR(sprd_cpufreq_conf->tdpllclk))
1263                 return PTR_ERR(sprd_cpufreq_conf->tdpllclk);
1264 #else
1265 //      sprd_cpufreq_conf->tdpllclk = clk_get_sys(NULL, "clk_twpll");
1266         sprd_cpufreq_conf->tdpllclk = clk_get_sys(NULL, "clk_768m");
1267         if (IS_ERR(sprd_cpufreq_conf->tdpllclk))
1268                 return PTR_ERR(sprd_cpufreq_conf->tdpllclk);
1269 #endif
1270         mutex_init(&cpufreq_vddarm_lock);
1271
1272         sprd_cpufreq_conf->regulator = regulator_get(NULL, "vddarm");
1273
1274         if (IS_ERR(sprd_cpufreq_conf->regulator))
1275                 return PTR_ERR(sprd_cpufreq_conf->regulator);
1276
1277         /* set max voltage first */
1278         /*
1279         regulator_set_voltage(sprd_cpufreq_conf->regulator,
1280                 sprd_cpufreq_conf->vddarm_mv[0],
1281                 sprd_cpufreq_conf->vddarm_mv[0]);
1282         */
1283         clk_set_parent(sprd_cpufreq_conf->clk, sprd_cpufreq_conf->tdpllclk);
1284         /*
1285         * clk_set_rate(sprd_cpufreq_conf->mpllclk, (sprd_top_frequency * 1000));
1286         */
1287         clk_set_parent(sprd_cpufreq_conf->clk, sprd_cpufreq_conf->mpllclk);
1288         global_freqs.old = sprd_raw_get_cpufreq();
1289
1290 #endif
1291
1292         boot_done = jiffies + DVFS_BOOT_TIME;
1293         ret = cpufreq_register_notifier(
1294                 &sprd_cpufreq_policy_nb, CPUFREQ_POLICY_NOTIFIER);
1295         if (ret)
1296                 return ret;
1297
1298         ret = cpufreq_register_driver(&sprd_cpufreq_driver);
1299
1300         pm_qos_add_notifier(PM_QOS_CPU_FREQ_MIN, &sprd_cpufreq_min_qos_notifier);
1301         pm_qos_add_notifier(PM_QOS_CPU_FREQ_MAX, &sprd_cpufreq_max_qos_notifier);
1302
1303         /* remove duplicated sysfs files */
1304         //ret = sysfs_create_group(power_kobj, &attr_group);
1305         return ret;
1306 }
1307
1308 static void __exit sprd_cpufreq_modexit(void)
1309 {
1310 #if defined(CONFIG_ARCH_SCX35)
1311         if (!IS_ERR_OR_NULL(sprd_cpufreq_conf->regulator))
1312                 regulator_put(sprd_cpufreq_conf->regulator);
1313 #endif
1314         cpufreq_unregister_driver(&sprd_cpufreq_driver);
1315         cpufreq_unregister_notifier(
1316                 &sprd_cpufreq_policy_nb, CPUFREQ_POLICY_NOTIFIER);
1317         return;
1318 }
1319
1320 module_init(sprd_cpufreq_modinit);
1321 module_exit(sprd_cpufreq_modexit);
1322
1323 MODULE_DESCRIPTION("cpufreq driver for Spreadtrum");
1324 MODULE_LICENSE("GPL");