1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
10 #include <linux/err.h>
11 #include <linux/kernel.h>
12 #include <linux/sizes.h>
13 #include <dm/pinctrl.h>
15 #include "pinctrl-uniphier.h"
17 #define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
18 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
19 #define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x1800
20 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900
21 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980
22 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
23 #define UNIPHIER_PINCTRL_IECTRL 0x1d00
25 static const char *uniphier_pinctrl_dummy_name = "_dummy";
27 static int uniphier_pinctrl_get_pins_count(struct udevice *dev)
29 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
30 const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
31 int pins_count = priv->socdata->pins_count;
34 * We do not list all pins in the pin table to save memory footprint.
35 * Report the max pin number + 1 to fake the framework.
37 return pins[pins_count - 1].number + 1;
40 static const char *uniphier_pinctrl_get_pin_name(struct udevice *dev,
41 unsigned int selector)
43 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
44 const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
45 int pins_count = priv->socdata->pins_count;
48 for (i = 0; i < pins_count; i++)
49 if (pins[i].number == selector)
52 return uniphier_pinctrl_dummy_name;
55 static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
57 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
59 return priv->socdata->groups_count;
62 static const char *uniphier_pinctrl_get_group_name(struct udevice *dev,
65 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
67 if (!priv->socdata->groups[selector].name)
68 return uniphier_pinctrl_dummy_name;
70 return priv->socdata->groups[selector].name;
73 static int uniphier_pinmux_get_functions_count(struct udevice *dev)
75 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
77 return priv->socdata->functions_count;
80 static const char *uniphier_pinmux_get_function_name(struct udevice *dev,
83 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
85 if (!priv->socdata->functions[selector])
86 return uniphier_pinctrl_dummy_name;
88 return priv->socdata->functions[selector];
91 static int uniphier_pinconf_input_enable_perpin(struct udevice *dev,
92 unsigned int pin, int enable)
94 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
98 reg = UNIPHIER_PINCTRL_IECTRL + pin / 32 * 4;
101 tmp = readl(priv->base + reg);
106 writel(tmp, priv->base + reg);
111 static int uniphier_pinconf_input_enable_legacy(struct udevice *dev,
112 unsigned int pin, int enable)
114 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
117 * Multiple pins share one input enable, per-pin disabling is
123 /* Set all bits instead of having a bunch of pin data */
124 writel(U32_MAX, priv->base + UNIPHIER_PINCTRL_IECTRL);
129 static int uniphier_pinconf_input_enable(struct udevice *dev,
130 unsigned int pin, int enable)
132 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
134 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
135 return uniphier_pinconf_input_enable_perpin(dev, pin, enable);
137 return uniphier_pinconf_input_enable_legacy(dev, pin, enable);
140 #if CONFIG_IS_ENABLED(PINCONF)
142 static const struct pinconf_param uniphier_pinconf_params[] = {
143 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
144 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
145 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
146 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
147 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
148 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
149 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
152 static const struct uniphier_pinctrl_pin *
153 uniphier_pinctrl_pin_get(struct uniphier_pinctrl_priv *priv, unsigned int pin)
155 const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
156 int pins_count = priv->socdata->pins_count;
159 for (i = 0; i < pins_count; i++)
160 if (pins[i].number == pin)
166 static int uniphier_pinconf_bias_set(struct udevice *dev, unsigned int pin,
167 unsigned int param, unsigned int arg)
169 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
170 unsigned int enable = 1;
174 if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE))
178 case PIN_CONFIG_BIAS_DISABLE:
181 case PIN_CONFIG_BIAS_PULL_UP:
182 case PIN_CONFIG_BIAS_PULL_DOWN:
183 if (arg == 0) /* total bias is not supported */
186 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
187 if (arg == 0) /* configuration ignored */
193 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pin / 32 * 4;
194 mask = BIT(pin % 32);
196 tmp = readl(priv->base + reg);
201 writel(tmp, priv->base + reg);
206 static const unsigned int uniphier_pinconf_drv_strengths_1bit[] = {
210 static const unsigned int uniphier_pinconf_drv_strengths_2bit[] = {
214 static const unsigned int uniphier_pinconf_drv_strengths_3bit[] = {
215 4, 5, 7, 9, 11, 12, 14, 16,
218 static int uniphier_pinconf_drive_set(struct udevice *dev, unsigned int pin,
219 unsigned int strength)
221 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
222 const struct uniphier_pinctrl_pin *desc;
223 const unsigned int *strengths;
224 unsigned int base, stride, width, drvctrl, reg, shift;
227 desc = uniphier_pinctrl_pin_get(priv, pin);
231 switch (uniphier_pin_get_drv_type(desc->data)) {
232 case UNIPHIER_PIN_DRV_1BIT:
233 strengths = uniphier_pinconf_drv_strengths_1bit;
234 base = UNIPHIER_PINCTRL_DRVCTRL_BASE;
238 case UNIPHIER_PIN_DRV_2BIT:
239 strengths = uniphier_pinconf_drv_strengths_2bit;
240 base = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
244 case UNIPHIER_PIN_DRV_3BIT:
245 strengths = uniphier_pinconf_drv_strengths_3bit;
246 base = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
251 /* drive strength control is not supported for this pin */
255 drvctrl = uniphier_pin_get_drvctrl(desc->data);
258 reg = base + drvctrl / 32 * 4;
259 shift = drvctrl % 32;
260 mask = (1U << width) - 1;
262 for (val = 0; val <= mask; val++) {
263 if (strengths[val] > strength)
268 dev_err(dev, "unsupported drive strength %u mA for pin %s\n",
269 strength, desc->name);
278 tmp = readl(priv->base + reg);
279 tmp &= ~(mask << shift);
280 tmp |= (mask & val) << shift;
281 writel(tmp, priv->base + reg);
286 static int uniphier_pinconf_set(struct udevice *dev, unsigned int pin,
287 unsigned int param, unsigned int arg)
292 case PIN_CONFIG_BIAS_DISABLE:
293 case PIN_CONFIG_BIAS_PULL_UP:
294 case PIN_CONFIG_BIAS_PULL_DOWN:
295 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
296 ret = uniphier_pinconf_bias_set(dev, pin, param, arg);
298 case PIN_CONFIG_DRIVE_STRENGTH:
299 ret = uniphier_pinconf_drive_set(dev, pin, arg);
301 case PIN_CONFIG_INPUT_ENABLE:
302 ret = uniphier_pinconf_input_enable(dev, pin, arg);
305 dev_err(dev, "unsupported configuration parameter %u\n", param);
312 static int uniphier_pinconf_group_set(struct udevice *dev,
313 unsigned int group_selector,
314 unsigned int param, unsigned int arg)
316 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
317 const struct uniphier_pinctrl_group *grp =
318 &priv->socdata->groups[group_selector];
321 for (i = 0; i < grp->num_pins; i++) {
322 ret = uniphier_pinconf_set(dev, grp->pins[i], param, arg);
330 #endif /* CONFIG_IS_ENABLED(PINCONF) */
332 static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
335 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
336 unsigned reg, reg_end, shift, mask;
337 unsigned mux_bits = 8;
338 unsigned reg_stride = 4;
339 bool load_pinctrl = false;
342 /* some pins need input-enabling */
343 uniphier_pinconf_input_enable(dev, pin, 1);
346 return; /* dedicated pin; nothing to do for pin-mux */
348 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
351 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
354 * Normal 4 * n shift+3:shift
355 * Debug 4 * n shift+7:shift+4
362 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
363 reg_end = reg + reg_stride;
364 shift = pin * mux_bits % 32;
365 mask = (1U << mux_bits) - 1;
368 * If reg_stride is greater than 4, the MSB of each pinsel shall be
369 * stored in the offset+4.
371 for (; reg < reg_end; reg += 4) {
372 tmp = readl(priv->base + reg);
373 tmp &= ~(mask << shift);
374 tmp |= (mask & muxval) << shift;
375 writel(tmp, priv->base + reg);
381 writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
384 static int uniphier_pinmux_group_set(struct udevice *dev,
385 unsigned group_selector,
386 unsigned func_selector)
388 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
389 const struct uniphier_pinctrl_group *grp =
390 &priv->socdata->groups[group_selector];
393 for (i = 0; i < grp->num_pins; i++)
394 uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]);
399 const struct pinctrl_ops uniphier_pinctrl_ops = {
400 .get_pins_count = uniphier_pinctrl_get_pins_count,
401 .get_pin_name = uniphier_pinctrl_get_pin_name,
402 .get_groups_count = uniphier_pinctrl_get_groups_count,
403 .get_group_name = uniphier_pinctrl_get_group_name,
404 .get_functions_count = uniphier_pinmux_get_functions_count,
405 .get_function_name = uniphier_pinmux_get_function_name,
406 .pinmux_group_set = uniphier_pinmux_group_set,
407 #if CONFIG_IS_ENABLED(PINCONF)
408 .pinconf_num_params = ARRAY_SIZE(uniphier_pinconf_params),
409 .pinconf_params = uniphier_pinconf_params,
410 .pinconf_set = uniphier_pinconf_set,
411 .pinconf_group_set = uniphier_pinconf_group_set,
413 .set_state = pinctrl_generic_set_state,
416 int uniphier_pinctrl_probe(struct udevice *dev,
417 struct uniphier_pinctrl_socdata *socdata)
419 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
422 addr = devfdt_get_addr(dev->parent);
423 if (addr == FDT_ADDR_T_NONE)
426 priv->base = devm_ioremap(dev, addr, SZ_4K);
430 priv->socdata = socdata;