1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
9 #include <dm/device_compat.h>
10 #include <linux/bitops.h>
11 #include <linux/bug.h>
13 #include <linux/err.h>
14 #include <linux/kernel.h>
15 #include <linux/sizes.h>
16 #include <dm/pinctrl.h>
18 #include "pinctrl-uniphier.h"
20 #define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
21 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
22 #define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x1800
23 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900
24 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980
25 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
26 #define UNIPHIER_PINCTRL_IECTRL 0x1d00
28 static const char *uniphier_pinctrl_dummy_name = "_dummy";
30 static int uniphier_pinctrl_get_pins_count(struct udevice *dev)
32 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
33 const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
34 int pins_count = priv->socdata->pins_count;
37 * We do not list all pins in the pin table to save memory footprint.
38 * Report the max pin number + 1 to fake the framework.
40 return pins[pins_count - 1].number + 1;
43 static const char *uniphier_pinctrl_get_pin_name(struct udevice *dev,
44 unsigned int selector)
46 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
47 const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
48 int pins_count = priv->socdata->pins_count;
51 for (i = 0; i < pins_count; i++)
52 if (pins[i].number == selector)
55 return uniphier_pinctrl_dummy_name;
58 static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
60 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
62 return priv->socdata->groups_count;
65 static const char *uniphier_pinctrl_get_group_name(struct udevice *dev,
68 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
70 if (!priv->socdata->groups[selector].name)
71 return uniphier_pinctrl_dummy_name;
73 return priv->socdata->groups[selector].name;
76 static int uniphier_pinmux_get_functions_count(struct udevice *dev)
78 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
80 return priv->socdata->functions_count;
83 static const char *uniphier_pinmux_get_function_name(struct udevice *dev,
86 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
88 if (!priv->socdata->functions[selector])
89 return uniphier_pinctrl_dummy_name;
91 return priv->socdata->functions[selector];
94 static int uniphier_pinconf_input_enable_perpin(struct udevice *dev,
95 unsigned int pin, int enable)
97 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
101 reg = UNIPHIER_PINCTRL_IECTRL + pin / 32 * 4;
102 mask = BIT(pin % 32);
104 tmp = readl(priv->base + reg);
109 writel(tmp, priv->base + reg);
114 static int uniphier_pinconf_input_enable_legacy(struct udevice *dev,
115 unsigned int pin, int enable)
117 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
120 * Multiple pins share one input enable, per-pin disabling is
126 /* Set all bits instead of having a bunch of pin data */
127 writel(U32_MAX, priv->base + UNIPHIER_PINCTRL_IECTRL);
132 static int uniphier_pinconf_input_enable(struct udevice *dev,
133 unsigned int pin, int enable)
135 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
137 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
138 return uniphier_pinconf_input_enable_perpin(dev, pin, enable);
140 return uniphier_pinconf_input_enable_legacy(dev, pin, enable);
143 #if CONFIG_IS_ENABLED(PINCONF)
145 static const struct pinconf_param uniphier_pinconf_params[] = {
146 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
147 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
148 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
149 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
150 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
151 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
152 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
155 static const struct uniphier_pinctrl_pin *
156 uniphier_pinctrl_pin_get(struct uniphier_pinctrl_priv *priv, unsigned int pin)
158 const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
159 int pins_count = priv->socdata->pins_count;
162 for (i = 0; i < pins_count; i++)
163 if (pins[i].number == pin)
169 static int uniphier_pinconf_bias_set(struct udevice *dev, unsigned int pin,
170 unsigned int param, unsigned int arg)
172 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
173 unsigned int enable = 1;
177 if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE))
181 case PIN_CONFIG_BIAS_DISABLE:
184 case PIN_CONFIG_BIAS_PULL_UP:
185 case PIN_CONFIG_BIAS_PULL_DOWN:
186 if (arg == 0) /* total bias is not supported */
189 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
190 if (arg == 0) /* configuration ignored */
196 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pin / 32 * 4;
197 mask = BIT(pin % 32);
199 tmp = readl(priv->base + reg);
204 writel(tmp, priv->base + reg);
209 static const unsigned int uniphier_pinconf_drv_strengths_1bit[] = {
213 static const unsigned int uniphier_pinconf_drv_strengths_2bit[] = {
217 static const unsigned int uniphier_pinconf_drv_strengths_3bit[] = {
218 4, 5, 7, 9, 11, 12, 14, 16,
221 static int uniphier_pinconf_drive_set(struct udevice *dev, unsigned int pin,
222 unsigned int strength)
224 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
225 const struct uniphier_pinctrl_pin *desc;
226 const unsigned int *strengths;
227 unsigned int base, stride, width, drvctrl, reg, shift;
230 desc = uniphier_pinctrl_pin_get(priv, pin);
234 switch (uniphier_pin_get_drv_type(desc->data)) {
235 case UNIPHIER_PIN_DRV_1BIT:
236 strengths = uniphier_pinconf_drv_strengths_1bit;
237 base = UNIPHIER_PINCTRL_DRVCTRL_BASE;
241 case UNIPHIER_PIN_DRV_2BIT:
242 strengths = uniphier_pinconf_drv_strengths_2bit;
243 base = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
247 case UNIPHIER_PIN_DRV_3BIT:
248 strengths = uniphier_pinconf_drv_strengths_3bit;
249 base = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
254 /* drive strength control is not supported for this pin */
258 drvctrl = uniphier_pin_get_drvctrl(desc->data);
261 reg = base + drvctrl / 32 * 4;
262 shift = drvctrl % 32;
263 mask = (1U << width) - 1;
265 for (val = 0; val <= mask; val++) {
266 if (strengths[val] > strength)
271 dev_err(dev, "unsupported drive strength %u mA for pin %s\n",
272 strength, desc->name);
281 tmp = readl(priv->base + reg);
282 tmp &= ~(mask << shift);
283 tmp |= (mask & val) << shift;
284 writel(tmp, priv->base + reg);
289 static int uniphier_pinconf_set(struct udevice *dev, unsigned int pin,
290 unsigned int param, unsigned int arg)
295 case PIN_CONFIG_BIAS_DISABLE:
296 case PIN_CONFIG_BIAS_PULL_UP:
297 case PIN_CONFIG_BIAS_PULL_DOWN:
298 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
299 ret = uniphier_pinconf_bias_set(dev, pin, param, arg);
301 case PIN_CONFIG_DRIVE_STRENGTH:
302 ret = uniphier_pinconf_drive_set(dev, pin, arg);
304 case PIN_CONFIG_INPUT_ENABLE:
305 ret = uniphier_pinconf_input_enable(dev, pin, arg);
308 dev_err(dev, "unsupported configuration parameter %u\n", param);
315 static int uniphier_pinconf_group_set(struct udevice *dev,
316 unsigned int group_selector,
317 unsigned int param, unsigned int arg)
319 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
320 const struct uniphier_pinctrl_group *grp =
321 &priv->socdata->groups[group_selector];
324 for (i = 0; i < grp->num_pins; i++) {
325 ret = uniphier_pinconf_set(dev, grp->pins[i], param, arg);
333 #endif /* CONFIG_IS_ENABLED(PINCONF) */
335 static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
338 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
339 unsigned reg, reg_end, shift, mask;
340 unsigned mux_bits = 8;
341 unsigned reg_stride = 4;
342 bool load_pinctrl = false;
345 /* some pins need input-enabling */
346 uniphier_pinconf_input_enable(dev, pin, 1);
349 return; /* dedicated pin; nothing to do for pin-mux */
351 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
354 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
357 * Normal 4 * n shift+3:shift
358 * Debug 4 * n shift+7:shift+4
365 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
366 reg_end = reg + reg_stride;
367 shift = pin * mux_bits % 32;
368 mask = (1U << mux_bits) - 1;
371 * If reg_stride is greater than 4, the MSB of each pinsel shall be
372 * stored in the offset+4.
374 for (; reg < reg_end; reg += 4) {
375 tmp = readl(priv->base + reg);
376 tmp &= ~(mask << shift);
377 tmp |= (mask & muxval) << shift;
378 writel(tmp, priv->base + reg);
384 writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
387 static int uniphier_pinmux_group_set(struct udevice *dev,
388 unsigned group_selector,
389 unsigned func_selector)
391 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
392 const struct uniphier_pinctrl_group *grp =
393 &priv->socdata->groups[group_selector];
396 for (i = 0; i < grp->num_pins; i++)
397 uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]);
402 const struct pinctrl_ops uniphier_pinctrl_ops = {
403 .get_pins_count = uniphier_pinctrl_get_pins_count,
404 .get_pin_name = uniphier_pinctrl_get_pin_name,
405 .get_groups_count = uniphier_pinctrl_get_groups_count,
406 .get_group_name = uniphier_pinctrl_get_group_name,
407 .get_functions_count = uniphier_pinmux_get_functions_count,
408 .get_function_name = uniphier_pinmux_get_function_name,
409 .pinmux_group_set = uniphier_pinmux_group_set,
410 #if CONFIG_IS_ENABLED(PINCONF)
411 .pinconf_num_params = ARRAY_SIZE(uniphier_pinconf_params),
412 .pinconf_params = uniphier_pinconf_params,
413 .pinconf_set = uniphier_pinconf_set,
414 .pinconf_group_set = uniphier_pinconf_group_set,
416 .set_state = pinctrl_generic_set_state,
419 int uniphier_pinctrl_probe(struct udevice *dev,
420 struct uniphier_pinctrl_socdata *socdata)
422 struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
425 addr = dev_read_addr(dev->parent);
426 if (addr == FDT_ADDR_T_NONE)
429 priv->base = devm_ioremap(dev, addr, SZ_4K);
433 priv->socdata = socdata;