1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC
5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
6 * Copyright (C) 2022 StarFive Technology Co., Ltd.
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/reset.h>
20 #include <linux/spinlock.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
25 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
28 #include "../pinctrl-utils.h"
29 #include "../pinmux.h"
30 #include "../pinconf.h"
31 #include "pinctrl-starfive.h"
33 /* pad control bits */
34 #define STARFIVE_PADCFG_POS BIT(7)
35 #define STARFIVE_PADCFG_SMT BIT(6)
36 #define STARFIVE_PADCFG_SLEW BIT(5)
37 #define STARFIVE_PADCFG_PD BIT(4)
38 #define STARFIVE_PADCFG_PU BIT(3)
39 #define STARFIVE_PADCFG_BIAS (STARFIVE_PADCFG_PD | STARFIVE_PADCFG_PU)
40 #define STARFIVE_PADCFG_DS_MASK GENMASK(2, 1)
41 #define STARFIVE_PADCFG_DS_2MA (0U << 1)
42 #define STARFIVE_PADCFG_DS_4MA BIT(1)
43 #define STARFIVE_PADCFG_DS_8MA (2U << 1)
44 #define STARFIVE_PADCFG_DS_12MA (3U << 1)
45 #define STARFIVE_PADCFG_IE BIT(0)
46 #define GPIO_NUM_PER_WORD 32
49 * The packed pinmux values from the device tree look like this:
51 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
52 * | din | dout | doen | function | pin |
54 static unsigned int starfive_pinmux_din(u32 v)
56 return (v & GENMASK(31, 24)) >> 24;
59 static u32 starfive_pinmux_dout(u32 v)
61 return (v & GENMASK(23, 16)) >> 16;
64 static u32 starfive_pinmux_doen(u32 v)
66 return (v & GENMASK(15, 10)) >> 10;
69 static u32 starfive_pinmux_function(u32 v)
71 return (v & GENMASK(9, 8)) >> 8;
74 static unsigned int starfive_pinmux_pin(u32 v)
76 return v & GENMASK(7, 0);
79 static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
81 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
83 return container_of(gc, struct starfive_pinctrl, gc);
86 struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
88 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
90 return container_of(gc, struct starfive_pinctrl, gc);
93 #ifdef CONFIG_DEBUG_FS
94 static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
95 struct seq_file *s, unsigned int pin)
97 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
98 const struct starfive_pinctrl_soc_info *info = sfp->info;
100 seq_printf(s, "%s", dev_name(pctldev->dev));
102 if (pin < sfp->gc.ngpio) {
103 unsigned int offset = 4 * (pin / 4);
104 unsigned int shift = 8 * (pin % 4);
105 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
106 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
107 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);
109 dout = (dout >> shift) & info->dout_mask;
110 doen = (doen >> shift) & info->doen_mask;
111 gpi = ((gpi >> shift) - 2) & info->gpi_mask;
113 seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi);
117 #define starfive_pin_dbg_show NULL
120 static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
121 struct device_node *np,
122 struct pinctrl_map **maps,
123 unsigned int *num_maps)
125 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
126 struct device *dev = sfp->gc.parent;
127 struct device_node *child;
128 struct pinctrl_map *map;
129 const char **pgnames;
136 for_each_child_of_node(np, child)
140 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
144 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
150 mutex_lock(&sfp->mutex);
151 for_each_child_of_node(np, child) {
152 int npins = of_property_count_u32_elems(child, "pinmux");
159 "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
165 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
171 pgnames[ngroups++] = grpname;
173 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
179 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
185 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
189 for (i = 0; i < npins; i++)
190 pins[i] = starfive_pinmux_pin(pinmux[i]);
192 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
193 map[nmaps].data.mux.function = np->name;
194 map[nmaps].data.mux.group = grpname;
197 ret = pinctrl_generic_add_group(pctldev, grpname,
198 pins, npins, pinmux);
200 dev_err(dev, "error adding group %s: %d\n", grpname, ret);
204 ret = pinconf_generic_parse_dt_config(child, pctldev,
205 &map[nmaps].data.configs.configs,
206 &map[nmaps].data.configs.num_configs);
208 dev_err(dev, "error parsing pin config of group %s: %d\n",
213 /* don't create a map if there are no pinconf settings */
214 if (map[nmaps].data.configs.num_configs == 0)
217 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
218 map[nmaps].data.configs.group_or_pin = grpname;
222 ret = pinmux_generic_add_function(pctldev, np->name,
223 pgnames, ngroups, NULL);
225 dev_err(dev, "error adding function %s: %d\n", np->name, ret);
228 mutex_unlock(&sfp->mutex);
237 pinctrl_utils_free_map(pctldev, map, nmaps);
238 mutex_unlock(&sfp->mutex);
242 static const struct pinctrl_ops starfive_pinctrl_ops = {
243 .get_groups_count = pinctrl_generic_get_group_count,
244 .get_group_name = pinctrl_generic_get_group_name,
245 .get_group_pins = pinctrl_generic_get_group_pins,
246 .pin_dbg_show = starfive_pin_dbg_show,
247 .dt_node_to_map = starfive_dt_node_to_map,
248 .dt_free_map = pinctrl_utils_free_map,
251 void starfive_set_gpiomux(struct starfive_pinctrl *sfp, unsigned int pin,
252 unsigned int din, u32 dout, u32 doen)
254 const struct starfive_pinctrl_soc_info *info = sfp->info;
256 unsigned int offset = 4 * (pin / 4);
257 unsigned int shift = 8 * (pin % 4);
258 u32 dout_mask = info->dout_mask << shift;
259 u32 done_mask = info->doen_mask << shift;
261 void __iomem *reg_dout;
262 void __iomem *reg_doen;
263 void __iomem *reg_din;
266 reg_dout = sfp->base + info->dout_reg_base + offset;
267 reg_doen = sfp->base + info->doen_reg_base + offset;
270 if (din != GPI_NONE) {
271 unsigned int ioffset = 4 * (din / 4);
272 unsigned int ishift = 8 * (din % 4);
274 reg_din = sfp->base + info->gpi_reg_base + ioffset;
275 ival = (pin + 2) << ishift;
276 imask = info->gpi_mask << ishift;
281 raw_spin_lock_irqsave(&sfp->lock, flags);
282 dout |= readl_relaxed(reg_dout) & ~dout_mask;
283 writel_relaxed(dout, reg_dout);
284 doen |= readl_relaxed(reg_doen) & ~done_mask;
285 writel_relaxed(doen, reg_doen);
287 ival |= readl_relaxed(reg_din) & ~imask;
288 writel_relaxed(ival, reg_din);
290 raw_spin_unlock_irqrestore(&sfp->lock, flags);
293 static int starfive_set_mux(struct pinctrl_dev *pctldev,
294 unsigned int fsel, unsigned int gsel)
296 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
297 const struct starfive_pinctrl_soc_info *info = sfp->info;
298 const struct group_desc *group;
302 group = pinctrl_generic_get_group(pctldev, gsel);
306 pinmux = group->data;
307 for (i = 0; i < group->num_pins; i++) {
310 if (info->starfive_set_one_pin_mux)
311 info->starfive_set_one_pin_mux(sfp,
312 starfive_pinmux_pin(v),
313 starfive_pinmux_din(v),
314 starfive_pinmux_dout(v),
315 starfive_pinmux_doen(v),
316 starfive_pinmux_function(v));
322 static const struct pinmux_ops starfive_pinmux_ops = {
323 .get_functions_count = pinmux_generic_get_function_count,
324 .get_function_name = pinmux_generic_get_function_name,
325 .get_function_groups = pinmux_generic_get_function_groups,
326 .set_mux = starfive_set_mux,
330 static const u8 starfive_drive_strength_mA[4] = { 2, 4, 8, 12 };
332 static u32 starfive_padcfg_ds_to_mA(u32 padcfg)
334 return starfive_drive_strength_mA[(padcfg >> 1) & 3U];
337 static u32 starfive_padcfg_ds_from_mA(u32 v)
341 for (i = 0; i < 3; i++) {
342 if (v <= starfive_drive_strength_mA[i])
348 static void starfive_padcfg_rmw(struct starfive_pinctrl *sfp,
349 unsigned int pin, u32 mask, u32 value)
351 const struct starfive_pinctrl_soc_info *info = sfp->info;
356 if (!info->starfive_get_padcfg_base)
359 padcfg_base = info->starfive_get_padcfg_base(sfp, pin);
363 reg = sfp->base + padcfg_base + 4 * pin;
366 raw_spin_lock_irqsave(&sfp->lock, flags);
367 value |= readl_relaxed(reg) & ~mask;
368 writel_relaxed(value, reg);
369 raw_spin_unlock_irqrestore(&sfp->lock, flags);
372 static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
373 unsigned int pin, unsigned long *config)
375 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
376 const struct starfive_pinctrl_soc_info *info = sfp->info;
377 int param = pinconf_to_config_param(*config);
382 if (!info->starfive_get_padcfg_base)
385 padcfg_base = info->starfive_get_padcfg_base(sfp, pin);
389 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
391 case PIN_CONFIG_BIAS_DISABLE:
392 enabled = !(padcfg & STARFIVE_PADCFG_BIAS);
395 case PIN_CONFIG_BIAS_PULL_DOWN:
396 enabled = padcfg & STARFIVE_PADCFG_PD;
399 case PIN_CONFIG_BIAS_PULL_UP:
400 enabled = padcfg & STARFIVE_PADCFG_PU;
403 case PIN_CONFIG_DRIVE_STRENGTH:
405 arg = starfive_padcfg_ds_to_mA(padcfg);
407 case PIN_CONFIG_INPUT_ENABLE:
408 enabled = padcfg & STARFIVE_PADCFG_IE;
411 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
412 enabled = padcfg & STARFIVE_PADCFG_SMT;
415 case PIN_CONFIG_SLEW_RATE:
417 arg = !!(padcfg & STARFIVE_PADCFG_SLEW);
423 *config = pinconf_to_config_packed(param, arg);
424 return enabled ? 0 : -EINVAL;
427 static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
429 unsigned long *config)
431 const struct group_desc *group;
433 group = pinctrl_generic_get_group(pctldev, gsel);
437 return starfive_pinconf_get(pctldev, group->pins[0], config);
440 static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
442 unsigned long *configs,
443 unsigned int num_configs)
445 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
446 const struct group_desc *group;
450 group = pinctrl_generic_get_group(pctldev, gsel);
456 for (i = 0; i < num_configs; i++) {
457 int param = pinconf_to_config_param(configs[i]);
458 u32 arg = pinconf_to_config_argument(configs[i]);
461 case PIN_CONFIG_BIAS_DISABLE:
462 mask |= STARFIVE_PADCFG_BIAS;
463 value &= ~STARFIVE_PADCFG_BIAS;
465 case PIN_CONFIG_BIAS_PULL_DOWN:
468 mask |= STARFIVE_PADCFG_BIAS;
469 value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PD;
471 case PIN_CONFIG_BIAS_PULL_UP:
474 mask |= STARFIVE_PADCFG_BIAS;
475 value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PU;
477 case PIN_CONFIG_DRIVE_STRENGTH:
478 mask |= STARFIVE_PADCFG_DS_MASK;
479 value = (value & ~STARFIVE_PADCFG_DS_MASK) |
480 starfive_padcfg_ds_from_mA(arg);
482 case PIN_CONFIG_INPUT_ENABLE:
483 mask |= STARFIVE_PADCFG_IE;
485 value |= STARFIVE_PADCFG_IE;
487 value &= ~STARFIVE_PADCFG_IE;
489 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
490 mask |= STARFIVE_PADCFG_SMT;
492 value |= STARFIVE_PADCFG_SMT;
494 value &= ~STARFIVE_PADCFG_SMT;
496 case PIN_CONFIG_SLEW_RATE:
497 mask |= STARFIVE_PADCFG_SLEW;
499 value |= STARFIVE_PADCFG_SLEW;
501 value &= ~STARFIVE_PADCFG_SLEW;
508 for (i = 0; i < group->num_pins; i++)
509 starfive_padcfg_rmw(sfp, group->pins[i], mask, value);
514 #ifdef CONFIG_DEBUG_FS
515 static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
516 struct seq_file *s, unsigned int pin)
518 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
519 const struct starfive_pinctrl_soc_info *info = sfp->info;
523 if (!info->starfive_get_padcfg_base)
526 padcfg_base = info->starfive_get_padcfg_base(sfp, pin);
530 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
531 seq_printf(s, " (0x%02x)", value);
534 #define starfive_pinconf_dbg_show NULL
537 static const struct pinconf_ops starfive_pinconf_ops = {
538 .pin_config_get = starfive_pinconf_get,
539 .pin_config_group_get = starfive_pinconf_group_get,
540 .pin_config_group_set = starfive_pinconf_group_set,
541 .pin_config_dbg_show = starfive_pinconf_dbg_show,
545 static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio)
547 return pinctrl_gpio_request(gc->base + gpio);
550 static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio)
552 pinctrl_gpio_free(gc->base + gpio);
555 static int starfive_gpio_get_direction(struct gpio_chip *gc,
558 struct starfive_pinctrl *sfp = container_of(gc,
559 struct starfive_pinctrl, gc);
560 const struct starfive_pinctrl_soc_info *info = sfp->info;
561 unsigned int offset = 4 * (gpio / 4);
562 unsigned int shift = 8 * (gpio % 4);
563 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
565 doen = (doen >> shift) & info->doen_mask;
567 return doen == GPOEN_ENABLE ?
568 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
571 static int starfive_gpio_direction_input(struct gpio_chip *gc,
574 struct starfive_pinctrl *sfp = container_of(gc,
575 struct starfive_pinctrl, gc);
576 const struct starfive_pinctrl_soc_info *info = sfp->info;
578 /* enable input and schmitt trigger */
579 starfive_padcfg_rmw(sfp, gpio,
580 STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT,
581 STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT);
583 if (info->starfive_set_one_pin_mux)
584 info->starfive_set_one_pin_mux(sfp, gpio,
585 GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
590 static int starfive_gpio_direction_output(struct gpio_chip *gc,
591 unsigned int gpio, int value)
593 struct starfive_pinctrl *sfp = container_of(gc,
594 struct starfive_pinctrl, gc);
595 const struct starfive_pinctrl_soc_info *info = sfp->info;
597 if (info->starfive_set_one_pin_mux)
598 info->starfive_set_one_pin_mux(sfp, gpio,
599 GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW,
602 /* disable input, schmitt trigger and bias */
603 starfive_padcfg_rmw(sfp, gpio,
604 STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT
605 | STARFIVE_PADCFG_BIAS, 0);
609 static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
611 struct starfive_pinctrl *sfp = container_of(gc,
612 struct starfive_pinctrl, gc);
613 const struct starfive_pinctrl_soc_info *info = sfp->info;
614 void __iomem *reg = sfp->base + info->gpioin_reg_base
615 + 4 * (gpio / GPIO_NUM_PER_WORD);
617 return !!(readl_relaxed(reg) & BIT(gpio % GPIO_NUM_PER_WORD));
620 static void starfive_gpio_set(struct gpio_chip *gc,
621 unsigned int gpio, int value)
623 struct starfive_pinctrl *sfp = container_of(gc,
624 struct starfive_pinctrl, gc);
625 const struct starfive_pinctrl_soc_info *info = sfp->info;
626 unsigned int offset = 4 * (gpio / 4);
627 unsigned int shift = 8 * (gpio % 4);
628 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;
629 u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift;
630 u32 mask = info->dout_mask << shift;
633 raw_spin_lock_irqsave(&sfp->lock, flags);
634 dout |= readl_relaxed(reg_dout) & ~mask;
635 writel_relaxed(dout, reg_dout);
636 raw_spin_unlock_irqrestore(&sfp->lock, flags);
639 static int starfive_gpio_set_config(struct gpio_chip *gc,
640 unsigned int gpio, unsigned long config)
642 struct starfive_pinctrl *sfp = container_of(gc,
643 struct starfive_pinctrl, gc);
644 u32 arg = pinconf_to_config_argument(config);
648 switch (pinconf_to_config_param(config)) {
649 case PIN_CONFIG_BIAS_DISABLE:
650 mask = STARFIVE_PADCFG_BIAS;
653 case PIN_CONFIG_BIAS_PULL_DOWN:
656 mask = STARFIVE_PADCFG_BIAS;
657 value = STARFIVE_PADCFG_PD;
659 case PIN_CONFIG_BIAS_PULL_UP:
662 mask = STARFIVE_PADCFG_BIAS;
663 value = STARFIVE_PADCFG_PU;
665 case PIN_CONFIG_DRIVE_PUSH_PULL:
667 case PIN_CONFIG_INPUT_ENABLE:
668 mask = STARFIVE_PADCFG_IE;
669 value = arg ? STARFIVE_PADCFG_IE : 0;
671 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
672 mask = STARFIVE_PADCFG_SMT;
673 value = arg ? STARFIVE_PADCFG_SMT : 0;
679 starfive_padcfg_rmw(sfp, gpio, mask, value);
683 static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
685 struct starfive_pinctrl *sfp = container_of(gc,
686 struct starfive_pinctrl, gc);
688 sfp->gpios.name = sfp->gc.label;
689 sfp->gpios.base = sfp->gc.base;
690 sfp->gpios.pin_base = 0;
691 sfp->gpios.npins = sfp->gc.ngpio;
692 sfp->gpios.gc = &sfp->gc;
693 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
697 static void starfive_irq_ack(struct irq_data *d)
699 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
700 const struct starfive_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
701 irq_hw_number_t gpio = irqd_to_hwirq(d);
702 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
703 + 4 * (gpio / GPIO_NUM_PER_WORD);
704 u32 mask = BIT(gpio % GPIO_NUM_PER_WORD);
708 raw_spin_lock_irqsave(&sfp->lock, flags);
709 value = readl_relaxed(ic) & ~mask;
710 writel_relaxed(value, ic);
711 writel_relaxed(value | mask, ic);
712 raw_spin_unlock_irqrestore(&sfp->lock, flags);
715 static void starfive_irq_mask(struct irq_data *d)
717 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
718 const struct starfive_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
719 irq_hw_number_t gpio = irqd_to_hwirq(d);
720 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
721 + 4 * (gpio / GPIO_NUM_PER_WORD);
722 u32 mask = BIT(gpio % GPIO_NUM_PER_WORD);
726 raw_spin_lock_irqsave(&sfp->lock, flags);
727 value = readl_relaxed(ie) & ~mask;
728 writel_relaxed(value, ie);
729 raw_spin_unlock_irqrestore(&sfp->lock, flags);
731 gpiochip_disable_irq(&sfp->gc, d->hwirq);
734 static void starfive_irq_mask_ack(struct irq_data *d)
736 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
737 const struct starfive_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
738 irq_hw_number_t gpio = irqd_to_hwirq(d);
739 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
740 + 4 * (gpio / GPIO_NUM_PER_WORD);
741 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
742 + 4 * (gpio / GPIO_NUM_PER_WORD);
743 u32 mask = BIT(gpio % GPIO_NUM_PER_WORD);
747 raw_spin_lock_irqsave(&sfp->lock, flags);
748 value = readl_relaxed(ie) & ~mask;
749 writel_relaxed(value, ie);
751 value = readl_relaxed(ic) & ~mask;
752 writel_relaxed(value, ic);
753 writel_relaxed(value | mask, ic);
754 raw_spin_unlock_irqrestore(&sfp->lock, flags);
757 static void starfive_irq_unmask(struct irq_data *d)
759 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
760 const struct starfive_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
761 irq_hw_number_t gpio = irqd_to_hwirq(d);
762 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
763 + 4 * (gpio / GPIO_NUM_PER_WORD);
764 u32 mask = BIT(gpio % GPIO_NUM_PER_WORD);
768 gpiochip_enable_irq(&sfp->gc, d->hwirq);
770 raw_spin_lock_irqsave(&sfp->lock, flags);
771 value = readl_relaxed(ie) | mask;
772 writel_relaxed(value, ie);
773 raw_spin_unlock_irqrestore(&sfp->lock, flags);
776 static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
778 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
779 const struct starfive_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
780 irq_hw_number_t gpio = irqd_to_hwirq(d);
781 void __iomem *base = sfp->base + 4 * (gpio / GPIO_NUM_PER_WORD);
782 u32 mask = BIT(gpio % GPIO_NUM_PER_WORD);
783 u32 irq_type, edge_both, polarity;
787 case IRQ_TYPE_EDGE_RISING:
788 irq_type = mask; /* 1: edge triggered */
789 edge_both = 0; /* 0: single edge */
790 polarity = mask; /* 1: rising edge */
792 case IRQ_TYPE_EDGE_FALLING:
793 irq_type = mask; /* 1: edge triggered */
794 edge_both = 0; /* 0: single edge */
795 polarity = 0; /* 0: falling edge */
797 case IRQ_TYPE_EDGE_BOTH:
798 irq_type = mask; /* 1: edge triggered */
799 edge_both = mask; /* 1: both edges */
800 polarity = 0; /* 0: ignored */
802 case IRQ_TYPE_LEVEL_HIGH:
803 irq_type = 0; /* 0: level triggered */
804 edge_both = 0; /* 0: ignored */
805 polarity = mask; /* 1: high level */
807 case IRQ_TYPE_LEVEL_LOW:
808 irq_type = 0; /* 0: level triggered */
809 edge_both = 0; /* 0: ignored */
810 polarity = 0; /* 0: low level */
816 if (trigger & IRQ_TYPE_EDGE_BOTH)
817 irq_set_handler_locked(d, handle_edge_irq);
819 irq_set_handler_locked(d, handle_level_irq);
821 raw_spin_lock_irqsave(&sfp->lock, flags);
822 irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask;
823 writel_relaxed(irq_type, base + irq_reg->is_reg_base);
825 edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask;
826 writel_relaxed(edge_both, base + irq_reg->ibe_reg_base);
828 polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask;
829 writel_relaxed(polarity, base + irq_reg->iev_reg_base);
830 raw_spin_unlock_irqrestore(&sfp->lock, flags);
834 static struct irq_chip starfive_irq_chip = {
835 .irq_ack = starfive_irq_ack,
836 .irq_mask = starfive_irq_mask,
837 .irq_mask_ack = starfive_irq_mask_ack,
838 .irq_unmask = starfive_irq_unmask,
839 .irq_set_type = starfive_irq_set_type,
840 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
841 GPIOCHIP_IRQ_RESOURCE_HELPERS,
844 static void starfive_disable_clock(void *data)
846 clk_disable_unprepare(data);
849 int starfive_pinctrl_probe(struct platform_device *pdev,
850 const struct starfive_pinctrl_soc_info *info)
852 struct device *dev = &pdev->dev;
853 struct starfive_pinctrl *sfp;
854 struct pinctrl_desc *starfive_pinctrl_desc;
855 struct reset_control *rst;
859 if (!info || !info->pins || !info->npins) {
860 dev_err(dev, "wrong pinctrl info\n");
864 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
868 sfp->base = devm_platform_ioremap_resource(pdev, 0);
869 if (IS_ERR(sfp->base))
870 return PTR_ERR(sfp->base);
872 clk = devm_clk_get_optional(dev, NULL);
874 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
876 rst = devm_reset_control_get_exclusive(dev, NULL);
878 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
881 * we don't want to assert reset and risk undoing pin muxing for the
882 * early boot serial console, but let's make sure the reset line is
883 * deasserted in case someone runs a really minimal bootloader.
885 ret = reset_control_deassert(rst);
887 return dev_err_probe(dev, ret, "could not deassert reset\n");
890 ret = clk_prepare_enable(clk);
892 return dev_err_probe(dev, ret, "could not enable clock\n");
894 ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
899 starfive_pinctrl_desc = devm_kzalloc(&pdev->dev,
900 sizeof(*starfive_pinctrl_desc),
902 if (!starfive_pinctrl_desc)
905 starfive_pinctrl_desc->name = dev_name(dev);
906 starfive_pinctrl_desc->pins = info->pins;
907 starfive_pinctrl_desc->npins = info->npins;
908 starfive_pinctrl_desc->pctlops = &starfive_pinctrl_ops;
909 starfive_pinctrl_desc->pmxops = &starfive_pinmux_ops;
910 starfive_pinctrl_desc->confops = &starfive_pinconf_ops;
911 starfive_pinctrl_desc->owner = THIS_MODULE;
915 platform_set_drvdata(pdev, sfp);
916 sfp->gc.parent = dev;
917 raw_spin_lock_init(&sfp->lock);
918 mutex_init(&sfp->mutex);
920 ret = devm_pinctrl_register_and_init(dev,
921 starfive_pinctrl_desc,
924 return dev_err_probe(dev, ret,
925 "could not register pinctrl driver\n");
927 sfp->gc.label = dev_name(dev);
928 sfp->gc.owner = THIS_MODULE;
929 sfp->gc.request = starfive_gpio_request;
930 sfp->gc.free = starfive_gpio_free;
931 sfp->gc.get_direction = starfive_gpio_get_direction;
932 sfp->gc.direction_input = starfive_gpio_direction_input;
933 sfp->gc.direction_output = starfive_gpio_direction_output;
934 sfp->gc.get = starfive_gpio_get;
935 sfp->gc.set = starfive_gpio_set;
936 sfp->gc.set_config = starfive_gpio_set_config;
937 sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
938 sfp->gc.base = info->gc_base;
939 sfp->gc.ngpio = info->ngpios;
941 starfive_irq_chip.name = sfp->gc.label;
942 gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
943 sfp->gc.irq.parent_handler = info->starfive_gpio_irq_handler;
944 sfp->gc.irq.num_parents = 1;
945 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
946 sizeof(*sfp->gc.irq.parents),
948 if (!sfp->gc.irq.parents)
950 sfp->gc.irq.default_type = IRQ_TYPE_NONE;
951 sfp->gc.irq.handler = handle_bad_irq;
952 sfp->gc.irq.init_hw = info->starfive_gpio_init_hw;
954 ret = platform_get_irq(pdev, 0);
957 sfp->gc.irq.parents[0] = ret;
959 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
961 return dev_err_probe(dev, ret, "could not register gpiochip\n");
963 irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
965 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);
967 return pinctrl_enable(sfp->pctl);
970 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC");
971 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
972 MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");