drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pinctrl / GPIO driver for StarFive JH7110 SoC
   4  *
   5  * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
   6  */
   7
   8 #include <linux/err.h>
   9 #include <linux/init.h>
  10 #include <linux/of.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 #include <linux/pinctrl/pinmux.h>
  19 #include <linux/pinctrl/pinconf.h>
  20 #include <linux/pinctrl/pinconf-generic.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26
  27 #include "../core.h"
  28 #include "../pinconf.h"
  29 #include "../pinmux.h"
  30 #include "pinctrl-starfive.h"
  31
  32 /***************sys_iomux***************/
  33 #define SYS_GPO_DOEN_CFG_BASE_REG                       0x0
  34 #define SYS_GPO_DOEN_CFG_END_REG                        0x3c
  35
  36 #define SYS_GPO_DOUT_CFG_BASE_REG                       0x40
  37 #define SYS_GPO_DOUT_CFG_END_REG                        0x7c
  38
  39 #define SYS_GPI_DIN_CFG_BASE_REG                        0x80
  40 #define SYS_GPI_DIN_CFG_END_REG                         0xd8
  41
  42 /*sys_iomux PIN 0-74 ioconfig reg*/
  43 #define SYS_GPO_PDA_0_74_CFG_BASE_REG                   0x120
  44 #define SYS_GPO_PDA_0_74_CFG_END_REG                    0x248
  45
  46 /*sys_iomux PIN 75-88 gamc1 no ioconfig reg*/
  47
  48 /*sys_iomux PIN 89-94 ioconfig reg*/
  49 #define SYS_GPO_PDA_89_94_CFG_BASE_REG                  0x284
  50 #define SYS_GPO_PDA_89_94_CFG_END_REG                   0x298
  51
  52 //sys_iomux GPIO CTRL
  53 #define GPIO_EN                                         0xdc
  54 #define GPIO_IS_LOW                                     0xe0
  55 #define GPIO_IS_HIGH                                    0xe4
  56 #define GPIO_IC_LOW                                     0xe8
  57 #define GPIO_IC_HIGH                                    0xec
  58 #define GPIO_IBE_LOW                                    0xf0
  59 #define GPIO_IBE_HIGH                                   0xf4
  60 #define GPIO_IEV_LOW                                    0xf8
  61 #define GPIO_IEV_HIGH                                   0xfc
  62 #define GPIO_IE_LOW                                     0x100
  63 #define GPIO_IE_HIGH                                    0x104
  64 //read only
  65 #define GPIO_RIS_LOW                                    0x108
  66 #define GPIO_RIS_HIGH                                   0x10c
  67 #define GPIO_MIS_LOW                                    0x110
  68 #define GPIO_MIS_HIGH                                   0x114
  69 #define GPIO_DIN_LOW                                    0x118
  70 #define GPIO_DIN_HIGH                                   0x11c
  71
  72 #define GPIO_DOEN_X_REG                                 0x0
  73 #define GPIO_DOUT_X_REG                                 0x40
  74
  75 #define GPIO_INPUT_ENABLE_X_REG                         0x120
  76
  77 #define MAX_GPIO                                        64
  78 /***************sys_iomux***************/
  79
  80 /***************aon_iomux***************/
  81 #define AON_GPO_DOEN_CFG_BASE_REG                       0x0
  82 #define AON_GPO_DOUT_CFG_BASE_REG                       0x4
  83 #define AON_GPI_DIN_CFG_BASE_REG                        0x8
  84 #define AON_GPIO_DIN_REG                                0x2c
  85
  86 //aon_iomux GPIO CTRL
  87 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_3_ADDR          0xc
  88 #define AON_GPIOEN_0_REG_SHIFT                          0x0
  89 #define AON_GPIOEN_0_REG_MASK                           0x1
  90 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_4_ADDR          0x10
  91 #define AON_GPIOIS_0_REG_SHIFT                          0x0
  92 #define AON_GPIOIS_0_REG_MASK                           0xF
  93 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_5_ADDR          0x14
  94 #define AON_GPIOIC_0_REG_SHIFT                          0x0
  95 #define AON_GPIOIC_0_REG_MASK                           0xF
  96 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_6_ADDR          0x18
  97 #define AON_GPIOIBE_0_REG_SHIFT                         0x0
  98 #define AON_GPIOIBE_0_REG_MASK                          0xF
  99 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_7_ADDR          0x1c
 100 #define AON_GPIOIEV_0_REG_SHIFT                         0x0
 101 #define AON_GPIOIEV_0_REG_MASK                          0xF
 102 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_8_ADDR          0x20
 103 #define AON_GPIOIE_0_REG_SHIFT                          0x0
 104 #define AON_GPIOIE_0_REG_MASK                           0xF
 105 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_9_ADDR          0x24
 106 #define AON_GPIORIS_0_REG_SHIFT                         0x0
 107 #define AON_GPIORIS_0_REG_MASK                          0xF
 108 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_10_ADDR         0x28
 109 #define AON_GPIOMIS_0_REG_SHIFT                         0x0
 110 #define AON_GPIOMIS_0_REG_MASK                          0xF
 111 #define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_11_ADDR         0x2c
 112 #define AON_GPIO_IN_SYNC2_0_REG_SHIFT                   0x0
 113 #define AON_GPIO_IN_SYNC2_0_REG_MASK                    0xF
 114
 115
 116 /* aon_iomux PIN ioconfig reg*/
 117 #define AON_IOMUX_CFG__SAIF__SYSCFG_48_ADDR             0x30
 118 #define PADCFG_PAD_TESTEN_POS_WIDTH                     0x1
 119 #define PADCFG_PAD_TESTEN_POS_SHIFT                     0x0
 120 #define PADCFG_PAD_TESTEN_POS_MASK                      0x1
 121 #define AON_IOMUX_CFG__SAIF__SYSCFG_52_ADDR             0x34
 122 #define PADCFG_PAD_RGPIO0_IE_WIDTH                      0x1
 123 #define PADCFG_PAD_RGPIO0_IE_SHIFT                      0x0
 124 #define PADCFG_PAD_RGPIO0_IE_MASK                       0x1
 125 #define PADCFG_PAD_RGPIO0_DS_WIDTH                      0x2
 126 #define PADCFG_PAD_RGPIO0_DS_SHIFT                      0x1
 127 #define PADCFG_PAD_RGPIO0_DS_MASK                       0x6
 128 #define PADCFG_PAD_RGPIO0_PU_WIDTH                      0x1
 129 #define PADCFG_PAD_RGPIO0_PU_SHIFT                      0x3
 130 #define PADCFG_PAD_RGPIO0_PU_MASK                       0x8
 131 #define PADCFG_PAD_RGPIO0_PD_WIDTH                      0x1
 132 #define PADCFG_PAD_RGPIO0_PD_SHIFT                      0x4
 133 #define PADCFG_PAD_RGPIO0_PD_MASK                       0x10
 134 #define PADCFG_PAD_RGPIO0_SLEW_WIDTH                    0x1
 135 #define PADCFG_PAD_RGPIO0_SLEW_SHIFT                    0x5
 136 #define PADCFG_PAD_RGPIO0_SLEW_MASK                     0x20
 137 #define PADCFG_PAD_RGPIO0_SMT_WIDTH                     0x1
 138 #define PADCFG_PAD_RGPIO0_SMT_SHIFT                     0x6
 139 #define PADCFG_PAD_RGPIO0_SMT_MASK                      0x40
 140 #define PADCFG_PAD_RGPIO0_POS_WIDTH                     0x1
 141 #define PADCFG_PAD_RGPIO0_POS_SHIFT                     0x7
 142 #define PADCFG_PAD_RGPIO0_POS_MASK                      0x80
 143 #define AON_IOMUX_CFG__SAIF__SYSCFG_56_ADDR             0x38
 144 #define PADCFG_PAD_RGPIO1_IE_WIDTH                      0x1
 145 #define PADCFG_PAD_RGPIO1_IE_SHIFT                      0x0
 146 #define PADCFG_PAD_RGPIO1_IE_MASK                       0x1
 147 #define PADCFG_PAD_RGPIO1_DS_WIDTH                      0x2
 148 #define PADCFG_PAD_RGPIO1_DS_SHIFT                      0x1
 149 #define PADCFG_PAD_RGPIO1_DS_MASK                       0x6
 150 #define PADCFG_PAD_RGPIO1_PU_WIDTH                      0x1
 151 #define PADCFG_PAD_RGPIO1_PU_SHIFT                      0x3
 152 #define PADCFG_PAD_RGPIO1_PU_MASK                       0x8
 153 #define PADCFG_PAD_RGPIO1_PD_WIDTH                      0x1
 154 #define PADCFG_PAD_RGPIO1_PD_SHIFT                      0x4
 155 #define PADCFG_PAD_RGPIO1_PD_MASK                       0x10
 156 #define PADCFG_PAD_RGPIO1_SLEW_WIDTH                    0x1
 157 #define PADCFG_PAD_RGPIO1_SLEW_SHIFT                    0x5
 158 #define PADCFG_PAD_RGPIO1_SLEW_MASK                     0x20
 159 #define PADCFG_PAD_RGPIO1_SMT_WIDTH                     0x1
 160 #define PADCFG_PAD_RGPIO1_SMT_SHIFT                     0x6
 161 #define PADCFG_PAD_RGPIO1_SMT_MASK                      0x40
 162 #define PADCFG_PAD_RGPIO1_POS_WIDTH                     0x1
 163 #define PADCFG_PAD_RGPIO1_POS_SHIFT                     0x7
 164 #define PADCFG_PAD_RGPIO1_POS_MASK                      0x80
 165 #define AON_IOMUX_CFG__SAIF__SYSCFG_60_ADDR             0x3c
 166 #define PADCFG_PAD_RGPIO2_IE_WIDTH                      0x1
 167 #define PADCFG_PAD_RGPIO2_IE_SHIFT                      0x0
 168 #define PADCFG_PAD_RGPIO2_IE_MASK                       0x1
 169 #define PADCFG_PAD_RGPIO2_DS_WIDTH                      0x2
 170 #define PADCFG_PAD_RGPIO2_DS_SHIFT                      0x1
 171 #define PADCFG_PAD_RGPIO2_DS_MASK                       0x6
 172 #define PADCFG_PAD_RGPIO2_PU_WIDTH                      0x1
 173 #define PADCFG_PAD_RGPIO2_PU_SHIFT                      0x3
 174 #define PADCFG_PAD_RGPIO2_PU_MASK                       0x8
 175 #define PADCFG_PAD_RGPIO2_PD_WIDTH                      0x1
 176 #define PADCFG_PAD_RGPIO2_PD_SHIFT                      0x4
 177 #define PADCFG_PAD_RGPIO2_PD_MASK                       0x10
 178 #define PADCFG_PAD_RGPIO2_SLEW_WIDTH                    0x1
 179 #define PADCFG_PAD_RGPIO2_SLEW_SHIFT                    0x5
 180 #define PADCFG_PAD_RGPIO2_SLEW_MASK                     0x20
 181 #define PADCFG_PAD_RGPIO2_SMT_WIDTH                     0x1
 182 #define PADCFG_PAD_RGPIO2_SMT_SHIFT                     0x6
 183 #define PADCFG_PAD_RGPIO2_SMT_MASK                      0x40
 184 #define PADCFG_PAD_RGPIO2_POS_WIDTH                     0x1
 185 #define PADCFG_PAD_RGPIO2_POS_SHIFT                     0x7
 186 #define PADCFG_PAD_RGPIO2_POS_MASK                      0x80
 187 #define AON_IOMUX_CFG__SAIF__SYSCFG_64_ADDR             0x40
 188 #define PADCFG_PAD_RGPIO3_IE_WIDTH                      0x1
 189 #define PADCFG_PAD_RGPIO3_IE_SHIFT                      0x0
 190 #define PADCFG_PAD_RGPIO3_IE_MASK                       0x1
 191 #define PADCFG_PAD_RGPIO3_DS_WIDTH                      0x2
 192 #define PADCFG_PAD_RGPIO3_DS_SHIFT                      0x1
 193 #define PADCFG_PAD_RGPIO3_DS_MASK                       0x6
 194 #define PADCFG_PAD_RGPIO3_PU_WIDTH                      0x1
 195 #define PADCFG_PAD_RGPIO3_PU_SHIFT                      0x3
 196 #define PADCFG_PAD_RGPIO3_PU_MASK                       0x8
 197 #define PADCFG_PAD_RGPIO3_PD_WIDTH                      0x1
 198 #define PADCFG_PAD_RGPIO3_PD_SHIFT                      0x4
 199 #define PADCFG_PAD_RGPIO3_PD_MASK                       0x10
 200 #define PADCFG_PAD_RGPIO3_SLEW_WIDTH                    0x1
 201 #define PADCFG_PAD_RGPIO3_SLEW_SHIFT                    0x5
 202 #define PADCFG_PAD_RGPIO3_SLEW_MASK                     0x20
 203 #define PADCFG_PAD_RGPIO3_SMT_WIDTH                     0x1
 204 #define PADCFG_PAD_RGPIO3_SMT_SHIFT                     0x6
 205 #define PADCFG_PAD_RGPIO3_SMT_MASK                      0x40
 206 #define PADCFG_PAD_RGPIO3_POS_WIDTH                     0x1
 207 #define PADCFG_PAD_RGPIO3_POS_SHIFT                     0x7
 208 #define PADCFG_PAD_RGPIO3_POS_MASK                      0x80
 209 #define AON_IOMUX_CFG__SAIF__SYSCFG_68_ADDR             0x44
 210 #define PADCFG_PAD_RSTN_SMT_WIDTH                       0x1
 211 #define PADCFG_PAD_RSTN_SMT_SHIFT                       0x0
 212 #define PADCFG_PAD_RSTN_SMT_MASK                        0x1
 213 #define PADCFG_PAD_RSTN_POS_WIDTH                       0x1
 214 #define PADCFG_PAD_RSTN_POS_SHIFT                       0x1
 215 #define PADCFG_PAD_RSTN_POS_MASK                        0x2
 216 #define AON_IOMUX_CFG__SAIF__SYSCFG_72_ADDR             0x48
 217 #define AON_IOMUX_CFG__SAIF__SYSCFG_76_ADDR             0x4c
 218 #define PADCFG_PAD_RTC_DS_WIDTH                         0x2
 219 #define PADCFG_PAD_RTC_DS_SHIFT                         0x0
 220 #define PADCFG_PAD_RTC_DS_MASK                          0x3
 221 #define AON_IOMUX_CFG__SAIF__SYSCFG_80_ADDR             0x50
 222 #define AON_IOMUX_CFG__SAIF__SYSCFG_84_ADDR             0x54
 223 #define PADCFG_PAD_OSC_DS_WIDTH                         0x2
 224 #define PADCFG_PAD_OSC_DS_SHIFT                         0x0
 225 #define PADCFG_PAD_OSC_DS_MASK                          0x3
 226
 227 /*aon_iomux PIN 0-5 ioconfig reg*/
 228 #define AON_GPO_PDA_0_5_CFG_BASE_REG    AON_IOMUX_CFG__SAIF__SYSCFG_48_ADDR
 229 #define AON_GPO_PDA_0_5_CFG_END_REG     AON_IOMUX_CFG__SAIF__SYSCFG_68_ADDR
 230 #define AON_GPO_PDA_RTC_CFG_REG         AON_IOMUX_CFG__SAIF__SYSCFG_76_ADDR
 231 /***************aon_iomux***************/
 232
 233 #define PADCFG_PAD_GMAC_SYSCON_WIDTH                    0x2
 234 #define PADCFG_PAD_GMAC_SYSCON_SHIFT                    0x0
 235 #define PADCFG_PAD_GMAC_SYSCON_MASK                     0x3
 236
 237 #define GPO_PDA_CFG_OFFSET                              0x4
 238
 239 #define AON_GPIO_INPUT_ENABLE_REG                       0x34
 240
 241 #define AON_GPIO_EN_REG         AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_3_ADDR
 242 #define AON_GPIO_IS_REG         AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_4_ADDR
 243 #define AON_GPIO_IC_REG         AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_5_ADDR
 244 #define AON_GPIO_IBE_REG        AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_6_ADDR
 245 #define AON_GPIO_IEV_REG        AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_7_ADDR
 246 #define AON_GPIO_IE_REG         AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_8_ADDR
 247 #define AON_GPIO_RIS_REG        AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_9_ADDR
 248 #define AON_GPIO_MIS_REG        AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_10_ADDR
 249
 250 /*one dword include 4 gpios*/
 251 #define GPIO_NUM_SHIFT                                  2
 252 /*8 bits for each gpio*/
 253 #define GPIO_BYTE_SHIFT                                 3
 254 /*gpio index in dword */
 255 #define GPIO_INDEX_MASK                                 0x3
 256 #define GPIO_VAL_MASK                                   0x7f
 257
 258 #define GPIO_NUM_PER_REG                                32
 259 #define OFFSET_PER_REG                                  4
 260 #define SYS_GPIO_NUM                                    64
 261 #define AON_GPIO_NUM                                    4
 262
 263 enum starfive_jh7110_sys_pads {
 264         PAD_GPIO0       = 0,
 265         PAD_GPIO1       = 1,
 266         PAD_GPIO2       = 2,
 267         PAD_GPIO3       = 3,
 268         PAD_GPIO4       = 4,
 269         PAD_GPIO5       = 5,
 270         PAD_GPIO6       = 6,
 271         PAD_GPIO7       = 7,
 272         PAD_GPIO8       = 8,
 273         PAD_GPIO9       = 9,
 274         PAD_GPIO10      = 10,
 275         PAD_GPIO11      = 11,
 276         PAD_GPIO12      = 12,
 277         PAD_GPIO13      = 13,
 278         PAD_GPIO14      = 14,
 279         PAD_GPIO15      = 15,
 280         PAD_GPIO16      = 16,
 281         PAD_GPIO17      = 17,
 282         PAD_GPIO18      = 18,
 283         PAD_GPIO19      = 19,
 284         PAD_GPIO20      = 20,
 285         PAD_GPIO21      = 21,
 286         PAD_GPIO22      = 22,
 287         PAD_GPIO23      = 23,
 288         PAD_GPIO24      = 24,
 289         PAD_GPIO25      = 25,
 290         PAD_GPIO26      = 26,
 291         PAD_GPIO27      = 27,
 292         PAD_GPIO28      = 28,
 293         PAD_GPIO29      = 29,
 294         PAD_GPIO30      = 30,
 295         PAD_GPIO31      = 31,
 296         PAD_GPIO32      = 32,
 297         PAD_GPIO33      = 33,
 298         PAD_GPIO34      = 34,
 299         PAD_GPIO35      = 35,
 300         PAD_GPIO36      = 36,
 301         PAD_GPIO37      = 37,
 302         PAD_GPIO38      = 38,
 303         PAD_GPIO39      = 39,
 304         PAD_GPIO40      = 40,
 305         PAD_GPIO41      = 41,
 306         PAD_GPIO42      = 42,
 307         PAD_GPIO43      = 43,
 308         PAD_GPIO44      = 44,
 309         PAD_GPIO45      = 45,
 310         PAD_GPIO46      = 46,
 311         PAD_GPIO47      = 47,
 312         PAD_GPIO48      = 48,
 313         PAD_GPIO49      = 49,
 314         PAD_GPIO50      = 50,
 315         PAD_GPIO51      = 51,
 316         PAD_GPIO52      = 52,
 317         PAD_GPIO53      = 53,
 318         PAD_GPIO54      = 54,
 319         PAD_GPIO55      = 55,
 320         PAD_GPIO56      = 56,
 321         PAD_GPIO57      = 57,
 322         PAD_GPIO58      = 58,
 323         PAD_GPIO59      = 59,
 324         PAD_GPIO60      = 60,
 325         PAD_GPIO61      = 61,
 326         PAD_GPIO62      = 62,
 327         PAD_GPIO63      = 63,
 328         PAD_SD0_CLK     = 64,
 329         PAD_SD0_CMD     = 65,
 330         PAD_SD0_DATA0   = 66,
 331         PAD_SD0_DATA1   = 67,
 332         PAD_SD0_DATA2   = 68,
 333         PAD_SD0_DATA3   = 69,
 334         PAD_SD0_DATA4   = 70,
 335         PAD_SD0_DATA5   = 71,
 336         PAD_SD0_DATA6   = 72,
 337         PAD_SD0_DATA7   = 73,
 338         PAD_SD0_STRB    = 74,
 339         PAD_GMAC1_MDC   = 75,
 340         PAD_GMAC1_MDIO  = 76,
 341         PAD_GMAC1_RXD0  = 77,
 342         PAD_GMAC1_RXD1  = 78,
 343         PAD_GMAC1_RXD2  = 79,
 344         PAD_GMAC1_RXD3  = 80,
 345         PAD_GMAC1_RXDV  = 81,
 346         PAD_GMAC1_RXC   = 82,
 347         PAD_GMAC1_TXD0  = 83,
 348         PAD_GMAC1_TXD1  = 84,
 349         PAD_GMAC1_TXD2  = 85,
 350         PAD_GMAC1_TXD3  = 86,
 351         PAD_GMAC1_TXEN  = 87,
 352         PAD_GMAC1_TXC   = 88,
 353         PAD_QSPI_SCLK   = 89,
 354         PAD_QSPI_CSn0   = 90,
 355         PAD_QSPI_DATA0  = 91,
 356         PAD_QSPI_DATA1  = 92,
 357         PAD_QSPI_DATA2  = 93,
 358         PAD_QSPI_DATA3  = 94,
 359 };
 360
 361
 362 /* Pad names for the pinmux subsystem */
 363 static const struct pinctrl_pin_desc starfive_jh7110_sys_pinctrl_pads[] = {
 364         STARFIVE_PINCTRL_PIN(PAD_GPIO0),
 365         STARFIVE_PINCTRL_PIN(PAD_GPIO1),
 366         STARFIVE_PINCTRL_PIN(PAD_GPIO2),
 367         STARFIVE_PINCTRL_PIN(PAD_GPIO3),
 368         STARFIVE_PINCTRL_PIN(PAD_GPIO4),
 369         STARFIVE_PINCTRL_PIN(PAD_GPIO5),
 370         STARFIVE_PINCTRL_PIN(PAD_GPIO6),
 371         STARFIVE_PINCTRL_PIN(PAD_GPIO7),
 372         STARFIVE_PINCTRL_PIN(PAD_GPIO8),
 373         STARFIVE_PINCTRL_PIN(PAD_GPIO9),
 374         STARFIVE_PINCTRL_PIN(PAD_GPIO10),
 375         STARFIVE_PINCTRL_PIN(PAD_GPIO11),
 376         STARFIVE_PINCTRL_PIN(PAD_GPIO12),
 377         STARFIVE_PINCTRL_PIN(PAD_GPIO13),
 378         STARFIVE_PINCTRL_PIN(PAD_GPIO14),
 379         STARFIVE_PINCTRL_PIN(PAD_GPIO15),
 380         STARFIVE_PINCTRL_PIN(PAD_GPIO16),
 381         STARFIVE_PINCTRL_PIN(PAD_GPIO17),
 382         STARFIVE_PINCTRL_PIN(PAD_GPIO18),
 383         STARFIVE_PINCTRL_PIN(PAD_GPIO19),
 384         STARFIVE_PINCTRL_PIN(PAD_GPIO20),
 385         STARFIVE_PINCTRL_PIN(PAD_GPIO21),
 386         STARFIVE_PINCTRL_PIN(PAD_GPIO22),
 387         STARFIVE_PINCTRL_PIN(PAD_GPIO23),
 388         STARFIVE_PINCTRL_PIN(PAD_GPIO24),
 389         STARFIVE_PINCTRL_PIN(PAD_GPIO25),
 390         STARFIVE_PINCTRL_PIN(PAD_GPIO26),
 391         STARFIVE_PINCTRL_PIN(PAD_GPIO27),
 392         STARFIVE_PINCTRL_PIN(PAD_GPIO28),
 393         STARFIVE_PINCTRL_PIN(PAD_GPIO29),
 394         STARFIVE_PINCTRL_PIN(PAD_GPIO30),
 395         STARFIVE_PINCTRL_PIN(PAD_GPIO31),
 396         STARFIVE_PINCTRL_PIN(PAD_GPIO32),
 397         STARFIVE_PINCTRL_PIN(PAD_GPIO33),
 398         STARFIVE_PINCTRL_PIN(PAD_GPIO34),
 399         STARFIVE_PINCTRL_PIN(PAD_GPIO35),
 400         STARFIVE_PINCTRL_PIN(PAD_GPIO36),
 401         STARFIVE_PINCTRL_PIN(PAD_GPIO37),
 402         STARFIVE_PINCTRL_PIN(PAD_GPIO38),
 403         STARFIVE_PINCTRL_PIN(PAD_GPIO39),
 404         STARFIVE_PINCTRL_PIN(PAD_GPIO40),
 405         STARFIVE_PINCTRL_PIN(PAD_GPIO41),
 406         STARFIVE_PINCTRL_PIN(PAD_GPIO42),
 407         STARFIVE_PINCTRL_PIN(PAD_GPIO43),
 408         STARFIVE_PINCTRL_PIN(PAD_GPIO44),
 409         STARFIVE_PINCTRL_PIN(PAD_GPIO45),
 410         STARFIVE_PINCTRL_PIN(PAD_GPIO46),
 411         STARFIVE_PINCTRL_PIN(PAD_GPIO47),
 412         STARFIVE_PINCTRL_PIN(PAD_GPIO48),
 413         STARFIVE_PINCTRL_PIN(PAD_GPIO49),
 414         STARFIVE_PINCTRL_PIN(PAD_GPIO50),
 415         STARFIVE_PINCTRL_PIN(PAD_GPIO51),
 416         STARFIVE_PINCTRL_PIN(PAD_GPIO52),
 417         STARFIVE_PINCTRL_PIN(PAD_GPIO53),
 418         STARFIVE_PINCTRL_PIN(PAD_GPIO54),
 419         STARFIVE_PINCTRL_PIN(PAD_GPIO55),
 420         STARFIVE_PINCTRL_PIN(PAD_GPIO56),
 421         STARFIVE_PINCTRL_PIN(PAD_GPIO57),
 422         STARFIVE_PINCTRL_PIN(PAD_GPIO58),
 423         STARFIVE_PINCTRL_PIN(PAD_GPIO59),
 424         STARFIVE_PINCTRL_PIN(PAD_GPIO60),
 425         STARFIVE_PINCTRL_PIN(PAD_GPIO61),
 426         STARFIVE_PINCTRL_PIN(PAD_GPIO62),
 427         STARFIVE_PINCTRL_PIN(PAD_GPIO63),
 428         STARFIVE_PINCTRL_PIN(PAD_SD0_CLK),
 429         STARFIVE_PINCTRL_PIN(PAD_SD0_CMD),
 430         STARFIVE_PINCTRL_PIN(PAD_SD0_DATA0),
 431         STARFIVE_PINCTRL_PIN(PAD_SD0_DATA1),
 432         STARFIVE_PINCTRL_PIN(PAD_SD0_DATA2),
 433         STARFIVE_PINCTRL_PIN(PAD_SD0_DATA3),
 434         STARFIVE_PINCTRL_PIN(PAD_SD0_DATA4),
 435         STARFIVE_PINCTRL_PIN(PAD_SD0_DATA5),
 436         STARFIVE_PINCTRL_PIN(PAD_SD0_DATA6),
 437         STARFIVE_PINCTRL_PIN(PAD_SD0_DATA7),
 438         STARFIVE_PINCTRL_PIN(PAD_SD0_STRB),
 439         STARFIVE_PINCTRL_PIN(PAD_GMAC1_MDC),
 440         STARFIVE_PINCTRL_PIN(PAD_GMAC1_MDIO),
 441         STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD0),
 442         STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD1),
 443         STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD2),
 444         STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD3),
 445         STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXDV),
 446         STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXC),
 447         STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD0),
 448         STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD1),
 449         STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD2),
 450         STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD3),
 451         STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXEN),
 452         STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXC),
 453         STARFIVE_PINCTRL_PIN(PAD_QSPI_SCLK),
 454         STARFIVE_PINCTRL_PIN(PAD_QSPI_CSn0),
 455         STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA0),
 456         STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA1),
 457         STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA2),
 458         STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA3),
 459 };
 460
 461 enum starfive_jh7110_aon_pads {
 462         PAD_TESTEN      = 0,
 463         PAD_RGPIO0      = 1,
 464         PAD_RGPIO1      = 2,
 465         PAD_RGPIO2      = 3,
 466         PAD_RGPIO3      = 4,
 467         PAD_RSTN        = 5,
 468         PAD_GMAC0_MDC   = 6,
 469         PAD_GMAC0_MDIO  = 7,
 470         PAD_GMAC0_RXD0  = 8,
 471         PAD_GMAC0_RXD1  = 9,
 472         PAD_GMAC0_RXD2  = 10,
 473         PAD_GMAC0_RXD3  = 11,
 474         PAD_GMAC0_RXDV  = 12,
 475         PAD_GMAC0_RXC   = 13,
 476         PAD_GMAC0_TXD0  = 14,
 477         PAD_GMAC0_TXD1  = 15,
 478         PAD_GMAC0_TXD2  = 16,
 479         PAD_GMAC0_TXD3  = 17,
 480         PAD_GMAC0_TXEN  = 18,
 481         PAD_GMAC0_TXC   = 19,
 482 };
 483
 484 static const struct pinctrl_pin_desc starfive_jh7110_aon_pinctrl_pads[] = {
 485         STARFIVE_PINCTRL_PIN(PAD_TESTEN),
 486         STARFIVE_PINCTRL_PIN(PAD_RGPIO0),
 487         STARFIVE_PINCTRL_PIN(PAD_RGPIO1),
 488         STARFIVE_PINCTRL_PIN(PAD_RGPIO2),
 489         STARFIVE_PINCTRL_PIN(PAD_RGPIO3),
 490         STARFIVE_PINCTRL_PIN(PAD_RSTN),
 491         STARFIVE_PINCTRL_PIN(PAD_GMAC0_MDC),
 492         STARFIVE_PINCTRL_PIN(PAD_GMAC0_MDIO),
 493         STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD0),
 494         STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD1),
 495         STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD2),
 496         STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD3),
 497         STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXDV),
 498         STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXC),
 499         STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD0),
 500         STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD1),
 501         STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD2),
 502         STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD3),
 503         STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXEN),
 504         STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXC),
 505 };
 506
 507 static void pinctrl_write_reg(void __iomem *addr, u32 mask, u32 val)
 508 {
 509         u32 value;
 510
 511         value = readl_relaxed(addr);
 512         value &= ~mask;
 513         value |= (val & mask);
 514         writel_relaxed(value, addr);
 515 }
 516
 517 uint32_t pinctrl_get_reg(void __iomem *addr, u32 shift, u32 mask)
 518 {
 519         u32 tmp;
 520
 521         tmp = readl_relaxed(addr);
 522         tmp = (tmp & mask) >> shift;
 523         return tmp;
 524 }
 525
 526 void pinctrl_set_reg(void __iomem *addr, u32 data, u32 shift, u32 mask)
 527 {
 528         u32 tmp;
 529
 530         tmp = readl_relaxed(addr);
 531         tmp &= ~mask;
 532         tmp |= (data<<shift) & mask;
 533         writel_relaxed(tmp, addr);
 534 }
 535
 536 static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
 537 {
 538         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 539
 540         return container_of(gc, struct starfive_pinctrl, gc);
 541 }
 542
 543 static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
 544 {
 545         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 546
 547         return container_of(gc, struct starfive_pinctrl, gc);
 548 }
 549
 550 static int starfive_jh7110_sys_direction_input(struct gpio_chip *gc,
 551                                                         unsigned int offset)
 552 {
 553         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
 554         unsigned long flags;
 555         unsigned int v;
 556
 557         if (offset >= gc->ngpio)
 558                 return -EINVAL;
 559
 560         raw_spin_lock_irqsave(&chip->lock, flags);
 561         v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG +
 562                         (offset & ~0x3));
 563         v &= ~(0x3f << ((offset & 0x3) * 8));
 564         v |= 1 << ((offset & 0x3) * 8);
 565         writel_relaxed(v, chip->padctl_base + GPIO_DOEN_X_REG +
 566                         (offset & ~0x3));
 567         raw_spin_unlock_irqrestore(&chip->lock, flags);
 568
 569         return 0;
 570 }
 571
 572 static int starfive_jh7110_sys_direction_output(struct gpio_chip *gc,
 573                 unsigned int offset,
 574                 int value)
 575 {
 576         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
 577         unsigned long flags;
 578         unsigned int v;
 579
 580         if (offset >= gc->ngpio)
 581                 return -EINVAL;
 582
 583         raw_spin_lock_irqsave(&chip->lock, flags);
 584         v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG +
 585                         (offset & ~0x3));
 586         v &= ~(0x3f << ((offset & 0x3) * 8));
 587         writel_relaxed(v, chip->padctl_base + GPIO_DOEN_X_REG +
 588                         (offset & ~0x3));
 589
 590         v = readl_relaxed(chip->padctl_base + GPIO_DOUT_X_REG +
 591                         (offset & ~0x3));
 592         v &= ~(0x7f << ((offset & 0x3) * 8));
 593         v |= value << ((offset & 0x3) * 8);
 594         writel_relaxed(v, chip->padctl_base + GPIO_DOUT_X_REG +
 595                         (offset & ~0x3));
 596         raw_spin_unlock_irqrestore(&chip->lock, flags);
 597
 598         return 0;
 599 }
 600
 601 static int starfive_jh7110_sys_get_direction(struct gpio_chip *gc,
 602                 unsigned int offset)
 603 {
 604         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
 605         unsigned int v;
 606
 607         if (offset >= gc->ngpio)
 608                 return -EINVAL;
 609
 610         v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG +
 611                         (offset & ~0x3));
 612         return !!(v & (0x3f << ((offset & 0x3) * 8)));
 613 }
 614
 615 static int starfive_jh7110_sys_get_value(struct gpio_chip *gc,
 616                 unsigned int offset)
 617 {
 618         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
 619         int value;
 620         int tmp;
 621
 622         if (offset >= gc->ngpio)
 623                 return -EINVAL;
 624
 625         if (offset < GPIO_NUM_PER_REG) {
 626                 value = readl_relaxed(chip->padctl_base + GPIO_DIN_LOW);
 627                 tmp = 0;
 628         } else {
 629                 value = readl_relaxed(chip->padctl_base + GPIO_DIN_HIGH);
 630                 tmp = GPIO_NUM_PER_REG;
 631         }
 632         return (value >> (offset - tmp)) & 0x1;
 633 }
 634
 635 static void starfive_jh7110_sys_set_value(struct gpio_chip *gc,
 636                 unsigned int offset,
 637                 int value)
 638 {
 639         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
 640         unsigned long flags;
 641         unsigned int v;
 642
 643         if (offset >= gc->ngpio)
 644                 return;
 645
 646         raw_spin_lock_irqsave(&chip->lock, flags);
 647         v = readl_relaxed(chip->padctl_base + GPIO_DOUT_X_REG +
 648                         (offset & ~0x3));
 649         v &= ~(0x7f << ((offset & 0x3) * 8));
 650         v |= value << ((offset & 0x3) * 8);
 651         writel_relaxed(v, chip->padctl_base + GPIO_DOUT_X_REG +
 652                         (offset & ~0x3));
 653         raw_spin_unlock_irqrestore(&chip->lock, flags);
 654 }
 655
 656 static int starfive_jh7110_sys_irq_set_type(struct irq_data *d,
 657                 unsigned int trigger)
 658 {
 659         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
 660         irq_hw_number_t gpio = irqd_to_hwirq(d);
 661         void __iomem *base = sfp->padctl_base +
 662                         OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
 663         u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
 664         u32 irq_type, edge_both, polarity;
 665         unsigned long flags;
 666
 667         switch (trigger) {
 668         case IRQ_TYPE_LEVEL_HIGH:
 669                 irq_type  = 0;    /* 0: level triggered */
 670                 edge_both = 0;    /* 0: ignored */
 671                 polarity  = 0;    /* 0: high level */
 672                 break;
 673         case IRQ_TYPE_LEVEL_LOW:
 674                 irq_type  = 0;    /* 0: level triggered */
 675                 edge_both = 0;    /* 0: ignored */
 676                 polarity  = 1;    /* 1: low level */
 677                 break;
 678         case IRQ_TYPE_EDGE_BOTH:
 679                 irq_type  = mask; /* 1: edge triggered */
 680                 edge_both = mask; /* 1: both edges */
 681                 polarity  = 0;    /* 0: ignored */
 682                 break;
 683         case IRQ_TYPE_EDGE_RISING:
 684                 irq_type  = mask; /* 1: edge triggered */
 685                 edge_both = 0;    /* 0: single edge */
 686                 polarity  = mask; /* 1: rising edge */
 687                 break;
 688         case IRQ_TYPE_EDGE_FALLING:
 689                 irq_type  = mask; /* 1: edge triggered */
 690                 edge_both = 0;    /* 0: single edge */
 691                 polarity  = 0;    /* 0: falling edge */
 692                 break;
 693         }
 694         if (trigger & IRQ_TYPE_EDGE_BOTH)
 695                 irq_set_handler_locked(d, handle_edge_irq);
 696         else
 697                 irq_set_handler_locked(d, handle_level_irq);
 698
 699         raw_spin_lock_irqsave(&sfp->lock, flags);
 700         irq_type |= readl_relaxed(base + GPIO_IS_LOW) & ~mask;
 701         writel_relaxed(irq_type, base + GPIO_IS_LOW);
 702         edge_both |= readl_relaxed(base + GPIO_IBE_LOW) & ~mask;
 703         writel_relaxed(edge_both, base + GPIO_IBE_LOW);
 704         polarity |= readl_relaxed(base + GPIO_IEV_LOW) & ~mask;
 705         writel_relaxed(polarity, base + GPIO_IEV_LOW);
 706         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 707
 708         sfp->trigger[gpio] = trigger;
 709         return 0;
 710 }
 711
 712 /* chained_irq_{enter,exit} already mask the parent */
 713 static void starfive_jh7110_sys_irq_mask(struct irq_data *d)
 714 {
 715         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
 716         irq_hw_number_t gpio = irqd_to_hwirq(d);
 717         void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
 718                         OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
 719         u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
 720         unsigned long flags;
 721         u32 value;
 722
 723         if (gpio < 0 || gpio >= sfp->gc.ngpio)
 724                 return;
 725
 726         raw_spin_lock_irqsave(&sfp->lock, flags);
 727         value = readl_relaxed(ie) & ~mask;
 728         writel_relaxed(value, ie);
 729         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 730 }
 731
 732 static void starfive_jh7110_sys_irq_unmask(struct irq_data *d)
 733 {
 734         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
 735         irq_hw_number_t gpio = irqd_to_hwirq(d);
 736         void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
 737                         OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
 738         u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
 739         unsigned long flags;
 740         u32 value;
 741
 742         if (gpio < 0 || gpio >= sfp->gc.ngpio)
 743                 return;
 744
 745         raw_spin_lock_irqsave(&sfp->lock, flags);
 746         value = readl_relaxed(ie) | mask;
 747         writel_relaxed(value, ie);
 748         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 749 }
 750
 751 static void starfive_jh7110_sys_irq_ack(struct irq_data *d)
 752 {
 753         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
 754         irq_hw_number_t gpio = irqd_to_hwirq(d);
 755         void __iomem *ic = sfp->padctl_base + GPIO_IC_LOW +
 756                         OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
 757         u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
 758         unsigned long flags;
 759         u32 value;
 760
 761         if (gpio < 0 || gpio >= sfp->gc.ngpio)
 762                 return;
 763
 764         raw_spin_lock_irqsave(&sfp->lock, flags);
 765         value = readl_relaxed(ic) & ~mask;
 766         writel_relaxed(value, ic);
 767         writel_relaxed(value | mask, ic);
 768         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 769 }
 770
 771 static void starfive_jh7110_sys_irq_mask_ack(struct irq_data *d)
 772 {
 773         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
 774         irq_hw_number_t gpio = irqd_to_hwirq(d);
 775         void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
 776                         OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
 777         void __iomem *ic = sfp->padctl_base + GPIO_IC_LOW +
 778                         OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
 779         u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
 780         unsigned long flags;
 781         u32 value;
 782
 783         if (gpio < 0 || gpio >= sfp->gc.ngpio)
 784                 return;
 785
 786         raw_spin_lock_irqsave(&sfp->lock, flags);
 787         value = readl_relaxed(ie) & ~mask;
 788         writel_relaxed(value, ie);
 789
 790         value = readl_relaxed(ic) & ~mask;
 791         writel_relaxed(value, ic);
 792         writel_relaxed(value | mask, ic);
 793         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 794 }
 795
 796 static struct irq_chip starfive_jh7110_sys_irqchip = {
 797         .name           = "starfive_jh7110_sys-gpio",
 798         .irq_ack        = starfive_jh7110_sys_irq_ack,
 799         .irq_mask_ack   = starfive_jh7110_sys_irq_mask_ack,
 800         .irq_set_type   = starfive_jh7110_sys_irq_set_type,
 801         .irq_mask       = starfive_jh7110_sys_irq_mask,
 802         .irq_unmask     = starfive_jh7110_sys_irq_unmask,
 803 };
 804
 805 static void starfive_jh7110_sys_irq_handler(struct irq_desc *desc)
 806 {
 807         struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
 808         struct irq_chip *chip = irq_desc_get_chip(desc);
 809         unsigned long mis;
 810         unsigned int pin;
 811
 812         chained_irq_enter(chip, desc);
 813
 814         mis = readl_relaxed(sfp->padctl_base + GPIO_MIS_LOW);
 815         for_each_set_bit(pin, &mis, GPIO_NUM_PER_REG)
 816                 generic_handle_domain_irq(sfp->gc.irq.domain, pin);
 817
 818         mis = readl_relaxed(sfp->padctl_base + GPIO_MIS_HIGH);
 819         for_each_set_bit(pin, &mis, GPIO_NUM_PER_REG)
 820                 generic_handle_domain_irq(sfp->gc.irq.domain,
 821                         pin + GPIO_NUM_PER_REG);
 822
 823         chained_irq_exit(chip, desc);
 824 }
 825
 826 static int starfive_jh7110_sys_init_hw(struct gpio_chip *gc)
 827 {
 828         struct starfive_pinctrl *sfp = container_of(gc,
 829                         struct starfive_pinctrl, gc);
 830
 831         /* mask all GPIO interrupts */
 832         writel_relaxed(0, sfp->padctl_base + GPIO_IE_LOW);
 833         writel_relaxed(0, sfp->padctl_base + GPIO_IE_HIGH);
 834         /* clear edge interrupt flags */
 835         writel_relaxed(0U, sfp->padctl_base + GPIO_IC_LOW);
 836         writel_relaxed(0U, sfp->padctl_base + GPIO_IC_HIGH);
 837         writel_relaxed(~0U, sfp->padctl_base + GPIO_IC_LOW);
 838         writel_relaxed(~0U, sfp->padctl_base + GPIO_IC_HIGH);
 839         /* enable GPIO interrupts */
 840         writel_relaxed(1, sfp->padctl_base + GPIO_EN);
 841         return 0;
 842 }
 843
 844 static int starfive_sys_add_pin_ranges(struct gpio_chip *gc)
 845 {
 846         struct starfive_pinctrl *sfp = container_of(gc,
 847                         struct starfive_pinctrl, gc);
 848
 849         sfp->gpios.name = sfp->gc.label;
 850         sfp->gpios.base = sfp->gc.base;
 851         /*
 852          * sfp->gpios.pin_base depends on the chosen signal group
 853          * and is set in starfive_probe()
 854          */
 855         sfp->gpios.npins = SYS_GPIO_NUM;
 856         sfp->gpios.gc = &sfp->gc;
 857         pinctrl_add_gpio_range(sfp->pctl_dev, &sfp->gpios);
 858         return 0;
 859 }
 860
 861 static int starfive_jh7110_sys_gpio_register(struct platform_device *pdev,
 862                 struct starfive_pinctrl *pctl)
 863 {
 864         struct device *dev = &pdev->dev;
 865         int ret, ngpio;
 866         int loop;
 867
 868         ngpio = SYS_GPIO_NUM;
 869
 870         pctl->gc.direction_input = starfive_jh7110_sys_direction_input;
 871         pctl->gc.direction_output = starfive_jh7110_sys_direction_output;
 872         pctl->gc.get_direction = starfive_jh7110_sys_get_direction;
 873         pctl->gc.get = starfive_jh7110_sys_get_value;
 874         pctl->gc.set = starfive_jh7110_sys_set_value;
 875         pctl->gc.add_pin_ranges = starfive_sys_add_pin_ranges;
 876         pctl->gc.base = 0;
 877         pctl->gc.ngpio = ngpio;
 878         pctl->gc.label = dev_name(dev);
 879         pctl->gc.parent = dev;
 880         pctl->gc.owner = THIS_MODULE;
 881         pctl->enabled = 0;
 882
 883         platform_set_drvdata(pdev, pctl);
 884
 885         starfive_jh7110_sys_irqchip.parent_device = dev;
 886         starfive_jh7110_sys_irqchip.name = pctl->gc.label;
 887
 888         pctl->gc.irq.chip = &starfive_jh7110_sys_irqchip;
 889         pctl->gc.irq.parent_handler = starfive_jh7110_sys_irq_handler;
 890         pctl->gc.irq.num_parents = 1;
 891         pctl->gc.irq.parents = devm_kcalloc(dev, pctl->gc.irq.num_parents,
 892                         sizeof(*pctl->gc.irq.parents), GFP_KERNEL);
 893         if (!pctl->gc.irq.parents)
 894                 return -ENOMEM;
 895         pctl->gc.irq.default_type = IRQ_TYPE_NONE;
 896         pctl->gc.irq.handler = handle_bad_irq;
 897         pctl->gc.irq.init_hw = starfive_jh7110_sys_init_hw;
 898
 899         if (IS_ENABLED(CONFIG_PM))
 900                 pm_runtime_enable(dev);
 901
 902         ret = platform_get_irq(pdev, 0);
 903         if (ret < 0)
 904                 return ret;
 905         pctl->gc.irq.parents[0] = ret;
 906
 907         ret = devm_gpiochip_add_data(dev, &pctl->gc, pctl);
 908         if (ret)
 909                 return dev_err_probe(dev, ret,
 910                                 "could not register gpiochip\n");
 911
 912         for (loop = 0; loop < MAX_GPIO; loop++) {
 913                 unsigned int v;
 914
 915                 v = readl_relaxed(pctl->padctl_base +
 916                                 GPIO_INPUT_ENABLE_X_REG + (loop << 2));
 917                 v |= 0x1;
 918                 writel_relaxed(v, pctl->padctl_base +
 919                                 GPIO_INPUT_ENABLE_X_REG + (loop << 2));
 920         }
 921
 922         dev_info(dev, "SiFive GPIO chip registered %d GPIOs\n", ngpio);
 923
 924         return 0;
 925 }
 926
 927 static int starfive_jh7110_pinconf_get(struct pinctrl_dev *pctldev,
 928                 unsigned int pin_id,
 929                 unsigned long *config)
 930 {
 931         struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 932         const struct starfive_pinctrl_soc_info *info = pctl->info;
 933         const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
 934         u32 value;
 935
 936         if (pin_reg->io_conf_reg == -1) {
 937                 dev_err(pctl->dev,
 938                         "Pin(%s) does not support config function\n",
 939                         info->pins[pin_id].name);
 940                 return -EINVAL;
 941         }
 942
 943         value = readl_relaxed(pctl->padctl_base + pin_reg->io_conf_reg);
 944         *config = value & 0xff;
 945         return 0;
 946 }
 947
 948 static int starfive_jh7110_pinconf_set(struct pinctrl_dev *pctldev,
 949                 unsigned int pin_id, unsigned long *configs,
 950                 unsigned int num_configs)
 951 {
 952         struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 953         const struct starfive_pinctrl_soc_info *info = pctl->info;
 954         const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
 955         int i;
 956         u32 value;
 957         unsigned long flags;
 958
 959         if (pin_reg->io_conf_reg == -1) {
 960                 dev_err(pctl->dev,
 961                         "Pin(%s) does not support config function\n",
 962                         info->pins[pin_id].name);
 963                 return -EINVAL;
 964         }
 965
 966         raw_spin_lock_irqsave(&pctl->lock, flags);
 967         for (i = 0; i < num_configs; i++) {
 968                 value = readl_relaxed(pctl->padctl_base +
 969                                 pin_reg->io_conf_reg);
 970                 value = value|(configs[i] & 0xFF);
 971                 writel_relaxed(value, pctl->padctl_base +
 972                                 pin_reg->io_conf_reg);
 973         }
 974         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 975
 976         return 0;
 977 }
 978
 979 static int starfive_jh7110_sys_pmx_set_one_pin_mux(struct starfive_pinctrl *pctl,
 980                 struct starfive_pin *pin)
 981 {
 982         const struct starfive_pinctrl_soc_info *info = pctl->info;
 983         struct starfive_pin_config *pin_config = &pin->pin_config;
 984         const struct starfive_pin_reg *pin_reg;
 985         unsigned int gpio, pin_id;
 986         int i;
 987         unsigned long flags;
 988         int n, shift;
 989
 990         gpio = pin->pin_config.gpio_num;
 991         pin_id = pin->pin;
 992         pin_reg = &pctl->pin_regs[pin_id];
 993
 994         raw_spin_lock_irqsave(&pctl->lock, flags);
 995         if (pin_reg->func_sel_reg != -1) {
 996                 pinctrl_set_reg(pctl->padctl_base + pin_reg->func_sel_reg,
 997                         pin_config->pinmux_func, pin_reg->func_sel_shift,
 998                         pin_reg->func_sel_mask);
 999         }
1000
1001         shift = (gpio & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT;
1002         if (pin_reg->gpo_dout_reg != -1) {
1003                 pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
1004                                 0x7F<<shift, pin_config->gpio_dout<<shift);
1005         }
1006
1007         if (pin_reg->gpo_doen_reg != -1) {
1008                 pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
1009                                 0x3F<<shift, pin_config->gpio_doen<<shift);
1010         }
1011
1012         for (i = 0; i < pin_config->gpio_din_num; i++) {
1013                 n = pin_config->gpio_din_reg[i] >> 2;
1014                 shift = (pin_config->gpio_din_reg[i] & 3) << 3;
1015                 pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
1016                                         0x7F<<shift, (gpio+2)<<shift);
1017         }
1018
1019         if (pin_reg->syscon_reg != -1) {
1020                 pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
1021                                 pin_config->syscon, PADCFG_PAD_GMAC_SYSCON_SHIFT,
1022                                 PADCFG_PAD_GMAC_SYSCON_MASK);
1023         }
1024
1025         if (pin_reg->pad_sel_reg != -1) {
1026                 pinctrl_set_reg(pctl->padctl_base + pin_reg->pad_sel_reg,
1027                         pin_config->padmux_func, pin_reg->pad_sel_shift,
1028                         pin_reg->pad_sel_mask);
1029         }
1030         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1031
1032         return 0;
1033 }
1034
1035
1036 static void starfive_jh7110_sys_parse_pin_config(
1037                 struct starfive_pinctrl *pctl,
1038                 unsigned int *pins_id,
1039                 struct starfive_pin *pin_data,
1040                 const __be32 *list_p,
1041                 struct device_node *np)
1042 {
1043         const struct starfive_pinctrl_soc_info *info = pctl->info;
1044         struct starfive_pin_reg *pin_reg;
1045         const __be32 *list = list_p;
1046         const __be32 *list_din;
1047         int size;
1048         int size_din;
1049         int pin_size;
1050         u32 value;
1051         int i;
1052         int n;
1053
1054         pin_size = 4;
1055         *pins_id = be32_to_cpu(*list);
1056         pin_reg = &pctl->pin_regs[*pins_id];
1057         pin_data->pin = *pins_id;
1058
1059         if (pin_data->pin > PAD_QSPI_DATA3) {
1060                 dev_err(pctl->dev, "err pin num\n");
1061                 return;
1062         }
1063
1064         if (pin_data->pin < PAD_GMAC1_MDC) {
1065                 pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET)
1066                         + SYS_GPO_PDA_0_74_CFG_BASE_REG;
1067         } else if (pin_data->pin > PAD_GMAC1_TXC) {
1068                 pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET)
1069                         + SYS_GPO_PDA_89_94_CFG_BASE_REG;
1070         }
1071
1072         if (!of_property_read_u32(np, "starfive,pin-ioconfig", &value))
1073                 pin_data->pin_config.io_config = value;
1074
1075         list = of_get_property(np, "starfive,pinmux", &size);
1076         if (list) {
1077                 pin_reg->func_sel_reg = be32_to_cpu(*list++);
1078                 pin_reg->func_sel_shift = be32_to_cpu(*list++);
1079                 pin_reg->func_sel_mask = be32_to_cpu(*list++);
1080                 pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
1081         }
1082
1083         list = of_get_property(np, "starfive,padmux", &size);
1084         if (list) {
1085                 pin_reg->pad_sel_reg = be32_to_cpu(*list++);
1086                 pin_reg->pad_sel_shift = be32_to_cpu(*list++);
1087                 pin_reg->pad_sel_mask = be32_to_cpu(*list++);
1088                 pin_data->pin_config.padmux_func = be32_to_cpu(*list++);
1089         }
1090
1091         list = of_get_property(np, "starfive,pin-syscon", &size);
1092         if (list) {
1093                 pin_reg->syscon_reg = be32_to_cpu(*list++);
1094                 pin_data->pin_config.syscon = be32_to_cpu(*list++);
1095         }
1096
1097         if (pin_data->pin < PAD_SD0_CLK) {
1098                 pin_data->pin_config.gpio_num = pin_data->pin;
1099                 n = pin_data->pin_config.gpio_num >> GPIO_NUM_SHIFT;
1100
1101                 if (!of_property_read_u32(np, "starfive,pin-gpio-dout", &value)) {
1102                         pin_data->pin_config.gpio_dout = value;
1103                         pin_reg->gpo_dout_reg = info->dout_reg_base + n * 4;
1104                 }
1105
1106                 if (!of_property_read_u32(np, "starfive,pin-gpio-doen", &value)) {
1107                         pin_data->pin_config.gpio_doen = value;
1108                         pin_reg->gpo_doen_reg = info->doen_reg_base + n * 4;
1109                 }
1110
1111                 list_din = of_get_property(np, "starfive,pin-gpio-din", &size_din);
1112                 if (list_din) {
1113                         if (!size_din || size_din % pin_size) {
1114                                 dev_err(pctl->dev,
1115                                         "Invalid starfive,pin-gpio-din property in node\n");
1116                                 return;
1117                         }
1118
1119                         pin_data->pin_config.gpio_din_num = size_din / pin_size;
1120                         pin_data->pin_config.gpio_din_reg = devm_kcalloc(pctl->dev,
1121                                         pin_data->pin_config.gpio_din_num,
1122                                         sizeof(s32),
1123                                         GFP_KERNEL);
1124
1125                         for (i = 0; i < pin_data->pin_config.gpio_din_num; i++) {
1126                                 value = be32_to_cpu(*list_din++);
1127                                 pin_data->pin_config.gpio_din_reg[i] = value;
1128                         }
1129                 }
1130         }
1131 }
1132
1133 static const struct starfive_pinctrl_soc_info starfive_jh7110_sys_pinctrl_info = {
1134         .pins = starfive_jh7110_sys_pinctrl_pads,
1135         .npins = ARRAY_SIZE(starfive_jh7110_sys_pinctrl_pads),
1136         .flags = 1,
1137         .dout_reg_base = SYS_GPO_DOUT_CFG_BASE_REG,
1138         .doen_reg_base = SYS_GPO_DOEN_CFG_BASE_REG,
1139         .din_reg_base = SYS_GPI_DIN_CFG_BASE_REG,
1140         .starfive_pinconf_get = starfive_jh7110_pinconf_get,
1141         .starfive_pinconf_set = starfive_jh7110_pinconf_set,
1142         .starfive_pmx_set_one_pin_mux = starfive_jh7110_sys_pmx_set_one_pin_mux,
1143         .starfive_gpio_register = starfive_jh7110_sys_gpio_register,
1144         .starfive_pinctrl_parse_pin = starfive_jh7110_sys_parse_pin_config,
1145 };
1146
1147 static int starfive_jh7110_aon_pmx_set_one_pin_mux(
1148                                         struct starfive_pinctrl *pctl,
1149                                         struct starfive_pin *pin)
1150 {
1151         const struct starfive_pinctrl_soc_info *info = pctl->info;
1152         struct starfive_pin_config *pin_config = &pin->pin_config;
1153         const struct starfive_pin_reg *pin_reg;
1154         unsigned int gpio, pin_id;
1155         int i;
1156         unsigned long flags;
1157         int n, shift;
1158
1159         gpio = pin->pin_config.gpio_num;
1160         pin_id = pin->pin;
1161         pin_reg = &pctl->pin_regs[pin_id];
1162
1163         raw_spin_lock_irqsave(&pctl->lock, flags);
1164         if (pin_reg->func_sel_reg != -1) {
1165                 pinctrl_set_reg(pctl->padctl_base + pin_reg->func_sel_reg,
1166                                 pin_config->pinmux_func,
1167                                 pin_reg->func_sel_shift,
1168                                 pin_reg->func_sel_mask);
1169         }
1170
1171         shift = (gpio & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT;
1172         if (pin_reg->gpo_dout_reg != -1) {
1173                 pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
1174                                 0xF << shift,
1175                                 pin_config->gpio_dout<<shift);
1176         }
1177
1178         if (pin_reg->gpo_doen_reg != -1) {
1179                 pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
1180                                 0x7 << shift,
1181                                 pin_config->gpio_doen << shift);
1182         }
1183
1184         for (i = 0; i < pin_config->gpio_din_num; i++) {
1185                 n = pin_config->gpio_din_reg[i] >> 2;
1186                 shift = (pin_config->gpio_din_reg[i] & 3) << 3;
1187                 pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
1188                                 0x7 << shift,
1189                                 (gpio+2) << shift);
1190         }
1191
1192         if (pin_reg->syscon_reg != -1) {
1193                 pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
1194                                 pin_config->syscon,
1195                                 PADCFG_PAD_GMAC_SYSCON_SHIFT,
1196                                 PADCFG_PAD_GMAC_SYSCON_MASK);
1197         }
1198
1199         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1200
1201         return 0;
1202 }
1203
1204
1205 static void starfive_jh7110_aon_parse_pin_config(
1206                 struct starfive_pinctrl *pctl, unsigned int *pins_id,
1207                 struct starfive_pin *pin_data, const __be32 *list_p,
1208                 struct device_node *np)
1209 {
1210         const struct starfive_pinctrl_soc_info *info = pctl->info;
1211         struct starfive_pin_reg *pin_reg;
1212         const __be32 *list = list_p;
1213         const __be32 *list_din;
1214         int size;
1215         int size_din;
1216         int pin_size;
1217         u32 value;
1218         int i;
1219
1220         pin_size = 4;
1221         *pins_id = be32_to_cpu(*list);
1222         pin_reg = &pctl->pin_regs[*pins_id];
1223         pin_data->pin = *pins_id;
1224
1225         if (pin_data->pin > PAD_GMAC0_TXC) {
1226                 dev_err(pctl->dev, "err pin num\n");
1227                 return;
1228         }
1229
1230         if (pin_data->pin < PAD_GMAC0_MDC) {
1231                 pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET) +
1232                                         AON_GPO_PDA_0_5_CFG_BASE_REG;
1233         }
1234
1235         if (!of_property_read_u32(np, "starfive,pin-ioconfig", &value))
1236                 pin_data->pin_config.io_config = value;
1237
1238         list = of_get_property(np, "starfive,pinmux", &size);
1239         if (list) {
1240                 pin_reg->func_sel_reg = be32_to_cpu(*list++);
1241                 pin_reg->func_sel_shift = be32_to_cpu(*list++);
1242                 pin_reg->func_sel_mask = be32_to_cpu(*list++);
1243                 pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
1244         }
1245
1246         list = of_get_property(np, "starfive,pin-syscon", &size);
1247         if (list) {
1248                 pin_reg->syscon_reg = be32_to_cpu(*list++);
1249                 pin_data->pin_config.syscon = be32_to_cpu(*list++);
1250         }
1251
1252         if ((pin_data->pin >= PAD_RGPIO0) && (pin_data->pin <= PAD_RGPIO3)) {
1253                 pin_data->pin_config.gpio_num = pin_data->pin - 1;
1254                 pin_reg->gpo_dout_reg = info->dout_reg_base;
1255                 pin_reg->gpo_doen_reg = info->doen_reg_base;
1256
1257                 if (!of_property_read_u32(np, "starfive,pin-gpio-dout", &value))
1258                         pin_data->pin_config.gpio_dout = value;
1259
1260                 if (!of_property_read_u32(np, "starfive,pin-gpio-doen", &value))
1261                         pin_data->pin_config.gpio_doen = value;
1262
1263                 list_din = of_get_property(np, "starfive,pin-gpio-din", &size_din);
1264                 if (list_din) {
1265                         if (!size_din || size_din % pin_size) {
1266                                 dev_err(pctl->dev,
1267                                         "Invalid starfive,pin-gpio-din property in node\n");
1268                                 return;
1269                         }
1270                         pin_data->pin_config.gpio_din_num = size_din / pin_size;
1271                         pin_data->pin_config.gpio_din_reg = devm_kcalloc(pctl->dev,
1272                                         pin_data->pin_config.gpio_din_num,
1273                                         sizeof(s32),
1274                                         GFP_KERNEL);
1275                         for (i = 0; i < pin_data->pin_config.gpio_din_num; i++) {
1276                                 value = be32_to_cpu(*list_din++);
1277                                 pin_data->pin_config.gpio_din_reg[i] = value;
1278                         }
1279                 }
1280         }
1281 }
1282
1283 static int starfive_jh7110_aon_direction_input(struct gpio_chip *gc,
1284                 unsigned int offset)
1285 {
1286         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
1287         unsigned long flags;
1288         unsigned int v;
1289
1290
1291         if (offset < 0 || offset >= gc->ngpio)
1292                 return -EINVAL;
1293
1294         raw_spin_lock_irqsave(&chip->lock, flags);
1295         v = readl_relaxed(chip->padctl_base + AON_GPO_DOEN_CFG_BASE_REG);
1296         v &= ~(0x07 << ((offset & 0x3) * 8));
1297         v |= 1 << ((offset & 0x3) * 8);
1298         writel_relaxed(v, chip->padctl_base + AON_GPO_DOEN_CFG_BASE_REG);
1299         raw_spin_unlock_irqrestore(&chip->lock, flags);
1300
1301         return 0;
1302 }
1303
1304 static int starfive_jh7110_aon_direction_output(struct gpio_chip *gc,
1305                 unsigned int offset,
1306                 int value)
1307 {
1308         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
1309         unsigned long flags;
1310         unsigned int v;
1311
1312         if (offset < 0 || offset >= gc->ngpio)
1313                 return -EINVAL;
1314
1315         raw_spin_lock_irqsave(&chip->lock, flags);
1316         v = readl_relaxed(chip->padctl_base + AON_GPO_DOEN_CFG_BASE_REG);
1317         v &= ~(0x07 << ((offset & 0x3) * 8));
1318         writel_relaxed(v, chip->padctl_base + AON_GPO_DOEN_CFG_BASE_REG);
1319
1320         v = readl_relaxed(chip->padctl_base + AON_GPO_DOUT_CFG_BASE_REG);
1321         v &= ~(0x0f << ((offset & 0x3) * 8));
1322         v |= value << ((offset & 0x3) * 8);
1323         writel_relaxed(v, chip->padctl_base + AON_GPO_DOUT_CFG_BASE_REG);
1324         raw_spin_unlock_irqrestore(&chip->lock, flags);
1325
1326         return 0;
1327 }
1328
1329 static int starfive_jh7110_aon_get_direction(struct gpio_chip *gc,
1330                 unsigned int offset)
1331 {
1332         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
1333         unsigned int v;
1334
1335         if (offset < 0 || offset >= gc->ngpio)
1336                 return -EINVAL;
1337
1338         v = readl_relaxed(chip->padctl_base + AON_GPO_DOEN_CFG_BASE_REG);
1339         return !!(v & (0x07 << ((offset & 0x3) * 8)));
1340 }
1341
1342 static int starfive_jh7110_aon_get_value(struct gpio_chip *gc,
1343                 unsigned int offset)
1344 {
1345         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
1346         int value;
1347
1348         if (offset < 0 || offset >= gc->ngpio)
1349                 return -EINVAL;
1350
1351         value = readl_relaxed(chip->padctl_base + AON_GPIO_DIN_REG);
1352         return (value >> offset) & 0x1;
1353 }
1354
1355 static void starfive_jh7110_aon_set_value(struct gpio_chip *gc,
1356                 unsigned int offset, int value)
1357 {
1358         struct starfive_pinctrl *chip = gpiochip_get_data(gc);
1359         unsigned long flags;
1360         unsigned int v;
1361
1362         if (offset < 0 || offset >= gc->ngpio)
1363                 return;
1364
1365         raw_spin_lock_irqsave(&chip->lock, flags);
1366         v = readl_relaxed(chip->padctl_base + AON_GPO_DOUT_CFG_BASE_REG);
1367         v &= ~(0x0f << ((offset & 0x3) * 8));
1368         v |= value << ((offset & 0x3) * 8);
1369         writel_relaxed(v, chip->padctl_base + AON_GPO_DOUT_CFG_BASE_REG);
1370         raw_spin_unlock_irqrestore(&chip->lock, flags);
1371 }
1372
1373 static void starfive_jh7110_aon_irq_handler(struct irq_desc *desc)
1374 {
1375         struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
1376         struct irq_chip *chip = irq_desc_get_chip(desc);
1377         unsigned long mis;
1378         unsigned int pin;
1379
1380         chained_irq_enter(chip, desc);
1381
1382         mis = readl_relaxed(sfp->padctl_base + AON_GPIO_MIS_REG);
1383         for_each_set_bit(pin, &mis, 4)
1384                 generic_handle_domain_irq(sfp->gc.irq.domain, pin);
1385
1386         chained_irq_exit(chip, desc);
1387 }
1388
1389 static int starfive_jh7110_aon_init_hw(struct gpio_chip *gc)
1390 {
1391         struct starfive_pinctrl *sfp = container_of(gc,
1392                         struct starfive_pinctrl, gc);
1393
1394         /* mask all GPIO interrupts */
1395         writel_relaxed(0, sfp->padctl_base + AON_GPIO_IE_REG);
1396         /* clear edge interrupt flags */
1397         writel_relaxed(0x00U, sfp->padctl_base + AON_GPIO_IC_REG);
1398         writel_relaxed(0x0fU, sfp->padctl_base + AON_GPIO_IC_REG);
1399         /* enable GPIO interrupts */
1400         writel_relaxed(1, sfp->padctl_base + AON_GPIO_EN_REG);
1401         return 0;
1402 }
1403
1404 static int starfive_jh7110_aon_irq_set_type(struct irq_data *d,
1405                 unsigned int trigger)
1406 {
1407         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1408         irq_hw_number_t gpio = irqd_to_hwirq(d);
1409         void __iomem *base = sfp->padctl_base;
1410         u32 mask = BIT(gpio);
1411         u32 irq_type, edge_both, polarity;
1412         unsigned long flags;
1413
1414         switch (trigger) {
1415         case IRQ_TYPE_LEVEL_HIGH:
1416                 irq_type  = 0;    /* 0: level triggered */
1417                 edge_both = 0;    /* 0: ignored */
1418                 polarity  = 0;    /* 0: high level */
1419                 break;
1420         case IRQ_TYPE_LEVEL_LOW:
1421                 irq_type  = 0;    /* 0: level triggered */
1422                 edge_both = 0;    /* 0: ignored */
1423                 polarity  = 1;    /* 1: low level */
1424                 break;
1425         case IRQ_TYPE_EDGE_BOTH:
1426                 irq_type  = mask; /* 1: edge triggered */
1427                 edge_both = mask; /* 1: both edges */
1428                 polarity  = 0;    /* 0: ignored */
1429                 break;
1430         case IRQ_TYPE_EDGE_RISING:
1431                 irq_type  = mask; /* 1: edge triggered */
1432                 edge_both = 0;    /* 0: single edge */
1433                 polarity  = mask; /* 1: rising edge */
1434                 break;
1435         case IRQ_TYPE_EDGE_FALLING:
1436                 irq_type  = mask; /* 1: edge triggered */
1437                 edge_both = 0;    /* 0: single edge */
1438                 polarity  = 0;    /* 0: falling edge */
1439                 break;
1440         }
1441         if (trigger & IRQ_TYPE_EDGE_BOTH)
1442                 irq_set_handler_locked(d, handle_edge_irq);
1443         else
1444                 irq_set_handler_locked(d, handle_level_irq);
1445
1446         raw_spin_lock_irqsave(&sfp->lock, flags);
1447         irq_type |= readl_relaxed(base + AON_GPIO_IS_REG) & ~mask;
1448         writel_relaxed(irq_type, base + AON_GPIO_IS_REG);
1449         edge_both |= readl_relaxed(base + AON_GPIO_IBE_REG) & ~mask;
1450         writel_relaxed(edge_both, base + AON_GPIO_IBE_REG);
1451         polarity |= readl_relaxed(base + AON_GPIO_IEV_REG) & ~mask;
1452         writel_relaxed(polarity, base + AON_GPIO_IEV_REG);
1453         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1454
1455         sfp->trigger[gpio] = trigger;
1456         return 0;
1457 }
1458
1459 static void starfive_jh7110_aon_irq_mask(struct irq_data *d)
1460 {
1461         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1462         irq_hw_number_t gpio = irqd_to_hwirq(d);
1463         void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
1464         u32 mask = BIT(gpio);
1465         unsigned long flags;
1466         u32 value;
1467
1468         if (gpio < 0 || gpio >= sfp->gc.ngpio)
1469                 return;
1470
1471         raw_spin_lock_irqsave(&sfp->lock, flags);
1472         value = readl_relaxed(ie) & ~mask;
1473         writel_relaxed(value, ie);
1474         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1475 }
1476
1477 static void starfive_jh7110_aon_irq_unmask(struct irq_data *d)
1478 {
1479         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1480         irq_hw_number_t gpio = irqd_to_hwirq(d);
1481         void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
1482         u32 mask = BIT(gpio);
1483         unsigned long flags;
1484         u32 value;
1485
1486         if (gpio < 0 || gpio >= sfp->gc.ngpio)
1487                 return;
1488
1489         raw_spin_lock_irqsave(&sfp->lock, flags);
1490         value = readl_relaxed(ie) | mask;
1491         writel_relaxed(value, ie);
1492         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1493 }
1494
1495 static void starfive_jh7110_aon_irq_ack(struct irq_data *d)
1496 {
1497         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1498         irq_hw_number_t gpio = irqd_to_hwirq(d);
1499         void __iomem *ic = sfp->padctl_base + AON_GPIO_IC_REG;
1500         u32 mask = BIT(gpio);
1501         unsigned long flags;
1502         u32 value;
1503
1504         if (gpio < 0 || gpio >= sfp->gc.ngpio)
1505                 return;
1506
1507         raw_spin_lock_irqsave(&sfp->lock, flags);
1508         value = readl_relaxed(ic) & ~mask;
1509         writel_relaxed(value, ic);
1510         writel_relaxed(value | mask, ic);
1511         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1512 }
1513
1514 static void starfive_jh7110_aon_irq_mask_ack(struct irq_data *d)
1515 {
1516         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1517         irq_hw_number_t gpio = irqd_to_hwirq(d);
1518         void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
1519         void __iomem *ic = sfp->padctl_base + AON_GPIO_IC_REG;
1520         u32 mask = BIT(gpio);
1521         unsigned long flags;
1522         u32 value;
1523
1524         if (gpio < 0 || gpio >= sfp->gc.ngpio)
1525                 return;
1526
1527         raw_spin_lock_irqsave(&sfp->lock, flags);
1528         value = readl_relaxed(ie) & ~mask;
1529         writel_relaxed(value, ie);
1530
1531         value = readl_relaxed(ic) & ~mask;
1532         writel_relaxed(value, ic);
1533         writel_relaxed(value | mask, ic);
1534         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1535 }
1536
1537 static struct irq_chip starfive_jh7110_aon_irqchip = {
1538         .name           = "starfive_jh7110_aon-gpio",
1539         .irq_ack        = starfive_jh7110_aon_irq_ack,
1540         .irq_mask_ack   = starfive_jh7110_aon_irq_mask_ack,
1541         .irq_set_type   = starfive_jh7110_aon_irq_set_type,
1542         .irq_mask       = starfive_jh7110_aon_irq_mask,
1543         .irq_unmask     = starfive_jh7110_aon_irq_unmask,
1544 };
1545
1546 static int starfive_aon_add_pin_ranges(struct gpio_chip *gc)
1547 {
1548         struct starfive_pinctrl *sfp = container_of(gc,
1549                         struct starfive_pinctrl, gc);
1550
1551         sfp->gpios.name = sfp->gc.label;
1552         sfp->gpios.base = sfp->gc.base;
1553         /*
1554          * sfp->gpios.pin_base depends on the chosen signal group
1555          * and is set in starfive_probe()
1556          */
1557         sfp->gpios.npins = AON_GPIO_NUM;
1558         sfp->gpios.gc = &sfp->gc;
1559         pinctrl_add_gpio_range(sfp->pctl_dev, &sfp->gpios);
1560         return 0;
1561 }
1562
1563 static int starfive_jh7110_aon_gpio_register(struct platform_device *pdev,
1564                 struct starfive_pinctrl *pctl)
1565 {
1566         struct device *dev = &pdev->dev;
1567         int ret, ngpio;
1568         int loop;
1569
1570         ngpio = AON_GPIO_NUM;
1571
1572         pctl->gc.direction_input = starfive_jh7110_aon_direction_input;
1573         pctl->gc.direction_output = starfive_jh7110_aon_direction_output;
1574         pctl->gc.get_direction = starfive_jh7110_aon_get_direction;
1575         pctl->gc.get = starfive_jh7110_aon_get_value;
1576         pctl->gc.set = starfive_jh7110_aon_set_value;
1577         pctl->gc.add_pin_ranges = starfive_aon_add_pin_ranges;
1578         pctl->gc.base = 64;
1579         pctl->gc.ngpio = ngpio;
1580         pctl->gc.label = dev_name(dev);
1581         pctl->gc.parent = dev;
1582         pctl->gc.owner = THIS_MODULE;
1583
1584         pctl->enabled = 0;
1585
1586         platform_set_drvdata(pdev, pctl);
1587
1588         starfive_jh7110_aon_irqchip.parent_device = dev;
1589         starfive_jh7110_aon_irqchip.name = pctl->gc.label;
1590
1591         pctl->gc.irq.chip = &starfive_jh7110_aon_irqchip;
1592         pctl->gc.irq.parent_handler = starfive_jh7110_aon_irq_handler;
1593         pctl->gc.irq.num_parents = 1;
1594         pctl->gc.irq.parents = devm_kcalloc(dev, pctl->gc.irq.num_parents,
1595                         sizeof(*pctl->gc.irq.parents), GFP_KERNEL);
1596         if (!pctl->gc.irq.parents)
1597                 return -ENOMEM;
1598         pctl->gc.irq.default_type = IRQ_TYPE_NONE;
1599         pctl->gc.irq.handler = handle_bad_irq;
1600         pctl->gc.irq.init_hw = starfive_jh7110_aon_init_hw;
1601
1602         if (IS_ENABLED(CONFIG_PM))
1603                 pm_runtime_enable(dev);
1604
1605         ret = platform_get_irq(pdev, 0);
1606         if (ret < 0)
1607                 return ret;
1608         pctl->gc.irq.parents[0] = ret;
1609
1610         ret = devm_gpiochip_add_data(dev, &pctl->gc, pctl);
1611         if (ret)
1612                 return dev_err_probe(dev, ret, "could not register gpiochip\n");
1613
1614         for (loop = 0; loop < ngpio; loop++) {
1615                 unsigned int v;
1616
1617                 v = readl_relaxed(pctl->padctl_base +
1618                                 AON_GPIO_INPUT_ENABLE_REG + (loop << 2));
1619                 v |= 0x1;
1620                 writel_relaxed(v, pctl->padctl_base +
1621                                 AON_GPIO_INPUT_ENABLE_REG + (loop << 2));
1622         }
1623
1624         dev_info(dev, "SiFive GPIO chip registered %d GPIOs\n", ngpio);
1625
1626         return 0;
1627 }
1628
1629 static const struct starfive_pinctrl_soc_info starfive_jh7110_aon_pinctrl_info = {
1630         .pins = starfive_jh7110_aon_pinctrl_pads,
1631         .npins = ARRAY_SIZE(starfive_jh7110_aon_pinctrl_pads),
1632         .flags = 1,
1633         .dout_reg_base = AON_GPO_DOUT_CFG_BASE_REG,
1634         .doen_reg_base = AON_GPO_DOEN_CFG_BASE_REG,
1635         .din_reg_base = AON_GPI_DIN_CFG_BASE_REG,
1636         .starfive_pinconf_get = starfive_jh7110_pinconf_get,
1637         .starfive_pinconf_set = starfive_jh7110_pinconf_set,
1638         .starfive_pmx_set_one_pin_mux = starfive_jh7110_aon_pmx_set_one_pin_mux,
1639         .starfive_gpio_register = starfive_jh7110_aon_gpio_register,
1640         .starfive_pinctrl_parse_pin = starfive_jh7110_aon_parse_pin_config,
1641 };
1642
1643 static const struct of_device_id starfive_jh7110_pinctrl_of_match[] = {
1644         {
1645                 .compatible = "starfive,jh7110-sys-pinctrl",
1646                 .data = &starfive_jh7110_sys_pinctrl_info,
1647         },
1648         {
1649                 .compatible = "starfive,jh7110-aon-pinctrl",
1650                 .data = &starfive_jh7110_aon_pinctrl_info,
1651         },
1652         { /* sentinel */ }
1653 };
1654
1655 static int starfive_jh7110_pinctrl_probe(struct platform_device *pdev)
1656 {
1657         const struct starfive_pinctrl_soc_info *pinctrl_info;
1658
1659         pinctrl_info = of_device_get_match_data(&pdev->dev);
1660         if (!pinctrl_info)
1661                 return -ENODEV;
1662
1663         return starfive_pinctrl_probe(pdev, pinctrl_info);
1664 }
1665
1666 static int __maybe_unused starfive_pinctrl_suspend(struct device *dev)
1667 {
1668         struct starfive_pinctrl *pctl = dev_get_drvdata(dev);
1669
1670         return pinctrl_force_sleep(pctl->pctl_dev);
1671 }
1672
1673 static int __maybe_unused starfive_pinctrl_resume(struct device *dev)
1674 {
1675         struct starfive_pinctrl *pctl = dev_get_drvdata(dev);
1676
1677         return pinctrl_force_default(pctl->pctl_dev);
1678 }
1679
1680 const struct dev_pm_ops starfive_pinctrl_pm_ops = {
1681         SET_LATE_SYSTEM_SLEEP_PM_OPS(starfive_pinctrl_suspend,
1682                                      starfive_pinctrl_resume)
1683 };
1684
1685 static struct platform_driver starfive_jh7110_pinctrl_driver = {
1686         .driver = {
1687                 .name = "starfive_jh7110-pinctrl",
1688                 .pm = &starfive_pinctrl_pm_ops,
1689                 .of_match_table = of_match_ptr(starfive_jh7110_pinctrl_of_match),
1690         },
1691         .probe = starfive_jh7110_pinctrl_probe,
1692 };
1693
1694 static int __init starfive_jh7110_pinctrl_init(void)
1695 {
1696         return platform_driver_register(&starfive_jh7110_pinctrl_driver);
1697 }
1698 arch_initcall(starfive_jh7110_pinctrl_init);
1699
1700 MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC");
1701 MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
1702 MODULE_LICENSE("GPL v2");