4230633dce2631c798c69e16a787af2c5d5730b9
[platform/kernel/linux-starfive.git] / drivers / pinctrl / starfive / pinctrl-starfive-jh7100.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Pinctrl / GPIO driver for StarFive JH7100 SoC
4  *
5  * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
6  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
7  */
8
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/io.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/spinlock.h>
19
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22
23 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
24
25 #include "../core.h"
26 #include "../pinctrl-utils.h"
27 #include "../pinmux.h"
28 #include "../pinconf.h"
29
30 #define DRIVER_NAME "pinctrl-starfive"
31
32 /*
33  * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
34  * https://github.com/starfive-tech/JH7100_Docs
35  */
36 #define NR_GPIOS        64
37
38 /*
39  * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
40  * are enabled. If set to 0 the GPIO interrupts are disabled.
41  */
42 #define GPIOEN          0x000
43
44 /*
45  * The following 32-bit registers come in pairs, but only the offset of the
46  * first register is defined. The first controls (interrupts for) GPIO 0-31 and
47  * the second GPIO 32-63.
48  */
49
50 /*
51  * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
52  * interrupt is level-triggered.
53  */
54 #define GPIOIS          0x010
55
56 /*
57  * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
58  * both positive and negative edges. If set to 0 the interrupt is triggered by a
59  * single edge.
60  */
61 #define GPIOIBE         0x018
62
63 /*
64  * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
65  * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
66  * interrupt is triggered on a falling edge (edge-triggered) or low level
67  * (level-triggered).
68  */
69 #define GPIOIEV         0x020
70
71 /*
72  * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
73  * the interrupt is disabled (masked). Note that the current documentation is
74  * wrong and says the exct opposite of this.
75  */
76 #define GPIOIE          0x028
77
78 /*
79  * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
80  * interrupt.
81  */
82 #define GPIOIC          0x030
83
84 /*
85  * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
86  */
87 #define GPIORIS         0x038
88
89 /*
90  * Interrupt Status after Masking. A 1 means the configured edge or level was
91  * detected and not masked.
92  */
93 #define GPIOMIS         0x040
94
95 /*
96  * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
97  * a digital 1 and if 0 the pin is a digital 0.
98  */
99 #define GPIODIN         0x048
100
101 /*
102  * From the data sheet section 12.2, there are 64 32-bit output data registers
103  * and 64 output enable registers. Output data and output enable registers for
104  * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
105  * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c.  The stride
106  * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
107  * and GPOn_DOEN_CFG is 0x54 + 8n.
108  */
109 #define GPON_DOUT_CFG   0x050
110 #define GPON_DOEN_CFG   0x054
111
112 /*
113  * From Section 12.3, there are 75 input signal configuration registers which
114  * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
115  * GPI_USB_OVER_CURRENT_CFG 0x378
116  */
117 #define GPI_CFG_OFFSET  0x250
118
119 /*
120  * Pad Control Bits. There are 16 pad control bits for each pin located in 103
121  * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
122  * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
123  * bit of each register.
124  */
125 #define PAD_SLEW_RATE_MASK              GENMASK(11, 9)
126 #define PAD_SLEW_RATE_POS               9
127 #define PAD_BIAS_STRONG_PULL_UP         BIT(8)
128 #define PAD_INPUT_ENABLE                BIT(7)
129 #define PAD_INPUT_SCHMITT_ENABLE        BIT(6)
130 #define PAD_BIAS_DISABLE                BIT(5)
131 #define PAD_BIAS_PULL_DOWN              BIT(4)
132 #define PAD_BIAS_MASK \
133         (PAD_BIAS_STRONG_PULL_UP | \
134          PAD_BIAS_DISABLE | \
135          PAD_BIAS_PULL_DOWN)
136 #define PAD_DRIVE_STRENGTH_MASK         GENMASK(3, 0)
137 #define PAD_DRIVE_STRENGTH_POS          0
138
139 /*
140  * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
141  * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
142  * PAD_GPIO pads. This is a global setting.
143  */
144 #define IO_PADSHARE_SEL                 0x1a0
145
146 /*
147  * This just needs to be some number such that when
148  * sfp->gpio.pin_base = PAD_INVALID_GPIO then
149  * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
150  * That is it should underflow and return something >= NR_GPIOS.
151  */
152 #define PAD_INVALID_GPIO                0x10000
153
154 /*
155  * The packed pinmux values from the device tree look like this:
156  *
157  *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
158  *  |  dout   |  doen   |  din   | dout rev | doen rev | gpio nr |
159  *
160  * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:
161  *
162  *  |      31       | 30 - 8 |   7 - 0   |
163  *  | dout/doen rev | unused | dout/doen |
164  */
165 static unsigned int starfive_pinmux_to_gpio(u32 v)
166 {
167         return v & (NR_GPIOS - 1);
168 }
169
170 static u32 starfive_pinmux_to_dout(u32 v)
171 {
172         return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
173 }
174
175 static u32 starfive_pinmux_to_doen(u32 v)
176 {
177         return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
178 }
179
180 static u32 starfive_pinmux_to_din(u32 v)
181 {
182         return (v >> 8) & GENMASK(7, 0);
183 }
184
185 /*
186  * The maximum GPIO output current depends on the chosen drive strength:
187  *
188  *  DS:   0     1     2     3     4     5     6     7
189  *  mA:  14.2  21.2  28.2  35.2  42.2  49.1  56.0  62.8
190  *
191  * After rounding that is 7*DS + 14 mA
192  */
193 static u32 starfive_drive_strength_to_max_mA(u16 ds)
194 {
195         return 7 * ds + 14;
196 }
197
198 static u16 starfive_drive_strength_from_max_mA(u32 i)
199 {
200         return (clamp(i, 14U, 63U) - 14) / 7;
201 }
202
203 static bool keepmux;
204 module_param(keepmux, bool, 0644);
205 MODULE_PARM_DESC(keepmux, "Keep pinmux settings from previous boot stage");
206
207 struct starfive_pinctrl {
208         struct gpio_chip gc;
209         struct pinctrl_gpio_range gpios;
210         raw_spinlock_t lock;
211         void __iomem *base;
212         void __iomem *padctl;
213         struct pinctrl_dev *pctl;
214         struct mutex mutex; /* serialize adding groups and functions */
215 };
216
217 static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
218                                                 unsigned int pin)
219 {
220         return pin - sfp->gpios.pin_base;
221 }
222
223 static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
224                                                 unsigned int gpio)
225 {
226         return sfp->gpios.pin_base + gpio;
227 }
228
229 static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
230 {
231         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
232
233         return container_of(gc, struct starfive_pinctrl, gc);
234 }
235
236 static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
237 {
238         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
239
240         return container_of(gc, struct starfive_pinctrl, gc);
241 }
242
243 static const struct pinctrl_pin_desc starfive_pins[] = {
244         PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
245         PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
246         PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
247         PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
248         PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
249         PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
250         PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
251         PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
252         PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
253         PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
254         PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
255         PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
256         PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
257         PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
258         PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
259         PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
260         PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
261         PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
262         PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
263         PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
264         PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
265         PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
266         PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
267         PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
268         PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
269         PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
270         PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
271         PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
272         PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
273         PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
274         PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
275         PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
276         PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
277         PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
278         PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
279         PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
280         PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
281         PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
282         PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
283         PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
284         PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
285         PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
286         PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
287         PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
288         PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
289         PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
290         PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
291         PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
292         PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
293         PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
294         PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
295         PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
296         PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
297         PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
298         PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
299         PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
300         PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
301         PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
302         PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
303         PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
304         PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
305         PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
306         PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
307         PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
308         PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),
309         PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),
310         PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),
311         PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),
312         PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),
313         PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),
314         PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),
315         PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),
316         PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),
317         PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),
318         PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),
319         PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),
320         PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),
321         PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),
322         PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),
323         PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),
324         PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),
325         PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),
326         PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),
327         PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),
328         PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),
329         PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),
330         PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),
331         PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),
332         PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),
333         PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),
334         PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),
335         PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),
336         PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),
337         PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),
338         PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),
339         PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),
340         PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),
341         PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),
342         PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),
343         PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),
344         PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),
345         PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),
346         PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),
347         PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),
348         PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),
349         PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),
350         PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),
351         PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),
352         PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),
353         PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),
354         PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),
355         PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),
356         PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),
357         PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),
358         PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),
359         PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),
360         PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),
361         PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),
362         PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),
363         PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),
364         PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),
365         PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),
366         PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),
367         PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),
368         PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),
369         PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),
370         PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),
371         PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),
372         PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),
373         PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),
374         PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),
375         PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),
376         PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),
377         PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),
378         PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),
379         PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),
380         PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),
381         PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),
382         PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),
383         PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),
384         PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),
385         PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),
386         PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),
387         PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),
388         PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),
389         PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),
390         PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),
391         PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),
392         PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),
393         PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),
394         PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),
395         PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),
396         PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),
397         PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),
398         PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),
399         PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),
400         PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),
401         PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),
402         PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),
403         PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),
404         PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),
405         PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),
406         PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),
407         PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),
408         PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),
409         PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),
410         PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),
411         PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),
412         PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),
413         PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),
414         PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),
415         PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),
416         PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),
417         PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),
418         PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),
419         PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),
420         PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),
421         PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),
422         PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),
423         PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),
424         PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),
425         PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),
426         PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),
427         PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),
428         PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),
429         PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),
430         PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),
431         PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),
432         PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),
433         PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),
434         PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),
435         PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),
436         PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),
437         PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),
438         PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),
439         PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),
440         PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),
441         PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),
442         PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),
443         PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),
444         PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),
445         PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),
446         PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),
447         PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),
448         PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),
449         PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),
450 };
451
452 #ifdef CONFIG_DEBUG_FS
453 static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
454                                   struct seq_file *s,
455                                   unsigned int pin)
456 {
457         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
458         unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
459         void __iomem *reg;
460         u32 dout, doen;
461
462         if (gpio >= NR_GPIOS)
463                 return;
464
465         reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
466         dout = readl_relaxed(reg + 0x000);
467         doen = readl_relaxed(reg + 0x004);
468
469         seq_printf(s, "dout=%lu%s doen=%lu%s",
470                    dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",
471                    doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");
472 }
473 #else
474 #define starfive_pin_dbg_show NULL
475 #endif
476
477 static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
478                                    struct device_node *np,
479                                    struct pinctrl_map **maps,
480                                    unsigned int *num_maps)
481 {
482         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
483         struct device *dev = sfp->gc.parent;
484         struct device_node *child;
485         struct pinctrl_map *map;
486         const char **pgnames;
487         const char *grpname;
488         u32 *pinmux;
489         int ngroups;
490         int *pins;
491         int nmaps;
492         int ret;
493
494         nmaps = 0;
495         ngroups = 0;
496         for_each_child_of_node(np, child) {
497                 int npinmux = of_property_count_u32_elems(child, "pinmux");
498                 int npins   = of_property_count_u32_elems(child, "pins");
499
500                 if (npinmux > 0 && npins > 0) {
501                         dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
502                                 np, child);
503                         of_node_put(child);
504                         return -EINVAL;
505                 }
506                 if (npinmux == 0 && npins == 0) {
507                         dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
508                                 np, child);
509                         of_node_put(child);
510                         return -EINVAL;
511                 }
512
513                 if (npinmux > 0)
514                         nmaps += 2;
515                 else
516                         nmaps += 1;
517                 ngroups += 1;
518         }
519
520         pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
521         if (!pgnames)
522                 return -ENOMEM;
523
524         map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
525         if (!map)
526                 return -ENOMEM;
527
528         nmaps = 0;
529         ngroups = 0;
530         mutex_lock(&sfp->mutex);
531         for_each_child_of_node(np, child) {
532                 int npins;
533                 int i;
534
535                 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
536                 if (!grpname) {
537                         ret = -ENOMEM;
538                         goto put_child;
539                 }
540
541                 pgnames[ngroups++] = grpname;
542
543                 if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {
544                         pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
545                         if (!pins) {
546                                 ret = -ENOMEM;
547                                 goto put_child;
548                         }
549
550                         pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
551                         if (!pinmux) {
552                                 ret = -ENOMEM;
553                                 goto put_child;
554                         }
555
556                         ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
557                         if (ret)
558                                 goto put_child;
559
560                         for (i = 0; i < npins; i++) {
561                                 unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
562
563                                 pins[i] = starfive_gpio_to_pin(sfp, gpio);
564                         }
565
566                         map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
567                         map[nmaps].data.mux.function = np->name;
568                         map[nmaps].data.mux.group = grpname;
569                         nmaps += 1;
570                 } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {
571                         pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
572                         if (!pins) {
573                                 ret = -ENOMEM;
574                                 goto put_child;
575                         }
576
577                         pinmux = NULL;
578
579                         for (i = 0; i < npins; i++) {
580                                 u32 v;
581
582                                 ret = of_property_read_u32_index(child, "pins", i, &v);
583                                 if (ret)
584                                         goto put_child;
585                                 pins[i] = v;
586                         }
587                 } else {
588                         ret = -EINVAL;
589                         goto put_child;
590                 }
591
592                 ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
593                 if (ret < 0) {
594                         dev_err(dev, "error adding group %s: %d\n", grpname, ret);
595                         goto put_child;
596                 }
597
598                 ret = pinconf_generic_parse_dt_config(child, pctldev,
599                                                       &map[nmaps].data.configs.configs,
600                                                       &map[nmaps].data.configs.num_configs);
601                 if (ret) {
602                         dev_err(dev, "error parsing pin config of group %s: %d\n",
603                                 grpname, ret);
604                         goto put_child;
605                 }
606
607                 /* don't create a map if there are no pinconf settings */
608                 if (map[nmaps].data.configs.num_configs == 0)
609                         continue;
610
611                 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
612                 map[nmaps].data.configs.group_or_pin = grpname;
613                 nmaps += 1;
614         }
615
616         ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
617         if (ret < 0) {
618                 dev_err(dev, "error adding function %s: %d\n", np->name, ret);
619                 goto free_map;
620         }
621
622         *maps = map;
623         *num_maps = nmaps;
624         mutex_unlock(&sfp->mutex);
625         return 0;
626
627 put_child:
628         of_node_put(child);
629 free_map:
630         pinctrl_utils_free_map(pctldev, map, nmaps);
631         mutex_unlock(&sfp->mutex);
632         return ret;
633 }
634
635 static const struct pinctrl_ops starfive_pinctrl_ops = {
636         .get_groups_count = pinctrl_generic_get_group_count,
637         .get_group_name = pinctrl_generic_get_group_name,
638         .get_group_pins = pinctrl_generic_get_group_pins,
639         .pin_dbg_show = starfive_pin_dbg_show,
640         .dt_node_to_map = starfive_dt_node_to_map,
641         .dt_free_map = pinctrl_utils_free_map,
642 };
643
644 static int starfive_set_mux(struct pinctrl_dev *pctldev,
645                             unsigned int fsel, unsigned int gsel)
646 {
647         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
648         struct device *dev = sfp->gc.parent;
649         const struct group_desc *group;
650         const u32 *pinmux;
651         unsigned int i;
652
653         group = pinctrl_generic_get_group(pctldev, gsel);
654         if (!group)
655                 return -EINVAL;
656
657         pinmux = group->data;
658         for (i = 0; i < group->num_pins; i++) {
659                 u32 v = pinmux[i];
660                 unsigned int gpio = starfive_pinmux_to_gpio(v);
661                 u32 dout = starfive_pinmux_to_dout(v);
662                 u32 doen = starfive_pinmux_to_doen(v);
663                 u32 din = starfive_pinmux_to_din(v);
664                 void __iomem *reg_dout;
665                 void __iomem *reg_doen;
666                 void __iomem *reg_din;
667                 unsigned long flags;
668
669                 dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",
670                         gpio, dout, doen, din);
671
672                 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
673                 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
674                 if (din != GPI_NONE)
675                         reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
676                 else
677                         reg_din = NULL;
678
679                 raw_spin_lock_irqsave(&sfp->lock, flags);
680                 writel_relaxed(dout, reg_dout);
681                 writel_relaxed(doen, reg_doen);
682                 if (reg_din)
683                         writel_relaxed(gpio + 2, reg_din);
684                 raw_spin_unlock_irqrestore(&sfp->lock, flags);
685         }
686
687         return 0;
688 }
689
690 static const struct pinmux_ops starfive_pinmux_ops = {
691         .get_functions_count = pinmux_generic_get_function_count,
692         .get_function_name = pinmux_generic_get_function_name,
693         .get_function_groups = pinmux_generic_get_function_groups,
694         .set_mux = starfive_set_mux,
695         .strict = true,
696 };
697
698 static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
699                                unsigned int pin)
700 {
701         void __iomem *reg = sfp->padctl + 4 * (pin / 2);
702         int shift = 16 * (pin % 2);
703
704         return readl_relaxed(reg) >> shift;
705 }
706
707 static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
708                                 unsigned int pin,
709                                 u16 _mask, u16 _value)
710 {
711         void __iomem *reg = sfp->padctl + 4 * (pin / 2);
712         int shift = 16 * (pin % 2);
713         u32 mask = (u32)_mask << shift;
714         u32 value = (u32)_value << shift;
715         unsigned long flags;
716
717         dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
718
719         raw_spin_lock_irqsave(&sfp->lock, flags);
720         value |= readl_relaxed(reg) & ~mask;
721         writel_relaxed(value, reg);
722         raw_spin_unlock_irqrestore(&sfp->lock, flags);
723 }
724
725 #define PIN_CONFIG_STARFIVE_STRONG_PULL_UP      (PIN_CONFIG_END + 1)
726
727 static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {
728         { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
729 };
730
731 #ifdef CONFIG_DEBUG_FS
732 static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {
733         PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
734 };
735
736 static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==
737               ARRAY_SIZE(starfive_pinconf_custom_params));
738 #else
739 #define starfive_pinconf_custom_conf_items NULL
740 #endif
741
742 static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
743                                 unsigned int pin, unsigned long *config)
744 {
745         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
746         int param = pinconf_to_config_param(*config);
747         u16 value = starfive_padctl_get(sfp, pin);
748         bool enabled;
749         u32 arg;
750
751         switch (param) {
752         case PIN_CONFIG_BIAS_DISABLE:
753                 enabled = value & PAD_BIAS_DISABLE;
754                 arg = 0;
755                 break;
756         case PIN_CONFIG_BIAS_PULL_DOWN:
757                 enabled = value & PAD_BIAS_PULL_DOWN;
758                 arg = 1;
759                 break;
760         case PIN_CONFIG_BIAS_PULL_UP:
761                 enabled = !(value & PAD_BIAS_MASK);
762                 arg = 1;
763                 break;
764         case PIN_CONFIG_DRIVE_STRENGTH:
765                 enabled = value & PAD_DRIVE_STRENGTH_MASK;
766                 arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);
767                 break;
768         case PIN_CONFIG_INPUT_ENABLE:
769                 enabled = value & PAD_INPUT_ENABLE;
770                 arg = enabled;
771                 break;
772         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
773                 enabled = value & PAD_INPUT_SCHMITT_ENABLE;
774                 arg = enabled;
775                 break;
776         case PIN_CONFIG_SLEW_RATE:
777                 enabled = value & PAD_SLEW_RATE_MASK;
778                 arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;
779                 break;
780         case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
781                 enabled = value & PAD_BIAS_STRONG_PULL_UP;
782                 arg = enabled;
783                 break;
784         default:
785                 return -ENOTSUPP;
786         }
787
788         *config = pinconf_to_config_packed(param, arg);
789         return enabled ? 0 : -EINVAL;
790 }
791
792 static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
793                                       unsigned int gsel, unsigned long *config)
794 {
795         const struct group_desc *group;
796
797         group = pinctrl_generic_get_group(pctldev, gsel);
798         if (!group)
799                 return -EINVAL;
800
801         return starfive_pinconf_get(pctldev, group->pins[0], config);
802 }
803
804 static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
805                                       unsigned int gsel,
806                                       unsigned long *configs,
807                                       unsigned int num_configs)
808 {
809         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
810         const struct group_desc *group;
811         u16 mask, value;
812         int i;
813
814         group = pinctrl_generic_get_group(pctldev, gsel);
815         if (!group)
816                 return -EINVAL;
817
818         mask = 0;
819         value = 0;
820         for (i = 0; i < num_configs; i++) {
821                 int param = pinconf_to_config_param(configs[i]);
822                 u32 arg = pinconf_to_config_argument(configs[i]);
823
824                 switch (param) {
825                 case PIN_CONFIG_BIAS_DISABLE:
826                         mask |= PAD_BIAS_MASK;
827                         value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;
828                         break;
829                 case PIN_CONFIG_BIAS_PULL_DOWN:
830                         if (arg == 0)
831                                 return -ENOTSUPP;
832                         mask |= PAD_BIAS_MASK;
833                         value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;
834                         break;
835                 case PIN_CONFIG_BIAS_PULL_UP:
836                         if (arg == 0)
837                                 return -ENOTSUPP;
838                         mask |= PAD_BIAS_MASK;
839                         value = value & ~PAD_BIAS_MASK;
840                         break;
841                 case PIN_CONFIG_DRIVE_STRENGTH:
842                         mask |= PAD_DRIVE_STRENGTH_MASK;
843                         value = (value & ~PAD_DRIVE_STRENGTH_MASK) |
844                                 starfive_drive_strength_from_max_mA(arg);
845                         break;
846                 case PIN_CONFIG_INPUT_ENABLE:
847                         mask |= PAD_INPUT_ENABLE;
848                         if (arg)
849                                 value |= PAD_INPUT_ENABLE;
850                         else
851                                 value &= ~PAD_INPUT_ENABLE;
852                         break;
853                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
854                         mask |= PAD_INPUT_SCHMITT_ENABLE;
855                         if (arg)
856                                 value |= PAD_INPUT_SCHMITT_ENABLE;
857                         else
858                                 value &= ~PAD_INPUT_SCHMITT_ENABLE;
859                         break;
860                 case PIN_CONFIG_SLEW_RATE:
861                         mask |= PAD_SLEW_RATE_MASK;
862                         value = (value & ~PAD_SLEW_RATE_MASK) |
863                                 ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);
864                         break;
865                 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
866                         if (arg) {
867                                 mask |= PAD_BIAS_MASK;
868                                 value = (value & ~PAD_BIAS_MASK) |
869                                         PAD_BIAS_STRONG_PULL_UP;
870                         } else {
871                                 mask |= PAD_BIAS_STRONG_PULL_UP;
872                                 value = value & ~PAD_BIAS_STRONG_PULL_UP;
873                         }
874                         break;
875                 default:
876                         return -ENOTSUPP;
877                 }
878         }
879
880         for (i = 0; i < group->num_pins; i++)
881                 starfive_padctl_rmw(sfp, group->pins[i], mask, value);
882
883         return 0;
884 }
885
886 #ifdef CONFIG_DEBUG_FS
887 static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
888                                       struct seq_file *s, unsigned int pin)
889 {
890         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
891         u16 value = starfive_padctl_get(sfp, pin);
892
893         seq_printf(s, " (0x%03x)", value);
894 }
895 #else
896 #define starfive_pinconf_dbg_show NULL
897 #endif
898
899 static const struct pinconf_ops starfive_pinconf_ops = {
900         .pin_config_get = starfive_pinconf_get,
901         .pin_config_group_get = starfive_pinconf_group_get,
902         .pin_config_group_set = starfive_pinconf_group_set,
903         .pin_config_dbg_show = starfive_pinconf_dbg_show,
904         .is_generic = true,
905 };
906
907 static struct pinctrl_desc starfive_desc = {
908         .name = DRIVER_NAME,
909         .pins = starfive_pins,
910         .npins = ARRAY_SIZE(starfive_pins),
911         .pctlops = &starfive_pinctrl_ops,
912         .pmxops = &starfive_pinmux_ops,
913         .confops = &starfive_pinconf_ops,
914         .owner = THIS_MODULE,
915         .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),
916         .custom_params = starfive_pinconf_custom_params,
917         .custom_conf_items = starfive_pinconf_custom_conf_items,
918 };
919
920 static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio)
921 {
922         return pinctrl_gpio_request(gc->base + gpio);
923 }
924
925 static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio)
926 {
927         pinctrl_gpio_free(gc->base + gpio);
928 }
929
930 static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
931 {
932         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
933         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
934
935         if (readl_relaxed(doen) == GPO_ENABLE)
936                 return GPIO_LINE_DIRECTION_OUT;
937
938         return GPIO_LINE_DIRECTION_IN;
939 }
940
941 static int starfive_gpio_direction_input(struct gpio_chip *gc,
942                                          unsigned int gpio)
943 {
944         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
945         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
946         unsigned long flags;
947
948         /* enable input and schmitt trigger */
949         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
950                             PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
951                             PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);
952
953         raw_spin_lock_irqsave(&sfp->lock, flags);
954         writel_relaxed(GPO_DISABLE, doen);
955         raw_spin_unlock_irqrestore(&sfp->lock, flags);
956         return 0;
957 }
958
959 static int starfive_gpio_direction_output(struct gpio_chip *gc,
960                                           unsigned int gpio, int value)
961 {
962         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
963         void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
964         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
965         unsigned long flags;
966
967         raw_spin_lock_irqsave(&sfp->lock, flags);
968         writel_relaxed(value, dout);
969         writel_relaxed(GPO_ENABLE, doen);
970         raw_spin_unlock_irqrestore(&sfp->lock, flags);
971
972         /* disable input, schmitt trigger and bias */
973         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
974                             PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
975                             PAD_BIAS_DISABLE);
976
977         return 0;
978 }
979
980 static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
981 {
982         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
983         void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
984
985         return !!(readl_relaxed(din) & BIT(gpio % 32));
986 }
987
988 static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
989                               int value)
990 {
991         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
992         void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
993         unsigned long flags;
994
995         raw_spin_lock_irqsave(&sfp->lock, flags);
996         writel_relaxed(value, dout);
997         raw_spin_unlock_irqrestore(&sfp->lock, flags);
998 }
999
1000 static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
1001                                     unsigned long config)
1002 {
1003         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1004         u32 arg = pinconf_to_config_argument(config);
1005         u16 value;
1006         u16 mask;
1007
1008         switch (pinconf_to_config_param(config)) {
1009         case PIN_CONFIG_BIAS_DISABLE:
1010                 mask  = PAD_BIAS_MASK;
1011                 value = PAD_BIAS_DISABLE;
1012                 break;
1013         case PIN_CONFIG_BIAS_PULL_DOWN:
1014                 if (arg == 0)
1015                         return -ENOTSUPP;
1016                 mask  = PAD_BIAS_MASK;
1017                 value = PAD_BIAS_PULL_DOWN;
1018                 break;
1019         case PIN_CONFIG_BIAS_PULL_UP:
1020                 if (arg == 0)
1021                         return -ENOTSUPP;
1022                 mask  = PAD_BIAS_MASK;
1023                 value = 0;
1024                 break;
1025         case PIN_CONFIG_DRIVE_PUSH_PULL:
1026                 return 0;
1027         case PIN_CONFIG_INPUT_ENABLE:
1028                 mask  = PAD_INPUT_ENABLE;
1029                 value = arg ? PAD_INPUT_ENABLE : 0;
1030                 break;
1031         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1032                 mask  = PAD_INPUT_SCHMITT_ENABLE;
1033                 value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;
1034                 break;
1035         default:
1036                 return -ENOTSUPP;
1037         }
1038
1039         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
1040         return 0;
1041 }
1042
1043 static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
1044 {
1045         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1046
1047         sfp->gpios.name = sfp->gc.label;
1048         sfp->gpios.base = sfp->gc.base;
1049         /*
1050          * sfp->gpios.pin_base depends on the chosen signal group
1051          * and is set in starfive_probe()
1052          */
1053         sfp->gpios.npins = NR_GPIOS;
1054         sfp->gpios.gc = &sfp->gc;
1055         pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
1056         return 0;
1057 }
1058
1059 static void starfive_irq_ack(struct irq_data *d)
1060 {
1061         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1062         irq_hw_number_t gpio = irqd_to_hwirq(d);
1063         void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1064         u32 mask = BIT(gpio % 32);
1065         unsigned long flags;
1066
1067         raw_spin_lock_irqsave(&sfp->lock, flags);
1068         writel_relaxed(mask, ic);
1069         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1070 }
1071
1072 static void starfive_irq_mask(struct irq_data *d)
1073 {
1074         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1075         irq_hw_number_t gpio = irqd_to_hwirq(d);
1076         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1077         u32 mask = BIT(gpio % 32);
1078         unsigned long flags;
1079         u32 value;
1080
1081         raw_spin_lock_irqsave(&sfp->lock, flags);
1082         value = readl_relaxed(ie) & ~mask;
1083         writel_relaxed(value, ie);
1084         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1085
1086         gpiochip_disable_irq(&sfp->gc, d->hwirq);
1087 }
1088
1089 static void starfive_irq_mask_ack(struct irq_data *d)
1090 {
1091         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1092         irq_hw_number_t gpio = irqd_to_hwirq(d);
1093         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1094         void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1095         u32 mask = BIT(gpio % 32);
1096         unsigned long flags;
1097         u32 value;
1098
1099         raw_spin_lock_irqsave(&sfp->lock, flags);
1100         value = readl_relaxed(ie) & ~mask;
1101         writel_relaxed(value, ie);
1102         writel_relaxed(mask, ic);
1103         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1104 }
1105
1106 static void starfive_irq_unmask(struct irq_data *d)
1107 {
1108         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1109         irq_hw_number_t gpio = irqd_to_hwirq(d);
1110         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1111         u32 mask = BIT(gpio % 32);
1112         unsigned long flags;
1113         u32 value;
1114
1115         gpiochip_enable_irq(&sfp->gc, d->hwirq);
1116
1117         raw_spin_lock_irqsave(&sfp->lock, flags);
1118         value = readl_relaxed(ie) | mask;
1119         writel_relaxed(value, ie);
1120         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1121 }
1122
1123 static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
1124 {
1125         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1126         irq_hw_number_t gpio = irqd_to_hwirq(d);
1127         void __iomem *base = sfp->base + 4 * (gpio / 32);
1128         u32 mask = BIT(gpio % 32);
1129         u32 irq_type, edge_both, polarity;
1130         unsigned long flags;
1131
1132         switch (trigger) {
1133         case IRQ_TYPE_EDGE_RISING:
1134                 irq_type  = mask; /* 1: edge triggered */
1135                 edge_both = 0;    /* 0: single edge */
1136                 polarity  = mask; /* 1: rising edge */
1137                 break;
1138         case IRQ_TYPE_EDGE_FALLING:
1139                 irq_type  = mask; /* 1: edge triggered */
1140                 edge_both = 0;    /* 0: single edge */
1141                 polarity  = 0;    /* 0: falling edge */
1142                 break;
1143         case IRQ_TYPE_EDGE_BOTH:
1144                 irq_type  = mask; /* 1: edge triggered */
1145                 edge_both = mask; /* 1: both edges */
1146                 polarity  = 0;    /* 0: ignored */
1147                 break;
1148         case IRQ_TYPE_LEVEL_HIGH:
1149                 irq_type  = 0;    /* 0: level triggered */
1150                 edge_both = 0;    /* 0: ignored */
1151                 polarity  = mask; /* 1: high level */
1152                 break;
1153         case IRQ_TYPE_LEVEL_LOW:
1154                 irq_type  = 0;    /* 0: level triggered */
1155                 edge_both = 0;    /* 0: ignored */
1156                 polarity  = 0;    /* 0: low level */
1157                 break;
1158         default:
1159                 return -EINVAL;
1160         }
1161
1162         if (trigger & IRQ_TYPE_EDGE_BOTH)
1163                 irq_set_handler_locked(d, handle_edge_irq);
1164         else
1165                 irq_set_handler_locked(d, handle_level_irq);
1166
1167         raw_spin_lock_irqsave(&sfp->lock, flags);
1168         irq_type |= readl_relaxed(base + GPIOIS) & ~mask;
1169         writel_relaxed(irq_type, base + GPIOIS);
1170         edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;
1171         writel_relaxed(edge_both, base + GPIOIBE);
1172         polarity |= readl_relaxed(base + GPIOIEV) & ~mask;
1173         writel_relaxed(polarity, base + GPIOIEV);
1174         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1175         return 0;
1176 }
1177
1178 static const struct irq_chip starfive_irq_chip = {
1179         .name = "StarFive GPIO",
1180         .irq_ack = starfive_irq_ack,
1181         .irq_mask = starfive_irq_mask,
1182         .irq_mask_ack = starfive_irq_mask_ack,
1183         .irq_unmask = starfive_irq_unmask,
1184         .irq_set_type = starfive_irq_set_type,
1185         .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
1186         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1187 };
1188
1189 static void starfive_gpio_irq_handler(struct irq_desc *desc)
1190 {
1191         struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
1192         struct irq_chip *chip = irq_desc_get_chip(desc);
1193         unsigned long mis;
1194         unsigned int pin;
1195
1196         chained_irq_enter(chip, desc);
1197
1198         mis = readl_relaxed(sfp->base + GPIOMIS + 0);
1199         for_each_set_bit(pin, &mis, 32)
1200                 generic_handle_domain_irq(sfp->gc.irq.domain, pin);
1201
1202         mis = readl_relaxed(sfp->base + GPIOMIS + 4);
1203         for_each_set_bit(pin, &mis, 32)
1204                 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
1205
1206         chained_irq_exit(chip, desc);
1207 }
1208
1209 static int starfive_gpio_init_hw(struct gpio_chip *gc)
1210 {
1211         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1212
1213         /* mask all GPIO interrupts */
1214         writel(0, sfp->base + GPIOIE + 0);
1215         writel(0, sfp->base + GPIOIE + 4);
1216         /* clear edge interrupt flags */
1217         writel(~0U, sfp->base + GPIOIC + 0);
1218         writel(~0U, sfp->base + GPIOIC + 4);
1219         /* enable GPIO interrupts */
1220         writel(1, sfp->base + GPIOEN);
1221         return 0;
1222 }
1223
1224 static void starfive_disable_clock(void *data)
1225 {
1226         clk_disable_unprepare(data);
1227 }
1228
1229 #define GPI_END (GPI_USB_OVER_CURRENT + 1)
1230 static void starfive_pinmux_reset(struct starfive_pinctrl *sfp)
1231 {
1232         static const DECLARE_BITMAP(defaults, GPI_END) = {
1233                 BIT_MASK(GPI_I2C0_PAD_SCK_IN) |
1234                 BIT_MASK(GPI_I2C0_PAD_SDA_IN) |
1235                 BIT_MASK(GPI_I2C1_PAD_SCK_IN) |
1236                 BIT_MASK(GPI_I2C1_PAD_SDA_IN) |
1237                 BIT_MASK(GPI_I2C2_PAD_SCK_IN) |
1238                 BIT_MASK(GPI_I2C2_PAD_SDA_IN) |
1239                 BIT_MASK(GPI_I2C3_PAD_SCK_IN) |
1240                 BIT_MASK(GPI_I2C3_PAD_SDA_IN) |
1241                 BIT_MASK(GPI_SDIO0_PAD_CARD_DETECT_N) |
1242
1243                 BIT_MASK(GPI_SDIO1_PAD_CARD_DETECT_N) |
1244                 BIT_MASK(GPI_SPI0_PAD_SS_IN_N) |
1245                 BIT_MASK(GPI_SPI1_PAD_SS_IN_N) |
1246                 BIT_MASK(GPI_SPI2_PAD_SS_IN_N) |
1247                 BIT_MASK(GPI_SPI2AHB_PAD_SS_N) |
1248                 BIT_MASK(GPI_SPI3_PAD_SS_IN_N),
1249
1250                 BIT_MASK(GPI_UART0_PAD_SIN) |
1251                 BIT_MASK(GPI_UART1_PAD_SIN) |
1252                 BIT_MASK(GPI_UART2_PAD_SIN) |
1253                 BIT_MASK(GPI_UART3_PAD_SIN) |
1254                 BIT_MASK(GPI_USB_OVER_CURRENT)
1255         };
1256         DECLARE_BITMAP(keep, NR_GPIOS) = {};
1257         struct device_node *np = sfp->gc.parent->of_node;
1258         int len = of_property_count_u32_elems(np, "starfive,keep-gpiomux");
1259         int i;
1260
1261         for (i = 0; i < len; i++) {
1262                 u32 gpio;
1263
1264                 of_property_read_u32_index(np, "starfive,keep-gpiomux", i, &gpio);
1265                 if (gpio < NR_GPIOS)
1266                         set_bit(gpio, keep);
1267         }
1268
1269         for (i = 0; i < NR_GPIOS; i++) {
1270                 if (test_bit(i, keep))
1271                         continue;
1272
1273                 writel_relaxed(GPO_DISABLE, sfp->base + GPON_DOEN_CFG + 8 * i);
1274                 writel_relaxed(GPO_LOW,     sfp->base + GPON_DOUT_CFG + 8 * i);
1275         }
1276
1277         for (i = 0; i < GPI_END; i++) {
1278                 void __iomem *reg = sfp->base + GPI_CFG_OFFSET + 4 * i;
1279                 u32 din = readl_relaxed(reg);
1280
1281                 if (din >= 2 && din < (NR_GPIOS + 2) && test_bit(din - 2, keep))
1282                         continue;
1283
1284                 writel_relaxed(test_bit(i, defaults), reg);
1285         }
1286 }
1287
1288 static int starfive_probe(struct platform_device *pdev)
1289 {
1290         struct device *dev = &pdev->dev;
1291         struct starfive_pinctrl *sfp;
1292         struct reset_control *rst;
1293         struct clk *clk;
1294         u32 value;
1295         int ret;
1296
1297         sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
1298         if (!sfp)
1299                 return -ENOMEM;
1300
1301         sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
1302         if (IS_ERR(sfp->base))
1303                 return PTR_ERR(sfp->base);
1304
1305         sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
1306         if (IS_ERR(sfp->padctl))
1307                 return PTR_ERR(sfp->padctl);
1308
1309         clk = devm_clk_get(dev, NULL);
1310         if (IS_ERR(clk))
1311                 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
1312
1313         rst = devm_reset_control_get_exclusive(dev, NULL);
1314         if (IS_ERR(rst))
1315                 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
1316
1317         ret = clk_prepare_enable(clk);
1318         if (ret)
1319                 return dev_err_probe(dev, ret, "could not enable clock\n");
1320
1321         ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
1322         if (ret)
1323                 return ret;
1324
1325         /*
1326          * We don't want to assert reset and risk undoing pin muxing for the
1327          * early boot serial console, but let's make sure the reset line is
1328          * deasserted in case someone runs a really minimal bootloader.
1329          */
1330         ret = reset_control_deassert(rst);
1331         if (ret)
1332                 return dev_err_probe(dev, ret, "could not deassert reset\n");
1333
1334         platform_set_drvdata(pdev, sfp);
1335         sfp->gc.parent = dev;
1336         raw_spin_lock_init(&sfp->lock);
1337         mutex_init(&sfp->mutex);
1338
1339         ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
1340         if (ret)
1341                 return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
1342
1343         if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
1344                 if (value > 6)
1345                         return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1346                 writel(value, sfp->padctl + IO_PADSHARE_SEL);
1347         }
1348
1349         if (!keepmux)
1350                 starfive_pinmux_reset(sfp);
1351
1352         value = readl(sfp->padctl + IO_PADSHARE_SEL);
1353         switch (value) {
1354         case 0:
1355                 sfp->gpios.pin_base = PAD_INVALID_GPIO;
1356                 goto out_pinctrl_enable;
1357         case 1:
1358                 sfp->gpios.pin_base = PAD_GPIO(0);
1359                 break;
1360         case 2:
1361                 sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
1362                 break;
1363         case 3:
1364                 sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
1365                 break;
1366         case 4: case 5: case 6:
1367                 sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
1368                 break;
1369         default:
1370                 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1371         }
1372
1373         sfp->gc.label = dev_name(dev);
1374         sfp->gc.owner = THIS_MODULE;
1375         sfp->gc.request = starfive_gpio_request;
1376         sfp->gc.free = starfive_gpio_free;
1377         sfp->gc.get_direction = starfive_gpio_get_direction;
1378         sfp->gc.direction_input = starfive_gpio_direction_input;
1379         sfp->gc.direction_output = starfive_gpio_direction_output;
1380         sfp->gc.get = starfive_gpio_get;
1381         sfp->gc.set = starfive_gpio_set;
1382         sfp->gc.set_config = starfive_gpio_set_config;
1383         sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
1384         sfp->gc.base = -1;
1385         sfp->gc.ngpio = NR_GPIOS;
1386
1387         gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
1388         sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
1389         sfp->gc.irq.num_parents = 1;
1390         sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
1391                                            sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
1392         if (!sfp->gc.irq.parents)
1393                 return -ENOMEM;
1394         sfp->gc.irq.default_type = IRQ_TYPE_NONE;
1395         sfp->gc.irq.handler = handle_bad_irq;
1396         sfp->gc.irq.init_hw = starfive_gpio_init_hw;
1397
1398         ret = platform_get_irq(pdev, 0);
1399         if (ret < 0)
1400                 return ret;
1401         sfp->gc.irq.parents[0] = ret;
1402
1403         ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
1404         if (ret)
1405                 return dev_err_probe(dev, ret, "could not register gpiochip\n");
1406
1407         irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
1408
1409 out_pinctrl_enable:
1410         return pinctrl_enable(sfp->pctl);
1411 }
1412
1413 static const struct of_device_id starfive_of_match[] = {
1414         { .compatible = "starfive,jh7100-pinctrl" },
1415         { /* sentinel */ }
1416 };
1417 MODULE_DEVICE_TABLE(of, starfive_of_match);
1418
1419 static struct platform_driver starfive_pinctrl_driver = {
1420         .probe = starfive_probe,
1421         .driver = {
1422                 .name = DRIVER_NAME,
1423                 .of_match_table = starfive_of_match,
1424         },
1425 };
1426 module_platform_driver(starfive_pinctrl_driver);
1427
1428 MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");
1429 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1430 MODULE_LICENSE("GPL v2");