drivers/pinctrl/sh-pfc/pfc-r8a7791.c

   1 /*
   2  * r8a7791 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2
   8  * as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/platform_data/gpio-rcar.h>
  13
  14 #include "core.h"
  15 #include "sh_pfc.h"
  16
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_32(0, fn, sfx),                                         \
  19         PORT_GP_32(1, fn, sfx),                                         \
  20         PORT_GP_32(2, fn, sfx),                                         \
  21         PORT_GP_32(3, fn, sfx),                                         \
  22         PORT_GP_32(4, fn, sfx),                                         \
  23         PORT_GP_32(5, fn, sfx),                                         \
  24         PORT_GP_32(6, fn, sfx),                                         \
  25         PORT_GP_32(7, fn, sfx)
  26
  27 enum {
  28         PINMUX_RESERVED = 0,
  29
  30         PINMUX_DATA_BEGIN,
  31         GP_ALL(DATA),
  32         PINMUX_DATA_END,
  33
  34         PINMUX_FUNCTION_BEGIN,
  35         GP_ALL(FN),
  36
  37         /* GPSR0 */
  38         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  39         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  40         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  41         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  42         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  43         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  44
  45         /* GPSR1 */
  46         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  47         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  48         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  49         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  50         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  51         FN_IP3_21_20,
  52
  53         /* GPSR2 */
  54         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  55         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  56         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  57         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  58         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  59         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  60         FN_IP6_5_3, FN_IP6_7_6,
  61
  62         /* GPSR3 */
  63         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  64         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  65         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  66         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  67         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  68         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  69         FN_IP9_18_17,
  70
  71         /* GPSR4 */
  72         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  73         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  74         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  75         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  76         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  77         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  78         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  79         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  80
  81         /* GPSR5 */
  82         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  83         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  84         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  85         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  86         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
  87         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
  88         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
  89
  90         /* GPSR6 */
  91         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
  92         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
  93         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
  94         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
  95         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
  96         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
  97         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
  98         FN_USB1_OVC, FN_DU0_DOTCLKIN,
  99
 100         /* GPSR7 */
 101         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 102         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 103         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 104         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 105         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 106         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 107
 108         /* IPSR0 */
 109         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 110         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 111         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
 112         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 113         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 114         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 115
 116         /* IPSR1 */
 117         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
 118         FN_A9, FN_MSIOF1_SS2, FN_SDA0,
 119         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 120         FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
 121         FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
 122         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 123         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 124         FN_A15, FN_BPFCLK_C,
 125         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 126         FN_A17, FN_DACK2_B, FN_SDA0_C,
 127         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 128
 129         /* IPSR2 */
 130         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 131         FN_A20, FN_SPCLK,
 132         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 133         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 134         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 135         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 136         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 137         FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
 138         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
 139         FN_EX_CS1_N, FN_MSIOF2_SCK,
 140         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 141         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 142
 143         /* IPSR3 */
 144         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 145         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 146         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 147         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 148         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 149         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 150         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 151         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 152         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 153         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 154         FN_DACK0, FN_DRACK0, FN_REMOCON,
 155         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 156         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 157         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 158         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 159
 160         /* IPSR4 */
 161         FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
 162         FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
 163         FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 164         FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
 165         FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 166         FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
 167         FN_GLO_Q1_D, FN_HCTS1_N_E,
 168         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 169         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 170         FN_SSI_SCK4, FN_GLO_SS_D,
 171         FN_SSI_WS4, FN_GLO_RFON_D,
 172         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 173         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 174         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 175
 176         /* IPSR5 */
 177         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 178         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 179         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 180         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 181         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 182         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 183         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 184         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 185         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 186         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 187         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 188         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 189         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 190         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 191         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 192
 193         /* IPSR6 */
 194         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 195         FN_SCIF_CLK, FN_BPFCLK_E,
 196         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 197         FN_SCIFA2_RXD, FN_FMIN_E,
 198         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 199         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 200         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 201         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 202         FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 203         FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 204         FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
 205         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
 206         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 207         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 208
 209         /* IPSR7 */
 210         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 211         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 212         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 213         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 214         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 215         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 216         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 217         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 218         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 219         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 220         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 221         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 222         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 223         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 224         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 225         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 226         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 227         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 228
 229         /* IPSR8 */
 230         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 231         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 232         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 233         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 234         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 235         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 236         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 237         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 238         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 239         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 240         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 241         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 242         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 243         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 244         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 245         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 246         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 247
 248         /* IPSR9 */
 249         FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
 250         FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 251         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 252         FN_DU1_DOTCLKOUT0, FN_QCLK,
 253         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 254         FN_TX3_B, FN_SCL2_B, FN_PWM4,
 255         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 256         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 257         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 258         FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
 259         FN_DU1_DISP, FN_QPOLA,
 260         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 261         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 262         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 263         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 264         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 265         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 266         FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
 267         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 268
 269         /* IPSR10 */
 270         FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
 271         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 272         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
 273         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 274         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
 275         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 276         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 277         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 278         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 279         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 280         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 281         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 282         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 283         FN_TS_SDATA0_C, FN_ATACS11_N,
 284         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 285         FN_TS_SCK0_C, FN_ATAG1_N,
 286         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 287         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 288         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
 289
 290         /* IPSR11 */
 291         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
 292         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
 293         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 294         FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 295         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 296         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 297         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 298         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 299         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 300         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 301         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 302         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 303         FN_VI1_DATA7, FN_AVB_MDC,
 304         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
 305         FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
 306
 307         /* IPSR12 */
 308         FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
 309         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
 310         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 311         FN_SCL2_D, FN_MSIOF1_RXD_E,
 312         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
 313         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 314         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 315         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 316         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 317         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 318         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 319         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 320         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 321         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 322         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 323         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 324         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 325
 326         /* IPSR13 */
 327         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 328         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 329         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 330         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 331         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 332         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 333         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 334         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 335         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 336         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 337         FN_SCIFA5_TXD_B, FN_TX3_C,
 338         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 339         FN_SCIFA5_RXD_B, FN_RX3_C,
 340         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 341         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 342         FN_SD1_DATA3, FN_IERX_B,
 343         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
 344
 345         /* IPSR14 */
 346         FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
 347         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 348         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 349         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 350         FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 351         FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 352         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 353         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 354         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 355         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 356         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 357         FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
 358         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 359         FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
 360
 361         /* IPSR15 */
 362         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 363         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 364         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 365         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 366         FN_PWM5_B, FN_SCIFA3_TXD_C,
 367         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 368         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 369         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 370         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 371         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 372         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 373         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 374         FN_TCLK2, FN_VI1_DATA3_C,
 375         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 376         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 377
 378         /* IPSR16 */
 379         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 380         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 381         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
 382         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 383         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 384
 385         /* MOD_SEL */
 386         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 387         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 388         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 389         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 390         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 391         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 392         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 393         FN_SEL_QSP_0, FN_SEL_QSP_1,
 394         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 395         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 396         FN_SEL_HSCIF1_4,
 397         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 398         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 399         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 400         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 401         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 402
 403         /* MOD_SEL2 */
 404         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 405         FN_SEL_SCIF0_4,
 406         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 407         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 408         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 409         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 410         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 411         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 412         FN_SEL_ADG_0, FN_SEL_ADG_1,
 413         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 414         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 415         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 416         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 417         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 418         FN_SEL_SIM_0, FN_SEL_SIM_1,
 419         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 420
 421         /* MOD_SEL3 */
 422         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 423         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 424         FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
 425         FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
 426         FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
 427         FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
 428         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 429         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 430         FN_SEL_MMC_0, FN_SEL_MMC_1,
 431         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 432         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 433         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
 434         FN_SEL_IIC1_4,
 435         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 436
 437         /* MOD_SEL4 */
 438         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 439         FN_SEL_SOF1_4,
 440         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 441         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 442         FN_SEL_RAD_0, FN_SEL_RAD_1,
 443         FN_SEL_RCN_0, FN_SEL_RCN_1,
 444         FN_SEL_RSP_0, FN_SEL_RSP_1,
 445         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 446         FN_SEL_SCIF2_4,
 447         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 448         FN_SEL_SOF2_4,
 449         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 450         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 451         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 452         PINMUX_FUNCTION_END,
 453
 454         PINMUX_MARK_BEGIN,
 455
 456         EX_CS0_N_MARK, RD_N_MARK,
 457
 458         AUDIO_CLKA_MARK,
 459
 460         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 461         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 462         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 463
 464         SD1_CLK_MARK,
 465
 466         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 467         DU0_DOTCLKIN_MARK,
 468
 469         /* IPSR0 */
 470         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 471         D6_MARK, D7_MARK, D8_MARK,
 472         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 473         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
 474         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 475         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 476         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 477
 478         /* IPSR1 */
 479         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
 480         A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
 481         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 482         A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
 483         A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
 484         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 485         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 486         A15_MARK, BPFCLK_C_MARK,
 487         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 488         A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
 489         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 490
 491         /* IPSR2 */
 492         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 493         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 494         A20_MARK, SPCLK_MARK,
 495         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 496         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 497         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 498         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 499         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 500         RX1_MARK, SCIFA1_RXD_MARK,
 501         CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
 502         CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
 503         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 504         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 505         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 506         ATAG0_N_MARK, EX_WAIT1_MARK,
 507
 508         /* IPSR3 */
 509         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 510         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 511         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 512         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 513         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 514         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 515         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 516         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 517         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 518         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 519         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 520         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 521         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 522         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 523         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 524         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 525         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 526         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 527
 528         /* IPSR4 */
 529         SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
 530         SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
 531         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 532         SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
 533         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 534         SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
 535         SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
 536         SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 537         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 538         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 539         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 540         SSI_SCK4_MARK, GLO_SS_D_MARK,
 541         SSI_WS4_MARK, GLO_RFON_D_MARK,
 542         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 543         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 544         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 545
 546         /* IPSR5 */
 547         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 548         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 549         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 550         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 551         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 552         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 553         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 554         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 555         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 556         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 557         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 558         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 559         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 560         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 561         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 562
 563         /* IPSR6 */
 564         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 565         SCIF_CLK_MARK, BPFCLK_E_MARK,
 566         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 567         SCIFA2_RXD_MARK, FMIN_E_MARK,
 568         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 569         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 570         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 571         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 572         IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 573         IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
 574         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 575         IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
 576         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 577         SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
 578         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 579         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 580         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 581         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 582
 583         /* IPSR7 */
 584         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 585         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 586         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 587         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 588         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 589         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 590         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 591         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 592         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 593         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 594         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 595         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 596         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 597         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 598         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 599         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 600         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 601         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 602
 603         /* IPSR8 */
 604         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 605         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 606         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 607         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 608         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 609         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 610         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 611         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 612         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 613         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 614         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 615         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 616         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 617         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 618         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 619         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 620         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 621         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 622
 623         /* IPSR9 */
 624         DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 625         DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
 626         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 627         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 628         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 629         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 630         TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
 631         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 632         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 633         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 634         CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
 635         DU1_DISP_MARK, QPOLA_MARK,
 636         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 637         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 638         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 639         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 640         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 641         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 642         VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
 643         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 644
 645         /* IPSR10 */
 646         VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
 647         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 648         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
 649         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 650         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
 651         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 652         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 653         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 654         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 655         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 656         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 657         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 658         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 659         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 660         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 661         TS_SCK0_C_MARK, ATAG1_N_MARK,
 662         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 663         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 664         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
 665
 666         /* IPSR11 */
 667         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
 668         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
 669         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 670         SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 671         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 672         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 673         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 674         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 675         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 676         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 677         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 678         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 679         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 680         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 681         VI1_DATA7_MARK, AVB_MDC_MARK,
 682         ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
 683         ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
 684
 685         /* IPSR12 */
 686         ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
 687         ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
 688         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 689         SCL2_D_MARK, MSIOF1_RXD_E_MARK,
 690         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 691         SDA2_D_MARK, MSIOF1_SCK_E_MARK,
 692         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 693         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 694         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 695         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 696         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 697         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 698         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 699         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 700         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 701         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 702         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 703         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 704
 705         /* IPSR13 */
 706         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 707         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 708         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 709         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 710         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 711         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 712         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 713         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 714         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 715         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 716         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 717         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 718         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 719         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 720         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 721         SD1_DATA3_MARK, IERX_B_MARK,
 722         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
 723
 724         /* IPSR14 */
 725         SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
 726         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 727         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 728         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 729         SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
 730         SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
 731         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 732         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 733         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 734         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 735         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 736         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 737         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 738         VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
 739         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 740         VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
 741
 742         /* IPSR15 */
 743         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 744         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 745         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 746         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 747         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 748         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 749         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 750         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 751         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 752         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 753         TCLK1_MARK, VI1_DATA1_C_MARK,
 754         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 755         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 756         TCLK2_MARK, VI1_DATA3_C_MARK,
 757         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 758         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 759         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 760         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 761
 762         /* IPSR16 */
 763         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 764         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 765         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 766         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 767         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
 768         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 769         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 770         PINMUX_MARK_END,
 771 };
 772
 773 static const u16 pinmux_data[] = {
 774         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 775
 776         PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
 777         PINMUX_DATA(RD_N_MARK, FN_RD_N),
 778         PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
 779         PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
 780         PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
 781         PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
 782         PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
 783         PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
 784         PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
 785         PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
 786         PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
 787         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 788         PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
 789         PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
 790         PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
 791         PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
 792         PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
 793
 794         /* IPSR0 */
 795         PINMUX_IPSR_DATA(IP0_0, D0),
 796         PINMUX_IPSR_DATA(IP0_1, D1),
 797         PINMUX_IPSR_DATA(IP0_2, D2),
 798         PINMUX_IPSR_DATA(IP0_3, D3),
 799         PINMUX_IPSR_DATA(IP0_4, D4),
 800         PINMUX_IPSR_DATA(IP0_5, D5),
 801         PINMUX_IPSR_DATA(IP0_6, D6),
 802         PINMUX_IPSR_DATA(IP0_7, D7),
 803         PINMUX_IPSR_DATA(IP0_8, D8),
 804         PINMUX_IPSR_DATA(IP0_9, D9),
 805         PINMUX_IPSR_DATA(IP0_10, D10),
 806         PINMUX_IPSR_DATA(IP0_11, D11),
 807         PINMUX_IPSR_DATA(IP0_12, D12),
 808         PINMUX_IPSR_DATA(IP0_13, D13),
 809         PINMUX_IPSR_DATA(IP0_14, D14),
 810         PINMUX_IPSR_DATA(IP0_15, D15),
 811         PINMUX_IPSR_DATA(IP0_18_16, A0),
 812         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 813         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 814         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2),
 815         PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
 816         PINMUX_IPSR_DATA(IP0_20_19, A1),
 817         PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 818         PINMUX_IPSR_DATA(IP0_22_21, A2),
 819         PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 820         PINMUX_IPSR_DATA(IP0_24_23, A3),
 821         PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 822         PINMUX_IPSR_DATA(IP0_26_25, A4),
 823         PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 824         PINMUX_IPSR_DATA(IP0_28_27, A5),
 825         PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 826         PINMUX_IPSR_DATA(IP0_30_29, A6),
 827         PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 828
 829         /* IPSR1 */
 830         PINMUX_IPSR_DATA(IP1_1_0, A7),
 831         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 832         PINMUX_IPSR_DATA(IP1_3_2, A8),
 833         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 834         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0),
 835         PINMUX_IPSR_DATA(IP1_5_4, A9),
 836         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 837         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0),
 838         PINMUX_IPSR_DATA(IP1_7_6, A10),
 839         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 840         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 841         PINMUX_IPSR_DATA(IP1_10_8, A11),
 842         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 843         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3),
 844         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 845         PINMUX_IPSR_DATA(IP1_13_11, A12),
 846         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0),
 847         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3),
 848         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 849         PINMUX_IPSR_DATA(IP1_16_14, A13),
 850         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 851         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0),
 852         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 853         PINMUX_IPSR_DATA(IP1_19_17, A14),
 854         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 855         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0),
 856         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2),
 857         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 858         PINMUX_IPSR_DATA(IP1_22_20, A15),
 859         PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2),
 860         PINMUX_IPSR_DATA(IP1_25_23, A16),
 861         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1),
 862         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2),
 863         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 864         PINMUX_IPSR_DATA(IP1_28_26, A17),
 865         PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1),
 866         PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2),
 867         PINMUX_IPSR_DATA(IP1_31_29, A18),
 868         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0),
 869         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 870         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 871
 872         /* IPSR2 */
 873         PINMUX_IPSR_DATA(IP2_2_0, A19),
 874         PINMUX_IPSR_DATA(IP2_2_0, DACK1),
 875         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 876         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 877         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0),
 878         PINMUX_IPSR_DATA(IP2_2_0, A20),
 879         PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0),
 880         PINMUX_IPSR_DATA(IP2_6_5, A21),
 881         PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 882         PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 883         PINMUX_IPSR_DATA(IP2_9_7, A22),
 884         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0),
 885         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1),
 886         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0),
 887         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 888         PINMUX_IPSR_DATA(IP2_12_10, A23),
 889         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0),
 890         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1),
 891         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0),
 892         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 893         PINMUX_IPSR_DATA(IP2_15_13, A24),
 894         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0),
 895         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0),
 896         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0),
 897         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 898         PINMUX_IPSR_DATA(IP2_18_16, A25),
 899         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0),
 900         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0),
 901         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2),
 902         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0),
 903         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 904         PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
 905         PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 906         PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0),
 907         PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
 908         PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 909         PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0),
 910         PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
 911         PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 912         PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
 913         PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 914         PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 915         PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
 916         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 917         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 918         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0),
 919         PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
 920
 921         /* IPSR3 */
 922         PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
 923         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0),
 924         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 925         PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
 926         PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
 927         PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
 928         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 929         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 930         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 931         PINMUX_IPSR_DATA(IP3_5_3, PWM1),
 932         PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
 933         PINMUX_IPSR_DATA(IP3_8_6, BS_N),
 934         PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
 935         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 936         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 937         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 938         PINMUX_IPSR_DATA(IP3_8_6, PWM2),
 939         PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
 940         PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
 941         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 942         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1),
 943         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 944         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1),
 945         PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
 946         PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 947         PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 948         PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
 949         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 950         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 951         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 952         PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
 953         PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 954         PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 955         PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
 956         PINMUX_IPSR_DATA(IP3_19_18, PWM3),
 957         PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
 958         PINMUX_IPSR_DATA(IP3_21_20, DACK0),
 959         PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
 960         PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0),
 961         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0),
 962         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 963         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 964         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 965         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 966         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2),
 967         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 968         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 969         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 970         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 971         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 972         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 973         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 974         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 975         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 976         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 977         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 978
 979         /* IPSR4 */
 980         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
 981         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1),
 982         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1),
 983         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
 984         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
 985         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1),
 986         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1),
 987         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
 988         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3),
 989         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0),
 990         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1),
 991         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1),
 992         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
 993         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3),
 994         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
 995         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1),
 996         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1),
 997         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
 998         PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
 999         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0),
1000         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1001         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1002         PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1003         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0),
1004         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1005         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4),
1006         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1007         PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1008         PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1009         PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4),
1010         PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1011         PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1012         PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1013         PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1014         PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1015         PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1016         PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1017         PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1018         PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1019         PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1020         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1021         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1022         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0),
1023         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1024         PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1025
1026         /* IPSR5 */
1027         PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1028         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1029         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1030         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0),
1031         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1032         PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1033         PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1034         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1035         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1036         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0),
1037         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1038         PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1039         PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1040         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1041         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1042         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0),
1043         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1044         PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1045         PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1046         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1047         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1048         PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1049         PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1050         PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1051         PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1052         PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1053         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1054         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1055         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0),
1056         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1057         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3),
1058         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1059         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0),
1060         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1061         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3),
1062         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1063         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1064         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3),
1065         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1066         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1067         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3),
1068         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1069         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1070         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3),
1071         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1072         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1073         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1074         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3),
1075         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1076
1077         /* IPSR6 */
1078         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1079         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1080         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1081         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1082         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
1083         PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1084         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1085         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1086         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
1087         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1088         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
1089         PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1090         PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1091         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
1092         PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1093         PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1094         PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1095         PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1096         PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1097         PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1098         PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1099         PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1100         PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1101         PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1102         PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1103         PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
1104         PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1105         PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1106         PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1107         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1108         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
1109         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1110         PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1111         PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1112         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1113         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
1114         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1115         PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1116         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1117         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1118         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
1119         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1120         PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1121         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1122         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1123         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1124         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1125         PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1126         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1127         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1128         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1129         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1130
1131         /* IPSR7 */
1132         PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1133         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1134         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1135         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1136         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1137         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1138         PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1139         PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1140         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1141         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1),
1142         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1143         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1144         PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1145         PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1146         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1147         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1),
1148         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1149         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1150         PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1151         PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1152         PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1153         PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1154         PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1155         PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1156         PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1157         PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1158         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1159         PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1160         PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1161         PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1162         PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1163         PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1164         PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1165         PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1166         PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1167         PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1168         PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1169         PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1170         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1171         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1),
1172         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1173         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1174         PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1175         PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1176         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1177         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1),
1178         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1179         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1180         PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1181         PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1182         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1183         PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1184         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1185         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1186
1187         /* IPSR8 */
1188         PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1189         PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1190         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1191         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1192         PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1193         PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1194         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1195         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1196         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1197         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1198         PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1199         PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1200         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1201         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1202         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1203         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1204         PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1205         PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1206         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1207         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1208         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1209         PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1210         PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1211         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1212         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1213         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1214         PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1215         PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1216         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1217         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1),
1218         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1219         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1220         PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1221         PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1222         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1223         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1),
1224         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1225         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1226         PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1227         PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1228         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1229         PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1230         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1231         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1232         PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1233         PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1234         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1235         PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1236         PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1237         PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1238         PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1239         PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1240         PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1241         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0),
1242         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1243         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1244
1245         /* IPSR9 */
1246         PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1247         PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1248         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2),
1249         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0),
1250         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1251         PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1252         PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1253         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2),
1254         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1255         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1256         PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1257         PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1258         PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1259         PINMUX_IPSR_DATA(IP9_7, QCLK),
1260         PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1261         PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1262         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1263         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1),
1264         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1),
1265         PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1266         PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1267         PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1268         PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1269         PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1270         PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1271         PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1272         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1273         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1),
1274         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1),
1275         PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1276         PINMUX_IPSR_DATA(IP9_16, QPOLA),
1277         PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1278         PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1279         PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1280         PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1281         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0),
1282         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1283         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1284         PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1285         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0),
1286         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1287         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1288         PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1289         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0),
1290         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1291         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1292         PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1293         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0),
1294         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1295         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1296         PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1297         PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1298         PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1299         PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1300         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0),
1301         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1302         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0),
1303         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1304         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1305         PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1306
1307         /* IPSR10 */
1308         PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1309         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0),
1310         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1311         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0),
1312         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1313         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1314         PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1315         PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1316         PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1317         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1318         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1),
1319         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1320         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1321         PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1322         PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1323         PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1324         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1325         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1),
1326         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0),
1327         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1328         PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1329         PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1330         PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1331         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1332         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0),
1333         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1334         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1335         PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1336         PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1337         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1338         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3),
1339         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1340         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1341         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1342         PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1343         PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1344         PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3),
1345         PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1346         PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1347         PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3),
1348         PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1349         PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1350         PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1351         PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1352         PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1353         PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1354         PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1355         PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1356         PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1357         PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1358         PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1359         PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1360         PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1361         PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1362         PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1363         PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1364         PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1365         PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1366         PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1367         PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1368         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1369         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2),
1370         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3),
1371
1372         /* IPSR11 */
1373         PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1374         PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1375         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1376         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
1377         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
1378         PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1379         PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1380         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1381         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
1382         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
1383         PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1384         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1385         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
1386         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1387         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
1388         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1389         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1390         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1391         PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1392         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1393         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
1394         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1395         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1396         PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1397         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1398         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
1399         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1400         PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1401         PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1402         PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1403         PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1404         PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1405         PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1406         PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
1407         PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1408         PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
1409         PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1410         PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
1411         PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1412         PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
1413         PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1414         PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
1415         PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1416         PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
1417         PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1418         PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
1419         PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1420         PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
1421         PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1422         PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
1423         PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1424         PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1425         PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1426         PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
1427         PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1428         PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1429         PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
1430
1431         /* IPSR12 */
1432         PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1433         PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1434         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
1435         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
1436         PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1437         PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1438         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
1439         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
1440         PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1441         PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1442         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1443         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
1444         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1445         PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1446         PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1447         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1448         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
1449         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1450         PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1451         PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1452         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1453         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1454         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1455         PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1456         PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1457         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1458         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1459         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1460         PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1461         PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1462         PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1463         PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1464         PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1465         PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1466         PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
1467         PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1468         PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1469         PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
1470         PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1471         PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1472         PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
1473         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1474         PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1475         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1476         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1477         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1478         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1479         PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1480         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1481         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1482         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1483
1484         /* IPSR13 */
1485         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1486         PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1487         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1488         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
1489         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1490         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1491         PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1492         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1493         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1494         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1495         PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1496         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1497         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1498         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1499         PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1500         PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1501         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1502         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1503         PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1504         PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
1505         PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1506         PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1507         PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1508         PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
1509         PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1510         PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
1511         PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1512         PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
1513         PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1514         PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
1515         PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1516         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1517         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1518         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1519         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1520         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
1521         PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1522         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1523         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1524         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1525         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1526         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
1527         PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1528         PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
1529         PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1530         PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1531         PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1532         PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
1533         PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1534         PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
1535         PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1536         PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
1537         PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1538         PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1539         PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1540         PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
1541
1542         /* IPSR14 */
1543         PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1544         PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1545         PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
1546         PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1547         PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1548         PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1549         PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1550         PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1551         PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1552         PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1553         PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1554         PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1555         PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1556         PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1557         PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1558         PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1559         PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1560         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
1561         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
1562         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1563         PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1564         PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1565         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
1566         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
1567         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1568         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1569         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
1570         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
1571         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1572         PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1573         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1574         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
1575         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1576         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1577         PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1578         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1579         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
1580         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1581         PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1582         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1583         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
1584         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1585         PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1586         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1587         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
1588         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
1589         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
1590         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1591         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
1592         PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1593         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1594         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
1595         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
1596         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
1597         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1598         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
1599         PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1600
1601         /* IPSR15 */
1602         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
1603         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
1604         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1605         PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1606         PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
1607         PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1608         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
1609         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
1610         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1611         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
1612         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1613         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1614         PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1615         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1616         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1617         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
1618         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1619         PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1620         PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1621         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1622         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
1623         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
1624         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1625         PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1626         PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1627         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1628         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1629         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1630         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1631         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
1632         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1633         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1634         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1635         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1636         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1637         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1638         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1639         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1640         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1641         PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1642         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1643         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
1644         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1645         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1646         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1647         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1648         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
1649         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1650         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1651         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1652         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1653
1654         /* IPSR16 */
1655         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
1656         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1657         PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1658         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1659         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1660         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
1661         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1662         PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1663         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1664         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1665         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1666         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1667         PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
1668         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1669         PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1670         PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1671         PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1672         PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1673         PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1674         PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1675         PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1676         PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1677 };
1678
1679 static const struct sh_pfc_pin pinmux_pins[] = {
1680         PINMUX_GPIO_GP_ALL(),
1681 };
1682
1683 /* - DU --------------------------------------------------------------------- */
1684 static const unsigned int du_rgb666_pins[] = {
1685         /* R[7:2], G[7:2], B[7:2] */
1686         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1687         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1688         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1689         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1690         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1691         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1692 };
1693 static const unsigned int du_rgb666_mux[] = {
1694         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1695         DU1_DR3_MARK, DU1_DR2_MARK,
1696         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1697         DU1_DG3_MARK, DU1_DG2_MARK,
1698         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1699         DU1_DB3_MARK, DU1_DB2_MARK,
1700 };
1701 static const unsigned int du_rgb888_pins[] = {
1702         /* R[7:0], G[7:0], B[7:0] */
1703         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1704         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1705         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
1706         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1707         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1708         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
1709         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1710         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1711         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1712 };
1713 static const unsigned int du_rgb888_mux[] = {
1714         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1715         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1716         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1717         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1718         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1719         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1720 };
1721 static const unsigned int du_clk_out_0_pins[] = {
1722         /* CLKOUT */
1723         RCAR_GP_PIN(3, 25),
1724 };
1725 static const unsigned int du_clk_out_0_mux[] = {
1726         DU1_DOTCLKOUT0_MARK
1727 };
1728 static const unsigned int du_clk_out_1_pins[] = {
1729         /* CLKOUT */
1730         RCAR_GP_PIN(3, 26),
1731 };
1732 static const unsigned int du_clk_out_1_mux[] = {
1733         DU1_DOTCLKOUT1_MARK
1734 };
1735 static const unsigned int du_sync_pins[] = {
1736         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1737         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1738 };
1739 static const unsigned int du_sync_mux[] = {
1740         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1741 };
1742 static const unsigned int du_oddf_pins[] = {
1743         /* EXDISP/EXODDF/EXCDE */
1744         RCAR_GP_PIN(3, 29),
1745 };
1746 static const unsigned int du_oddf_mux[] = {
1747         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1748 };
1749 static const unsigned int du_cde_pins[] = {
1750         /* CDE */
1751         RCAR_GP_PIN(3, 31),
1752 };
1753 static const unsigned int du_cde_mux[] = {
1754         DU1_CDE_MARK,
1755 };
1756 static const unsigned int du_disp_pins[] = {
1757         /* DISP */
1758         RCAR_GP_PIN(3, 30),
1759 };
1760 static const unsigned int du_disp_mux[] = {
1761         DU1_DISP_MARK,
1762 };
1763 static const unsigned int du0_clk_in_pins[] = {
1764         /* CLKIN */
1765         RCAR_GP_PIN(6, 31),
1766 };
1767 static const unsigned int du0_clk_in_mux[] = {
1768         DU0_DOTCLKIN_MARK
1769 };
1770 static const unsigned int du1_clk_in_pins[] = {
1771         /* CLKIN */
1772         RCAR_GP_PIN(3, 24),
1773 };
1774 static const unsigned int du1_clk_in_mux[] = {
1775         DU1_DOTCLKIN_MARK
1776 };
1777 static const unsigned int du1_clk_in_b_pins[] = {
1778         /* CLKIN */
1779         RCAR_GP_PIN(7, 19),
1780 };
1781 static const unsigned int du1_clk_in_b_mux[] = {
1782         DU1_DOTCLKIN_B_MARK,
1783 };
1784 static const unsigned int du1_clk_in_c_pins[] = {
1785         /* CLKIN */
1786         RCAR_GP_PIN(7, 20),
1787 };
1788 static const unsigned int du1_clk_in_c_mux[] = {
1789         DU1_DOTCLKIN_C_MARK,
1790 };
1791 /* - ETH -------------------------------------------------------------------- */
1792 static const unsigned int eth_link_pins[] = {
1793         /* LINK */
1794         RCAR_GP_PIN(5, 18),
1795 };
1796 static const unsigned int eth_link_mux[] = {
1797         ETH_LINK_MARK,
1798 };
1799 static const unsigned int eth_magic_pins[] = {
1800         /* MAGIC */
1801         RCAR_GP_PIN(5, 22),
1802 };
1803 static const unsigned int eth_magic_mux[] = {
1804         ETH_MAGIC_MARK,
1805 };
1806 static const unsigned int eth_mdio_pins[] = {
1807         /* MDC, MDIO */
1808         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1809 };
1810 static const unsigned int eth_mdio_mux[] = {
1811         ETH_MDC_MARK, ETH_MDIO_MARK,
1812 };
1813 static const unsigned int eth_rmii_pins[] = {
1814         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1815         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
1816         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
1817         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
1818 };
1819 static const unsigned int eth_rmii_mux[] = {
1820         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1821         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1822 };
1823 /* - I2C0 ------------------------------------------------------------------- */
1824 static const unsigned int i2c0_pins[] = {
1825         /* SCL, SDA */
1826         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
1827 };
1828 static const unsigned int i2c0_mux[] = {
1829         SCL0_MARK, SDA0_MARK,
1830 };
1831 static const unsigned int i2c0_b_pins[] = {
1832         /* SCL, SDA */
1833         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1834 };
1835 static const unsigned int i2c0_b_mux[] = {
1836         SCL0_B_MARK, SDA0_B_MARK,
1837 };
1838 static const unsigned int i2c0_c_pins[] = {
1839         /* SCL, SDA */
1840         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
1841 };
1842 static const unsigned int i2c0_c_mux[] = {
1843         SCL0_C_MARK, SDA0_C_MARK,
1844 };
1845 /* - I2C1 ------------------------------------------------------------------- */
1846 static const unsigned int i2c1_pins[] = {
1847         /* SCL, SDA */
1848         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1849 };
1850 static const unsigned int i2c1_mux[] = {
1851         SCL1_MARK, SDA1_MARK,
1852 };
1853 static const unsigned int i2c1_b_pins[] = {
1854         /* SCL, SDA */
1855         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1856 };
1857 static const unsigned int i2c1_b_mux[] = {
1858         SCL1_B_MARK, SDA1_B_MARK,
1859 };
1860 static const unsigned int i2c1_c_pins[] = {
1861         /* SCL, SDA */
1862         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1863 };
1864 static const unsigned int i2c1_c_mux[] = {
1865         SCL1_C_MARK, SDA1_C_MARK,
1866 };
1867 static const unsigned int i2c1_d_pins[] = {
1868         /* SCL, SDA */
1869         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1870 };
1871 static const unsigned int i2c1_d_mux[] = {
1872         SCL1_D_MARK, SDA1_D_MARK,
1873 };
1874 static const unsigned int i2c1_e_pins[] = {
1875         /* SCL, SDA */
1876         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
1877 };
1878 static const unsigned int i2c1_e_mux[] = {
1879         SCL1_E_MARK, SDA1_E_MARK,
1880 };
1881 /* - I2C2 ------------------------------------------------------------------- */
1882 static const unsigned int i2c2_pins[] = {
1883         /* SCL, SDA */
1884         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1885 };
1886 static const unsigned int i2c2_mux[] = {
1887         SCL2_MARK, SDA2_MARK,
1888 };
1889 static const unsigned int i2c2_b_pins[] = {
1890         /* SCL, SDA */
1891         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1892 };
1893 static const unsigned int i2c2_b_mux[] = {
1894         SCL2_B_MARK, SDA2_B_MARK,
1895 };
1896 static const unsigned int i2c2_c_pins[] = {
1897         /* SCL, SDA */
1898         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1899 };
1900 static const unsigned int i2c2_c_mux[] = {
1901         SCL2_C_MARK, SDA2_C_MARK,
1902 };
1903 static const unsigned int i2c2_d_pins[] = {
1904         /* SCL, SDA */
1905         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1906 };
1907 static const unsigned int i2c2_d_mux[] = {
1908         SCL2_D_MARK, SDA2_D_MARK,
1909 };
1910 /* - I2C3 ------------------------------------------------------------------- */
1911 static const unsigned int i2c3_pins[] = {
1912         /* SCL, SDA */
1913         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1914 };
1915 static const unsigned int i2c3_mux[] = {
1916         SCL3_MARK, SDA3_MARK,
1917 };
1918 static const unsigned int i2c3_b_pins[] = {
1919         /* SCL, SDA */
1920         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1921 };
1922 static const unsigned int i2c3_b_mux[] = {
1923         SCL3_B_MARK, SDA3_B_MARK,
1924 };
1925 static const unsigned int i2c3_c_pins[] = {
1926         /* SCL, SDA */
1927         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
1928 };
1929 static const unsigned int i2c3_c_mux[] = {
1930         SCL3_C_MARK, SDA3_C_MARK,
1931 };
1932 static const unsigned int i2c3_d_pins[] = {
1933         /* SCL, SDA */
1934         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1935 };
1936 static const unsigned int i2c3_d_mux[] = {
1937         SCL3_D_MARK, SDA3_D_MARK,
1938 };
1939 /* - I2C4 ------------------------------------------------------------------- */
1940 static const unsigned int i2c4_pins[] = {
1941         /* SCL, SDA */
1942         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1943 };
1944 static const unsigned int i2c4_mux[] = {
1945         SCL4_MARK, SDA4_MARK,
1946 };
1947 static const unsigned int i2c4_b_pins[] = {
1948         /* SCL, SDA */
1949         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
1950 };
1951 static const unsigned int i2c4_b_mux[] = {
1952         SCL4_B_MARK, SDA4_B_MARK,
1953 };
1954 static const unsigned int i2c4_c_pins[] = {
1955         /* SCL, SDA */
1956         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1957 };
1958 static const unsigned int i2c4_c_mux[] = {
1959         SCL4_C_MARK, SDA4_C_MARK,
1960 };
1961 /* - I2C7 ------------------------------------------------------------------- */
1962 static const unsigned int i2c7_pins[] = {
1963         /* SCL, SDA */
1964         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1965 };
1966 static const unsigned int i2c7_mux[] = {
1967         SCL7_MARK, SDA7_MARK,
1968 };
1969 static const unsigned int i2c7_b_pins[] = {
1970         /* SCL, SDA */
1971         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1972 };
1973 static const unsigned int i2c7_b_mux[] = {
1974         SCL7_B_MARK, SDA7_B_MARK,
1975 };
1976 static const unsigned int i2c7_c_pins[] = {
1977         /* SCL, SDA */
1978         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
1979 };
1980 static const unsigned int i2c7_c_mux[] = {
1981         SCL7_C_MARK, SDA7_C_MARK,
1982 };
1983 /* - I2C8 ------------------------------------------------------------------- */
1984 static const unsigned int i2c8_pins[] = {
1985         /* SCL, SDA */
1986         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1987 };
1988 static const unsigned int i2c8_mux[] = {
1989         SCL8_MARK, SDA8_MARK,
1990 };
1991 static const unsigned int i2c8_b_pins[] = {
1992         /* SCL, SDA */
1993         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1994 };
1995 static const unsigned int i2c8_b_mux[] = {
1996         SCL8_B_MARK, SDA8_B_MARK,
1997 };
1998 static const unsigned int i2c8_c_pins[] = {
1999         /* SCL, SDA */
2000         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2001 };
2002 static const unsigned int i2c8_c_mux[] = {
2003         SCL8_C_MARK, SDA8_C_MARK,
2004 };
2005 /* - INTC ------------------------------------------------------------------- */
2006 static const unsigned int intc_irq0_pins[] = {
2007         /* IRQ */
2008         RCAR_GP_PIN(7, 10),
2009 };
2010 static const unsigned int intc_irq0_mux[] = {
2011         IRQ0_MARK,
2012 };
2013 static const unsigned int intc_irq1_pins[] = {
2014         /* IRQ */
2015         RCAR_GP_PIN(7, 11),
2016 };
2017 static const unsigned int intc_irq1_mux[] = {
2018         IRQ1_MARK,
2019 };
2020 static const unsigned int intc_irq2_pins[] = {
2021         /* IRQ */
2022         RCAR_GP_PIN(7, 12),
2023 };
2024 static const unsigned int intc_irq2_mux[] = {
2025         IRQ2_MARK,
2026 };
2027 static const unsigned int intc_irq3_pins[] = {
2028         /* IRQ */
2029         RCAR_GP_PIN(7, 13),
2030 };
2031 static const unsigned int intc_irq3_mux[] = {
2032         IRQ3_MARK,
2033 };
2034 /* - MMCIF ------------------------------------------------------------------ */
2035 static const unsigned int mmc_data1_pins[] = {
2036         /* D[0] */
2037         RCAR_GP_PIN(6, 18),
2038 };
2039 static const unsigned int mmc_data1_mux[] = {
2040         MMC_D0_MARK,
2041 };
2042 static const unsigned int mmc_data4_pins[] = {
2043         /* D[0:3] */
2044         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2045         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2046 };
2047 static const unsigned int mmc_data4_mux[] = {
2048         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2049 };
2050 static const unsigned int mmc_data8_pins[] = {
2051         /* D[0:7] */
2052         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2053         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2054         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2055         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2056 };
2057 static const unsigned int mmc_data8_mux[] = {
2058         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2059         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2060 };
2061 static const unsigned int mmc_ctrl_pins[] = {
2062         /* CLK, CMD */
2063         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2064 };
2065 static const unsigned int mmc_ctrl_mux[] = {
2066         MMC_CLK_MARK, MMC_CMD_MARK,
2067 };
2068 /* - MSIOF0 ----------------------------------------------------------------- */
2069 static const unsigned int msiof0_clk_pins[] = {
2070         /* SCK */
2071         RCAR_GP_PIN(6, 24),
2072 };
2073 static const unsigned int msiof0_clk_mux[] = {
2074         MSIOF0_SCK_MARK,
2075 };
2076 static const unsigned int msiof0_sync_pins[] = {
2077         /* SYNC */
2078         RCAR_GP_PIN(6, 25),
2079 };
2080 static const unsigned int msiof0_sync_mux[] = {
2081         MSIOF0_SYNC_MARK,
2082 };
2083 static const unsigned int msiof0_ss1_pins[] = {
2084         /* SS1 */
2085         RCAR_GP_PIN(6, 28),
2086 };
2087 static const unsigned int msiof0_ss1_mux[] = {
2088         MSIOF0_SS1_MARK,
2089 };
2090 static const unsigned int msiof0_ss2_pins[] = {
2091         /* SS2 */
2092         RCAR_GP_PIN(6, 29),
2093 };
2094 static const unsigned int msiof0_ss2_mux[] = {
2095         MSIOF0_SS2_MARK,
2096 };
2097 static const unsigned int msiof0_rx_pins[] = {
2098         /* RXD */
2099         RCAR_GP_PIN(6, 27),
2100 };
2101 static const unsigned int msiof0_rx_mux[] = {
2102         MSIOF0_RXD_MARK,
2103 };
2104 static const unsigned int msiof0_tx_pins[] = {
2105         /* TXD */
2106         RCAR_GP_PIN(6, 26),
2107 };
2108 static const unsigned int msiof0_tx_mux[] = {
2109         MSIOF0_TXD_MARK,
2110 };
2111
2112 static const unsigned int msiof0_clk_b_pins[] = {
2113         /* SCK */
2114         RCAR_GP_PIN(0, 16),
2115 };
2116 static const unsigned int msiof0_clk_b_mux[] = {
2117         MSIOF0_SCK_B_MARK,
2118 };
2119 static const unsigned int msiof0_sync_b_pins[] = {
2120         /* SYNC */
2121         RCAR_GP_PIN(0, 17),
2122 };
2123 static const unsigned int msiof0_sync_b_mux[] = {
2124         MSIOF0_SYNC_B_MARK,
2125 };
2126 static const unsigned int msiof0_ss1_b_pins[] = {
2127         /* SS1 */
2128         RCAR_GP_PIN(0, 18),
2129 };
2130 static const unsigned int msiof0_ss1_b_mux[] = {
2131         MSIOF0_SS1_B_MARK,
2132 };
2133 static const unsigned int msiof0_ss2_b_pins[] = {
2134         /* SS2 */
2135         RCAR_GP_PIN(0, 19),
2136 };
2137 static const unsigned int msiof0_ss2_b_mux[] = {
2138         MSIOF0_SS2_B_MARK,
2139 };
2140 static const unsigned int msiof0_rx_b_pins[] = {
2141         /* RXD */
2142         RCAR_GP_PIN(0, 21),
2143 };
2144 static const unsigned int msiof0_rx_b_mux[] = {
2145         MSIOF0_RXD_B_MARK,
2146 };
2147 static const unsigned int msiof0_tx_b_pins[] = {
2148         /* TXD */
2149         RCAR_GP_PIN(0, 20),
2150 };
2151 static const unsigned int msiof0_tx_b_mux[] = {
2152         MSIOF0_TXD_B_MARK,
2153 };
2154
2155 static const unsigned int msiof0_clk_c_pins[] = {
2156         /* SCK */
2157         RCAR_GP_PIN(5, 26),
2158 };
2159 static const unsigned int msiof0_clk_c_mux[] = {
2160         MSIOF0_SCK_C_MARK,
2161 };
2162 static const unsigned int msiof0_sync_c_pins[] = {
2163         /* SYNC */
2164         RCAR_GP_PIN(5, 25),
2165 };
2166 static const unsigned int msiof0_sync_c_mux[] = {
2167         MSIOF0_SYNC_C_MARK,
2168 };
2169 static const unsigned int msiof0_ss1_c_pins[] = {
2170         /* SS1 */
2171         RCAR_GP_PIN(5, 27),
2172 };
2173 static const unsigned int msiof0_ss1_c_mux[] = {
2174         MSIOF0_SS1_C_MARK,
2175 };
2176 static const unsigned int msiof0_ss2_c_pins[] = {
2177         /* SS2 */
2178         RCAR_GP_PIN(5, 28),
2179 };
2180 static const unsigned int msiof0_ss2_c_mux[] = {
2181         MSIOF0_SS2_C_MARK,
2182 };
2183 static const unsigned int msiof0_rx_c_pins[] = {
2184         /* RXD */
2185         RCAR_GP_PIN(5, 29),
2186 };
2187 static const unsigned int msiof0_rx_c_mux[] = {
2188         MSIOF0_RXD_C_MARK,
2189 };
2190 static const unsigned int msiof0_tx_c_pins[] = {
2191         /* TXD */
2192         RCAR_GP_PIN(5, 30),
2193 };
2194 static const unsigned int msiof0_tx_c_mux[] = {
2195         MSIOF0_TXD_C_MARK,
2196 };
2197 /* - MSIOF1 ----------------------------------------------------------------- */
2198 static const unsigned int msiof1_clk_pins[] = {
2199         /* SCK */
2200         RCAR_GP_PIN(0, 22),
2201 };
2202 static const unsigned int msiof1_clk_mux[] = {
2203         MSIOF1_SCK_MARK,
2204 };
2205 static const unsigned int msiof1_sync_pins[] = {
2206         /* SYNC */
2207         RCAR_GP_PIN(0, 23),
2208 };
2209 static const unsigned int msiof1_sync_mux[] = {
2210         MSIOF1_SYNC_MARK,
2211 };
2212 static const unsigned int msiof1_ss1_pins[] = {
2213         /* SS1 */
2214         RCAR_GP_PIN(0, 24),
2215 };
2216 static const unsigned int msiof1_ss1_mux[] = {
2217         MSIOF1_SS1_MARK,
2218 };
2219 static const unsigned int msiof1_ss2_pins[] = {
2220         /* SS2 */
2221         RCAR_GP_PIN(0, 25),
2222 };
2223 static const unsigned int msiof1_ss2_mux[] = {
2224         MSIOF1_SS2_MARK,
2225 };
2226 static const unsigned int msiof1_rx_pins[] = {
2227         /* RXD */
2228         RCAR_GP_PIN(0, 27),
2229 };
2230 static const unsigned int msiof1_rx_mux[] = {
2231         MSIOF1_RXD_MARK,
2232 };
2233 static const unsigned int msiof1_tx_pins[] = {
2234         /* TXD */
2235         RCAR_GP_PIN(0, 26),
2236 };
2237 static const unsigned int msiof1_tx_mux[] = {
2238         MSIOF1_TXD_MARK,
2239 };
2240
2241 static const unsigned int msiof1_clk_b_pins[] = {
2242         /* SCK */
2243         RCAR_GP_PIN(2, 29),
2244 };
2245 static const unsigned int msiof1_clk_b_mux[] = {
2246         MSIOF1_SCK_B_MARK,
2247 };
2248 static const unsigned int msiof1_sync_b_pins[] = {
2249         /* SYNC */
2250         RCAR_GP_PIN(2, 30),
2251 };
2252 static const unsigned int msiof1_sync_b_mux[] = {
2253         MSIOF1_SYNC_B_MARK,
2254 };
2255 static const unsigned int msiof1_ss1_b_pins[] = {
2256         /* SS1 */
2257         RCAR_GP_PIN(2, 31),
2258 };
2259 static const unsigned int msiof1_ss1_b_mux[] = {
2260         MSIOF1_SS1_B_MARK,
2261 };
2262 static const unsigned int msiof1_ss2_b_pins[] = {
2263         /* SS2 */
2264         RCAR_GP_PIN(7, 16),
2265 };
2266 static const unsigned int msiof1_ss2_b_mux[] = {
2267         MSIOF1_SS2_B_MARK,
2268 };
2269 static const unsigned int msiof1_rx_b_pins[] = {
2270         /* RXD */
2271         RCAR_GP_PIN(7, 18),
2272 };
2273 static const unsigned int msiof1_rx_b_mux[] = {
2274         MSIOF1_RXD_B_MARK,
2275 };
2276 static const unsigned int msiof1_tx_b_pins[] = {
2277         /* TXD */
2278         RCAR_GP_PIN(7, 17),
2279 };
2280 static const unsigned int msiof1_tx_b_mux[] = {
2281         MSIOF1_TXD_B_MARK,
2282 };
2283
2284 static const unsigned int msiof1_clk_c_pins[] = {
2285         /* SCK */
2286         RCAR_GP_PIN(2, 15),
2287 };
2288 static const unsigned int msiof1_clk_c_mux[] = {
2289         MSIOF1_SCK_C_MARK,
2290 };
2291 static const unsigned int msiof1_sync_c_pins[] = {
2292         /* SYNC */
2293         RCAR_GP_PIN(2, 16),
2294 };
2295 static const unsigned int msiof1_sync_c_mux[] = {
2296         MSIOF1_SYNC_C_MARK,
2297 };
2298 static const unsigned int msiof1_rx_c_pins[] = {
2299         /* RXD */
2300         RCAR_GP_PIN(2, 18),
2301 };
2302 static const unsigned int msiof1_rx_c_mux[] = {
2303         MSIOF1_RXD_C_MARK,
2304 };
2305 static const unsigned int msiof1_tx_c_pins[] = {
2306         /* TXD */
2307         RCAR_GP_PIN(2, 17),
2308 };
2309 static const unsigned int msiof1_tx_c_mux[] = {
2310         MSIOF1_TXD_C_MARK,
2311 };
2312
2313 static const unsigned int msiof1_clk_d_pins[] = {
2314         /* SCK */
2315         RCAR_GP_PIN(0, 28),
2316 };
2317 static const unsigned int msiof1_clk_d_mux[] = {
2318         MSIOF1_SCK_D_MARK,
2319 };
2320 static const unsigned int msiof1_sync_d_pins[] = {
2321         /* SYNC */
2322         RCAR_GP_PIN(0, 30),
2323 };
2324 static const unsigned int msiof1_sync_d_mux[] = {
2325         MSIOF1_SYNC_D_MARK,
2326 };
2327 static const unsigned int msiof1_ss1_d_pins[] = {
2328         /* SS1 */
2329         RCAR_GP_PIN(0, 29),
2330 };
2331 static const unsigned int msiof1_ss1_d_mux[] = {
2332         MSIOF1_SS1_D_MARK,
2333 };
2334 static const unsigned int msiof1_rx_d_pins[] = {
2335         /* RXD */
2336         RCAR_GP_PIN(0, 27),
2337 };
2338 static const unsigned int msiof1_rx_d_mux[] = {
2339         MSIOF1_RXD_D_MARK,
2340 };
2341 static const unsigned int msiof1_tx_d_pins[] = {
2342         /* TXD */
2343         RCAR_GP_PIN(0, 26),
2344 };
2345 static const unsigned int msiof1_tx_d_mux[] = {
2346         MSIOF1_TXD_D_MARK,
2347 };
2348
2349 static const unsigned int msiof1_clk_e_pins[] = {
2350         /* SCK */
2351         RCAR_GP_PIN(5, 18),
2352 };
2353 static const unsigned int msiof1_clk_e_mux[] = {
2354         MSIOF1_SCK_E_MARK,
2355 };
2356 static const unsigned int msiof1_sync_e_pins[] = {
2357         /* SYNC */
2358         RCAR_GP_PIN(5, 19),
2359 };
2360 static const unsigned int msiof1_sync_e_mux[] = {
2361         MSIOF1_SYNC_E_MARK,
2362 };
2363 static const unsigned int msiof1_rx_e_pins[] = {
2364         /* RXD */
2365         RCAR_GP_PIN(5, 17),
2366 };
2367 static const unsigned int msiof1_rx_e_mux[] = {
2368         MSIOF1_RXD_E_MARK,
2369 };
2370 static const unsigned int msiof1_tx_e_pins[] = {
2371         /* TXD */
2372         RCAR_GP_PIN(5, 20),
2373 };
2374 static const unsigned int msiof1_tx_e_mux[] = {
2375         MSIOF1_TXD_E_MARK,
2376 };
2377 /* - MSIOF2 ----------------------------------------------------------------- */
2378 static const unsigned int msiof2_clk_pins[] = {
2379         /* SCK */
2380         RCAR_GP_PIN(1, 13),
2381 };
2382 static const unsigned int msiof2_clk_mux[] = {
2383         MSIOF2_SCK_MARK,
2384 };
2385 static const unsigned int msiof2_sync_pins[] = {
2386         /* SYNC */
2387         RCAR_GP_PIN(1, 14),
2388 };
2389 static const unsigned int msiof2_sync_mux[] = {
2390         MSIOF2_SYNC_MARK,
2391 };
2392 static const unsigned int msiof2_ss1_pins[] = {
2393         /* SS1 */
2394         RCAR_GP_PIN(1, 17),
2395 };
2396 static const unsigned int msiof2_ss1_mux[] = {
2397         MSIOF2_SS1_MARK,
2398 };
2399 static const unsigned int msiof2_ss2_pins[] = {
2400         /* SS2 */
2401         RCAR_GP_PIN(1, 18),
2402 };
2403 static const unsigned int msiof2_ss2_mux[] = {
2404         MSIOF2_SS2_MARK,
2405 };
2406 static const unsigned int msiof2_rx_pins[] = {
2407         /* RXD */
2408         RCAR_GP_PIN(1, 16),
2409 };
2410 static const unsigned int msiof2_rx_mux[] = {
2411         MSIOF2_RXD_MARK,
2412 };
2413 static const unsigned int msiof2_tx_pins[] = {
2414         /* TXD */
2415         RCAR_GP_PIN(1, 15),
2416 };
2417 static const unsigned int msiof2_tx_mux[] = {
2418         MSIOF2_TXD_MARK,
2419 };
2420
2421 static const unsigned int msiof2_clk_b_pins[] = {
2422         /* SCK */
2423         RCAR_GP_PIN(3, 0),
2424 };
2425 static const unsigned int msiof2_clk_b_mux[] = {
2426         MSIOF2_SCK_B_MARK,
2427 };
2428 static const unsigned int msiof2_sync_b_pins[] = {
2429         /* SYNC */
2430         RCAR_GP_PIN(3, 1),
2431 };
2432 static const unsigned int msiof2_sync_b_mux[] = {
2433         MSIOF2_SYNC_B_MARK,
2434 };
2435 static const unsigned int msiof2_ss1_b_pins[] = {
2436         /* SS1 */
2437         RCAR_GP_PIN(3, 8),
2438 };
2439 static const unsigned int msiof2_ss1_b_mux[] = {
2440         MSIOF2_SS1_B_MARK,
2441 };
2442 static const unsigned int msiof2_ss2_b_pins[] = {
2443         /* SS2 */
2444         RCAR_GP_PIN(3, 9),
2445 };
2446 static const unsigned int msiof2_ss2_b_mux[] = {
2447         MSIOF2_SS2_B_MARK,
2448 };
2449 static const unsigned int msiof2_rx_b_pins[] = {
2450         /* RXD */
2451         RCAR_GP_PIN(3, 17),
2452 };
2453 static const unsigned int msiof2_rx_b_mux[] = {
2454         MSIOF2_RXD_B_MARK,
2455 };
2456 static const unsigned int msiof2_tx_b_pins[] = {
2457         /* TXD */
2458         RCAR_GP_PIN(3, 16),
2459 };
2460 static const unsigned int msiof2_tx_b_mux[] = {
2461         MSIOF2_TXD_B_MARK,
2462 };
2463
2464 static const unsigned int msiof2_clk_c_pins[] = {
2465         /* SCK */
2466         RCAR_GP_PIN(2, 2),
2467 };
2468 static const unsigned int msiof2_clk_c_mux[] = {
2469         MSIOF2_SCK_C_MARK,
2470 };
2471 static const unsigned int msiof2_sync_c_pins[] = {
2472         /* SYNC */
2473         RCAR_GP_PIN(2, 3),
2474 };
2475 static const unsigned int msiof2_sync_c_mux[] = {
2476         MSIOF2_SYNC_C_MARK,
2477 };
2478 static const unsigned int msiof2_rx_c_pins[] = {
2479         /* RXD */
2480         RCAR_GP_PIN(2, 5),
2481 };
2482 static const unsigned int msiof2_rx_c_mux[] = {
2483         MSIOF2_RXD_C_MARK,
2484 };
2485 static const unsigned int msiof2_tx_c_pins[] = {
2486         /* TXD */
2487         RCAR_GP_PIN(2, 4),
2488 };
2489 static const unsigned int msiof2_tx_c_mux[] = {
2490         MSIOF2_TXD_C_MARK,
2491 };
2492
2493 static const unsigned int msiof2_clk_d_pins[] = {
2494         /* SCK */
2495         RCAR_GP_PIN(2, 14),
2496 };
2497 static const unsigned int msiof2_clk_d_mux[] = {
2498         MSIOF2_SCK_D_MARK,
2499 };
2500 static const unsigned int msiof2_sync_d_pins[] = {
2501         /* SYNC */
2502         RCAR_GP_PIN(2, 15),
2503 };
2504 static const unsigned int msiof2_sync_d_mux[] = {
2505         MSIOF2_SYNC_D_MARK,
2506 };
2507 static const unsigned int msiof2_ss1_d_pins[] = {
2508         /* SS1 */
2509         RCAR_GP_PIN(2, 17),
2510 };
2511 static const unsigned int msiof2_ss1_d_mux[] = {
2512         MSIOF2_SS1_D_MARK,
2513 };
2514 static const unsigned int msiof2_ss2_d_pins[] = {
2515         /* SS2 */
2516         RCAR_GP_PIN(2, 19),
2517 };
2518 static const unsigned int msiof2_ss2_d_mux[] = {
2519         MSIOF2_SS2_D_MARK,
2520 };
2521 static const unsigned int msiof2_rx_d_pins[] = {
2522         /* RXD */
2523         RCAR_GP_PIN(2, 18),
2524 };
2525 static const unsigned int msiof2_rx_d_mux[] = {
2526         MSIOF2_RXD_D_MARK,
2527 };
2528 static const unsigned int msiof2_tx_d_pins[] = {
2529         /* TXD */
2530         RCAR_GP_PIN(2, 16),
2531 };
2532 static const unsigned int msiof2_tx_d_mux[] = {
2533         MSIOF2_TXD_D_MARK,
2534 };
2535
2536 static const unsigned int msiof2_clk_e_pins[] = {
2537         /* SCK */
2538         RCAR_GP_PIN(7, 15),
2539 };
2540 static const unsigned int msiof2_clk_e_mux[] = {
2541         MSIOF2_SCK_E_MARK,
2542 };
2543 static const unsigned int msiof2_sync_e_pins[] = {
2544         /* SYNC */
2545         RCAR_GP_PIN(7, 16),
2546 };
2547 static const unsigned int msiof2_sync_e_mux[] = {
2548         MSIOF2_SYNC_E_MARK,
2549 };
2550 static const unsigned int msiof2_rx_e_pins[] = {
2551         /* RXD */
2552         RCAR_GP_PIN(7, 14),
2553 };
2554 static const unsigned int msiof2_rx_e_mux[] = {
2555         MSIOF2_RXD_E_MARK,
2556 };
2557 static const unsigned int msiof2_tx_e_pins[] = {
2558         /* TXD */
2559         RCAR_GP_PIN(7, 13),
2560 };
2561 static const unsigned int msiof2_tx_e_mux[] = {
2562         MSIOF2_TXD_E_MARK,
2563 };
2564 /* - QSPI ------------------------------------------------------------------- */
2565 static const unsigned int qspi_ctrl_pins[] = {
2566         /* SPCLK, SSL */
2567         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2568 };
2569 static const unsigned int qspi_ctrl_mux[] = {
2570         SPCLK_MARK, SSL_MARK,
2571 };
2572 static const unsigned int qspi_data2_pins[] = {
2573         /* MOSI_IO0, MISO_IO1 */
2574         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2575 };
2576 static const unsigned int qspi_data2_mux[] = {
2577         MOSI_IO0_MARK, MISO_IO1_MARK,
2578 };
2579 static const unsigned int qspi_data4_pins[] = {
2580         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2581         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2582         RCAR_GP_PIN(1, 8),
2583 };
2584 static const unsigned int qspi_data4_mux[] = {
2585         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2586 };
2587
2588 static const unsigned int qspi_ctrl_b_pins[] = {
2589         /* SPCLK, SSL */
2590         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
2591 };
2592 static const unsigned int qspi_ctrl_b_mux[] = {
2593         SPCLK_B_MARK, SSL_B_MARK,
2594 };
2595 static const unsigned int qspi_data2_b_pins[] = {
2596         /* MOSI_IO0, MISO_IO1 */
2597         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
2598 };
2599 static const unsigned int qspi_data2_b_mux[] = {
2600         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2601 };
2602 static const unsigned int qspi_data4_b_pins[] = {
2603         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2604         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2605         RCAR_GP_PIN(6, 4),
2606 };
2607 static const unsigned int qspi_data4_b_mux[] = {
2608         SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2609         IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
2610 };
2611 /* - SCIF0 ------------------------------------------------------------------ */
2612 static const unsigned int scif0_data_pins[] = {
2613         /* RX, TX */
2614         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2615 };
2616 static const unsigned int scif0_data_mux[] = {
2617         RX0_MARK, TX0_MARK,
2618 };
2619 static const unsigned int scif0_data_b_pins[] = {
2620         /* RX, TX */
2621         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2622 };
2623 static const unsigned int scif0_data_b_mux[] = {
2624         RX0_B_MARK, TX0_B_MARK,
2625 };
2626 static const unsigned int scif0_data_c_pins[] = {
2627         /* RX, TX */
2628         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
2629 };
2630 static const unsigned int scif0_data_c_mux[] = {
2631         RX0_C_MARK, TX0_C_MARK,
2632 };
2633 static const unsigned int scif0_data_d_pins[] = {
2634         /* RX, TX */
2635         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2636 };
2637 static const unsigned int scif0_data_d_mux[] = {
2638         RX0_D_MARK, TX0_D_MARK,
2639 };
2640 static const unsigned int scif0_data_e_pins[] = {
2641         /* RX, TX */
2642         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
2643 };
2644 static const unsigned int scif0_data_e_mux[] = {
2645         RX0_E_MARK, TX0_E_MARK,
2646 };
2647 /* - SCIF1 ------------------------------------------------------------------ */
2648 static const unsigned int scif1_data_pins[] = {
2649         /* RX, TX */
2650         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2651 };
2652 static const unsigned int scif1_data_mux[] = {
2653         RX1_MARK, TX1_MARK,
2654 };
2655 static const unsigned int scif1_data_b_pins[] = {
2656         /* RX, TX */
2657         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2658 };
2659 static const unsigned int scif1_data_b_mux[] = {
2660         RX1_B_MARK, TX1_B_MARK,
2661 };
2662 static const unsigned int scif1_clk_b_pins[] = {
2663         /* SCK */
2664         RCAR_GP_PIN(3, 10),
2665 };
2666 static const unsigned int scif1_clk_b_mux[] = {
2667         SCIF1_SCK_B_MARK,
2668 };
2669 static const unsigned int scif1_data_c_pins[] = {
2670         /* RX, TX */
2671         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
2672 };
2673 static const unsigned int scif1_data_c_mux[] = {
2674         RX1_C_MARK, TX1_C_MARK,
2675 };
2676 static const unsigned int scif1_data_d_pins[] = {
2677         /* RX, TX */
2678         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
2679 };
2680 static const unsigned int scif1_data_d_mux[] = {
2681         RX1_D_MARK, TX1_D_MARK,
2682 };
2683 /* - SCIF2 ------------------------------------------------------------------ */
2684 static const unsigned int scif2_data_pins[] = {
2685         /* RX, TX */
2686         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2687 };
2688 static const unsigned int scif2_data_mux[] = {
2689         RX2_MARK, TX2_MARK,
2690 };
2691 static const unsigned int scif2_data_b_pins[] = {
2692         /* RX, TX */
2693         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2694 };
2695 static const unsigned int scif2_data_b_mux[] = {
2696         RX2_B_MARK, TX2_B_MARK,
2697 };
2698 static const unsigned int scif2_clk_b_pins[] = {
2699         /* SCK */
2700         RCAR_GP_PIN(3, 18),
2701 };
2702 static const unsigned int scif2_clk_b_mux[] = {
2703         SCIF2_SCK_B_MARK,
2704 };
2705 static const unsigned int scif2_data_c_pins[] = {
2706         /* RX, TX */
2707         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2708 };
2709 static const unsigned int scif2_data_c_mux[] = {
2710         RX2_C_MARK, TX2_C_MARK,
2711 };
2712 static const unsigned int scif2_data_e_pins[] = {
2713         /* RX, TX */
2714         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2715 };
2716 static const unsigned int scif2_data_e_mux[] = {
2717         RX2_E_MARK, TX2_E_MARK,
2718 };
2719 /* - SCIF3 ------------------------------------------------------------------ */
2720 static const unsigned int scif3_data_pins[] = {
2721         /* RX, TX */
2722         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2723 };
2724 static const unsigned int scif3_data_mux[] = {
2725         RX3_MARK, TX3_MARK,
2726 };
2727 static const unsigned int scif3_clk_pins[] = {
2728         /* SCK */
2729         RCAR_GP_PIN(3, 23),
2730 };
2731 static const unsigned int scif3_clk_mux[] = {
2732         SCIF3_SCK_MARK,
2733 };
2734 static const unsigned int scif3_data_b_pins[] = {
2735         /* RX, TX */
2736         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
2737 };
2738 static const unsigned int scif3_data_b_mux[] = {
2739         RX3_B_MARK, TX3_B_MARK,
2740 };
2741 static const unsigned int scif3_clk_b_pins[] = {
2742         /* SCK */
2743         RCAR_GP_PIN(4, 8),
2744 };
2745 static const unsigned int scif3_clk_b_mux[] = {
2746         SCIF3_SCK_B_MARK,
2747 };
2748 static const unsigned int scif3_data_c_pins[] = {
2749         /* RX, TX */
2750         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2751 };
2752 static const unsigned int scif3_data_c_mux[] = {
2753         RX3_C_MARK, TX3_C_MARK,
2754 };
2755 static const unsigned int scif3_data_d_pins[] = {
2756         /* RX, TX */
2757         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
2758 };
2759 static const unsigned int scif3_data_d_mux[] = {
2760         RX3_D_MARK, TX3_D_MARK,
2761 };
2762 /* - SCIF4 ------------------------------------------------------------------ */
2763 static const unsigned int scif4_data_pins[] = {
2764         /* RX, TX */
2765         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2766 };
2767 static const unsigned int scif4_data_mux[] = {
2768         RX4_MARK, TX4_MARK,
2769 };
2770 static const unsigned int scif4_data_b_pins[] = {
2771         /* RX, TX */
2772         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2773 };
2774 static const unsigned int scif4_data_b_mux[] = {
2775         RX4_B_MARK, TX4_B_MARK,
2776 };
2777 static const unsigned int scif4_data_c_pins[] = {
2778         /* RX, TX */
2779         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2780 };
2781 static const unsigned int scif4_data_c_mux[] = {
2782         RX4_C_MARK, TX4_C_MARK,
2783 };
2784 /* - SCIF5 ------------------------------------------------------------------ */
2785 static const unsigned int scif5_data_pins[] = {
2786         /* RX, TX */
2787         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2788 };
2789 static const unsigned int scif5_data_mux[] = {
2790         RX5_MARK, TX5_MARK,
2791 };
2792 static const unsigned int scif5_data_b_pins[] = {
2793         /* RX, TX */
2794         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2795 };
2796 static const unsigned int scif5_data_b_mux[] = {
2797         RX5_B_MARK, TX5_B_MARK,
2798 };
2799 /* - SCIFA0 ----------------------------------------------------------------- */
2800 static const unsigned int scifa0_data_pins[] = {
2801         /* RXD, TXD */
2802         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2803 };
2804 static const unsigned int scifa0_data_mux[] = {
2805         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2806 };
2807 static const unsigned int scifa0_data_b_pins[] = {
2808         /* RXD, TXD */
2809         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2810 };
2811 static const unsigned int scifa0_data_b_mux[] = {
2812         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2813 };
2814 /* - SCIFA1 ----------------------------------------------------------------- */
2815 static const unsigned int scifa1_data_pins[] = {
2816         /* RXD, TXD */
2817         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2818 };
2819 static const unsigned int scifa1_data_mux[] = {
2820         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2821 };
2822 static const unsigned int scifa1_clk_pins[] = {
2823         /* SCK */
2824         RCAR_GP_PIN(3, 10),
2825 };
2826 static const unsigned int scifa1_clk_mux[] = {
2827         SCIFA1_SCK_MARK,
2828 };
2829 static const unsigned int scifa1_data_b_pins[] = {
2830         /* RXD, TXD */
2831         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2832 };
2833 static const unsigned int scifa1_data_b_mux[] = {
2834         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2835 };
2836 static const unsigned int scifa1_clk_b_pins[] = {
2837         /* SCK */
2838         RCAR_GP_PIN(1, 0),
2839 };
2840 static const unsigned int scifa1_clk_b_mux[] = {
2841         SCIFA1_SCK_B_MARK,
2842 };
2843 static const unsigned int scifa1_data_c_pins[] = {
2844         /* RXD, TXD */
2845         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2846 };
2847 static const unsigned int scifa1_data_c_mux[] = {
2848         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2849 };
2850 /* - SCIFA2 ----------------------------------------------------------------- */
2851 static const unsigned int scifa2_data_pins[] = {
2852         /* RXD, TXD */
2853         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2854 };
2855 static const unsigned int scifa2_data_mux[] = {
2856         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2857 };
2858 static const unsigned int scifa2_clk_pins[] = {
2859         /* SCK */
2860         RCAR_GP_PIN(3, 18),
2861 };
2862 static const unsigned int scifa2_clk_mux[] = {
2863         SCIFA2_SCK_MARK,
2864 };
2865 static const unsigned int scifa2_data_b_pins[] = {
2866         /* RXD, TXD */
2867         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2868 };
2869 static const unsigned int scifa2_data_b_mux[] = {
2870         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2871 };
2872 /* - SCIFA3 ----------------------------------------------------------------- */
2873 static const unsigned int scifa3_data_pins[] = {
2874         /* RXD, TXD */
2875         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2876 };
2877 static const unsigned int scifa3_data_mux[] = {
2878         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2879 };
2880 static const unsigned int scifa3_clk_pins[] = {
2881         /* SCK */
2882         RCAR_GP_PIN(3, 23),
2883 };
2884 static const unsigned int scifa3_clk_mux[] = {
2885         SCIFA3_SCK_MARK,
2886 };
2887 static const unsigned int scifa3_data_b_pins[] = {
2888         /* RXD, TXD */
2889         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
2890 };
2891 static const unsigned int scifa3_data_b_mux[] = {
2892         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2893 };
2894 static const unsigned int scifa3_clk_b_pins[] = {
2895         /* SCK */
2896         RCAR_GP_PIN(4, 8),
2897 };
2898 static const unsigned int scifa3_clk_b_mux[] = {
2899         SCIFA3_SCK_B_MARK,
2900 };
2901 static const unsigned int scifa3_data_c_pins[] = {
2902         /* RXD, TXD */
2903         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
2904 };
2905 static const unsigned int scifa3_data_c_mux[] = {
2906         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
2907 };
2908 static const unsigned int scifa3_clk_c_pins[] = {
2909         /* SCK */
2910         RCAR_GP_PIN(7, 22),
2911 };
2912 static const unsigned int scifa3_clk_c_mux[] = {
2913         SCIFA3_SCK_C_MARK,
2914 };
2915 /* - SCIFA4 ----------------------------------------------------------------- */
2916 static const unsigned int scifa4_data_pins[] = {
2917         /* RXD, TXD */
2918         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2919 };
2920 static const unsigned int scifa4_data_mux[] = {
2921         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2922 };
2923 static const unsigned int scifa4_data_b_pins[] = {
2924         /* RXD, TXD */
2925         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2926 };
2927 static const unsigned int scifa4_data_b_mux[] = {
2928         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2929 };
2930 static const unsigned int scifa4_data_c_pins[] = {
2931         /* RXD, TXD */
2932         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2933 };
2934 static const unsigned int scifa4_data_c_mux[] = {
2935         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2936 };
2937 /* - SCIFA5 ----------------------------------------------------------------- */
2938 static const unsigned int scifa5_data_pins[] = {
2939         /* RXD, TXD */
2940         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2941 };
2942 static const unsigned int scifa5_data_mux[] = {
2943         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2944 };
2945 static const unsigned int scifa5_data_b_pins[] = {
2946         /* RXD, TXD */
2947         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2948 };
2949 static const unsigned int scifa5_data_b_mux[] = {
2950         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2951 };
2952 static const unsigned int scifa5_data_c_pins[] = {
2953         /* RXD, TXD */
2954         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2955 };
2956 static const unsigned int scifa5_data_c_mux[] = {
2957         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2958 };
2959 /* - SCIFB0 ----------------------------------------------------------------- */
2960 static const unsigned int scifb0_data_pins[] = {
2961         /* RXD, TXD */
2962         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2963 };
2964 static const unsigned int scifb0_data_mux[] = {
2965         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2966 };
2967 static const unsigned int scifb0_clk_pins[] = {
2968         /* SCK */
2969         RCAR_GP_PIN(7, 2),
2970 };
2971 static const unsigned int scifb0_clk_mux[] = {
2972         SCIFB0_SCK_MARK,
2973 };
2974 static const unsigned int scifb0_ctrl_pins[] = {
2975         /* RTS, CTS */
2976         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2977 };
2978 static const unsigned int scifb0_ctrl_mux[] = {
2979         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2980 };
2981 static const unsigned int scifb0_data_b_pins[] = {
2982         /* RXD, TXD */
2983         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2984 };
2985 static const unsigned int scifb0_data_b_mux[] = {
2986         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2987 };
2988 static const unsigned int scifb0_clk_b_pins[] = {
2989         /* SCK */
2990         RCAR_GP_PIN(5, 31),
2991 };
2992 static const unsigned int scifb0_clk_b_mux[] = {
2993         SCIFB0_SCK_B_MARK,
2994 };
2995 static const unsigned int scifb0_ctrl_b_pins[] = {
2996         /* RTS, CTS */
2997         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
2998 };
2999 static const unsigned int scifb0_ctrl_b_mux[] = {
3000         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3001 };
3002 static const unsigned int scifb0_data_c_pins[] = {
3003         /* RXD, TXD */
3004         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3005 };
3006 static const unsigned int scifb0_data_c_mux[] = {
3007         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3008 };
3009 static const unsigned int scifb0_clk_c_pins[] = {
3010         /* SCK */
3011         RCAR_GP_PIN(2, 30),
3012 };
3013 static const unsigned int scifb0_clk_c_mux[] = {
3014         SCIFB0_SCK_C_MARK,
3015 };
3016 static const unsigned int scifb0_data_d_pins[] = {
3017         /* RXD, TXD */
3018         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3019 };
3020 static const unsigned int scifb0_data_d_mux[] = {
3021         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3022 };
3023 static const unsigned int scifb0_clk_d_pins[] = {
3024         /* SCK */
3025         RCAR_GP_PIN(4, 17),
3026 };
3027 static const unsigned int scifb0_clk_d_mux[] = {
3028         SCIFB0_SCK_D_MARK,
3029 };
3030 /* - SCIFB1 ----------------------------------------------------------------- */
3031 static const unsigned int scifb1_data_pins[] = {
3032         /* RXD, TXD */
3033         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3034 };
3035 static const unsigned int scifb1_data_mux[] = {
3036         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3037 };
3038 static const unsigned int scifb1_clk_pins[] = {
3039         /* SCK */
3040         RCAR_GP_PIN(7, 7),
3041 };
3042 static const unsigned int scifb1_clk_mux[] = {
3043         SCIFB1_SCK_MARK,
3044 };
3045 static const unsigned int scifb1_ctrl_pins[] = {
3046         /* RTS, CTS */
3047         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3048 };
3049 static const unsigned int scifb1_ctrl_mux[] = {
3050         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3051 };
3052 static const unsigned int scifb1_data_b_pins[] = {
3053         /* RXD, TXD */
3054         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3055 };
3056 static const unsigned int scifb1_data_b_mux[] = {
3057         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3058 };
3059 static const unsigned int scifb1_clk_b_pins[] = {
3060         /* SCK */
3061         RCAR_GP_PIN(1, 3),
3062 };
3063 static const unsigned int scifb1_clk_b_mux[] = {
3064         SCIFB1_SCK_B_MARK,
3065 };
3066 static const unsigned int scifb1_data_c_pins[] = {
3067         /* RXD, TXD */
3068         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3069 };
3070 static const unsigned int scifb1_data_c_mux[] = {
3071         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3072 };
3073 static const unsigned int scifb1_clk_c_pins[] = {
3074         /* SCK */
3075         RCAR_GP_PIN(7, 11),
3076 };
3077 static const unsigned int scifb1_clk_c_mux[] = {
3078         SCIFB1_SCK_C_MARK,
3079 };
3080 static const unsigned int scifb1_data_d_pins[] = {
3081         /* RXD, TXD */
3082         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3083 };
3084 static const unsigned int scifb1_data_d_mux[] = {
3085         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3086 };
3087 /* - SCIFB2 ----------------------------------------------------------------- */
3088 static const unsigned int scifb2_data_pins[] = {
3089         /* RXD, TXD */
3090         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3091 };
3092 static const unsigned int scifb2_data_mux[] = {
3093         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3094 };
3095 static const unsigned int scifb2_clk_pins[] = {
3096         /* SCK */
3097         RCAR_GP_PIN(4, 15),
3098 };
3099 static const unsigned int scifb2_clk_mux[] = {
3100         SCIFB2_SCK_MARK,
3101 };
3102 static const unsigned int scifb2_ctrl_pins[] = {
3103         /* RTS, CTS */
3104         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3105 };
3106 static const unsigned int scifb2_ctrl_mux[] = {
3107         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3108 };
3109 static const unsigned int scifb2_data_b_pins[] = {
3110         /* RXD, TXD */
3111         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3112 };
3113 static const unsigned int scifb2_data_b_mux[] = {
3114         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3115 };
3116 static const unsigned int scifb2_clk_b_pins[] = {
3117         /* SCK */
3118         RCAR_GP_PIN(5, 31),
3119 };
3120 static const unsigned int scifb2_clk_b_mux[] = {
3121         SCIFB2_SCK_B_MARK,
3122 };
3123 static const unsigned int scifb2_ctrl_b_pins[] = {
3124         /* RTS, CTS */
3125         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3126 };
3127 static const unsigned int scifb2_ctrl_b_mux[] = {
3128         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3129 };
3130 static const unsigned int scifb2_data_c_pins[] = {
3131         /* RXD, TXD */
3132         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3133 };
3134 static const unsigned int scifb2_data_c_mux[] = {
3135         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3136 };
3137 static const unsigned int scifb2_clk_c_pins[] = {
3138         /* SCK */
3139         RCAR_GP_PIN(5, 27),
3140 };
3141 static const unsigned int scifb2_clk_c_mux[] = {
3142         SCIFB2_SCK_C_MARK,
3143 };
3144 static const unsigned int scifb2_data_d_pins[] = {
3145         /* RXD, TXD */
3146         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3147 };
3148 static const unsigned int scifb2_data_d_mux[] = {
3149         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3150 };
3151 /* - SDHI0 ------------------------------------------------------------------ */
3152 static const unsigned int sdhi0_data1_pins[] = {
3153         /* D0 */
3154         RCAR_GP_PIN(6, 2),
3155 };
3156 static const unsigned int sdhi0_data1_mux[] = {
3157         SD0_DATA0_MARK,
3158 };
3159 static const unsigned int sdhi0_data4_pins[] = {
3160         /* D[0:3] */
3161         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3162         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3163 };
3164 static const unsigned int sdhi0_data4_mux[] = {
3165         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3166 };
3167 static const unsigned int sdhi0_ctrl_pins[] = {
3168         /* CLK, CMD */
3169         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3170 };
3171 static const unsigned int sdhi0_ctrl_mux[] = {
3172         SD0_CLK_MARK, SD0_CMD_MARK,
3173 };
3174 static const unsigned int sdhi0_cd_pins[] = {
3175         /* CD */
3176         RCAR_GP_PIN(6, 6),
3177 };
3178 static const unsigned int sdhi0_cd_mux[] = {
3179         SD0_CD_MARK,
3180 };
3181 static const unsigned int sdhi0_wp_pins[] = {
3182         /* WP */
3183         RCAR_GP_PIN(6, 7),
3184 };
3185 static const unsigned int sdhi0_wp_mux[] = {
3186         SD0_WP_MARK,
3187 };
3188 /* - SDHI1 ------------------------------------------------------------------ */
3189 static const unsigned int sdhi1_data1_pins[] = {
3190         /* D0 */
3191         RCAR_GP_PIN(6, 10),
3192 };
3193 static const unsigned int sdhi1_data1_mux[] = {
3194         SD1_DATA0_MARK,
3195 };
3196 static const unsigned int sdhi1_data4_pins[] = {
3197         /* D[0:3] */
3198         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3199         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3200 };
3201 static const unsigned int sdhi1_data4_mux[] = {
3202         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3203 };
3204 static const unsigned int sdhi1_ctrl_pins[] = {
3205         /* CLK, CMD */
3206         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3207 };
3208 static const unsigned int sdhi1_ctrl_mux[] = {
3209         SD1_CLK_MARK, SD1_CMD_MARK,
3210 };
3211 static const unsigned int sdhi1_cd_pins[] = {
3212         /* CD */
3213         RCAR_GP_PIN(6, 14),
3214 };
3215 static const unsigned int sdhi1_cd_mux[] = {
3216         SD1_CD_MARK,
3217 };
3218 static const unsigned int sdhi1_wp_pins[] = {
3219         /* WP */
3220         RCAR_GP_PIN(6, 15),
3221 };
3222 static const unsigned int sdhi1_wp_mux[] = {
3223         SD1_WP_MARK,
3224 };
3225 /* - SDHI2 ------------------------------------------------------------------ */
3226 static const unsigned int sdhi2_data1_pins[] = {
3227         /* D0 */
3228         RCAR_GP_PIN(6, 18),
3229 };
3230 static const unsigned int sdhi2_data1_mux[] = {
3231         SD2_DATA0_MARK,
3232 };
3233 static const unsigned int sdhi2_data4_pins[] = {
3234         /* D[0:3] */
3235         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3236         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3237 };
3238 static const unsigned int sdhi2_data4_mux[] = {
3239         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3240 };
3241 static const unsigned int sdhi2_ctrl_pins[] = {
3242         /* CLK, CMD */
3243         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3244 };
3245 static const unsigned int sdhi2_ctrl_mux[] = {
3246         SD2_CLK_MARK, SD2_CMD_MARK,
3247 };
3248 static const unsigned int sdhi2_cd_pins[] = {
3249         /* CD */
3250         RCAR_GP_PIN(6, 22),
3251 };
3252 static const unsigned int sdhi2_cd_mux[] = {
3253         SD2_CD_MARK,
3254 };
3255 static const unsigned int sdhi2_wp_pins[] = {
3256         /* WP */
3257         RCAR_GP_PIN(6, 23),
3258 };
3259 static const unsigned int sdhi2_wp_mux[] = {
3260         SD2_WP_MARK,
3261 };
3262 /* - USB0 ------------------------------------------------------------------- */
3263 static const unsigned int usb0_pins[] = {
3264         RCAR_GP_PIN(7, 23), /* PWEN */
3265         RCAR_GP_PIN(7, 24), /* OVC */
3266 };
3267 static const unsigned int usb0_mux[] = {
3268         USB0_PWEN_MARK,
3269         USB0_OVC_MARK,
3270 };
3271 /* - USB1 ------------------------------------------------------------------- */
3272 static const unsigned int usb1_pins[] = {
3273         RCAR_GP_PIN(7, 25), /* PWEN */
3274         RCAR_GP_PIN(6, 30), /* OVC */
3275 };
3276 static const unsigned int usb1_mux[] = {
3277         USB1_PWEN_MARK,
3278         USB1_OVC_MARK,
3279 };
3280
3281 union vin_data {
3282         unsigned int data24[24];
3283         unsigned int data20[20];
3284         unsigned int data16[16];
3285         unsigned int data12[12];
3286         unsigned int data10[10];
3287         unsigned int data8[8];
3288 };
3289
3290 #define VIN_DATA_PIN_GROUP(n, s)                                \
3291         {                                                       \
3292                 .name = #n#s,                                   \
3293                 .pins = n##_pins.data##s,                       \
3294                 .mux = n##_mux.data##s,                         \
3295                 .nr_pins = ARRAY_SIZE(n##_pins.data##s),        \
3296         }
3297
3298 /* - VIN0 ------------------------------------------------------------------- */
3299 static const union vin_data vin0_data_pins = {
3300         .data24 = {
3301                 /* B */
3302                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
3303                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3304                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3305                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3306                 /* G */
3307                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3308                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3309                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3310                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
3311                 /* R */
3312                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
3313                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
3314                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3315                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3316         },
3317 };
3318 static const union vin_data vin0_data_mux = {
3319         .data24 = {
3320                 /* B */
3321                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3322                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3323                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3324                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3325                 /* G */
3326                 VI0_G0_MARK, VI0_G1_MARK,
3327                 VI0_G2_MARK, VI0_G3_MARK,
3328                 VI0_G4_MARK, VI0_G5_MARK,
3329                 VI0_G6_MARK, VI0_G7_MARK,
3330                 /* R */
3331                 VI0_R0_MARK, VI0_R1_MARK,
3332                 VI0_R2_MARK, VI0_R3_MARK,
3333                 VI0_R4_MARK, VI0_R5_MARK,
3334                 VI0_R6_MARK, VI0_R7_MARK,
3335         },
3336 };
3337 static const unsigned int vin0_data18_pins[] = {
3338         /* B */
3339         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3340         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3341         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3342         /* G */
3343         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3344         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3345         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
3346         /* R */
3347         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
3348         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3349         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3350 };
3351 static const unsigned int vin0_data18_mux[] = {
3352         /* B */
3353         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3354         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3355         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3356         /* G */
3357         VI0_G2_MARK, VI0_G3_MARK,
3358         VI0_G4_MARK, VI0_G5_MARK,
3359         VI0_G6_MARK, VI0_G7_MARK,
3360         /* R */
3361         VI0_R2_MARK, VI0_R3_MARK,
3362         VI0_R4_MARK, VI0_R5_MARK,
3363         VI0_R6_MARK, VI0_R7_MARK,
3364 };
3365 static const unsigned int vin0_sync_pins[] = {
3366         RCAR_GP_PIN(4, 3), /* HSYNC */
3367         RCAR_GP_PIN(4, 4), /* VSYNC */
3368 };
3369 static const unsigned int vin0_sync_mux[] = {
3370         VI0_HSYNC_N_MARK,
3371         VI0_VSYNC_N_MARK,
3372 };
3373 static const unsigned int vin0_field_pins[] = {
3374         RCAR_GP_PIN(4, 2),
3375 };
3376 static const unsigned int vin0_field_mux[] = {
3377         VI0_FIELD_MARK,
3378 };
3379 static const unsigned int vin0_clkenb_pins[] = {
3380         RCAR_GP_PIN(4, 1),
3381 };
3382 static const unsigned int vin0_clkenb_mux[] = {
3383         VI0_CLKENB_MARK,
3384 };
3385 static const unsigned int vin0_clk_pins[] = {
3386         RCAR_GP_PIN(4, 0),
3387 };
3388 static const unsigned int vin0_clk_mux[] = {
3389         VI0_CLK_MARK,
3390 };
3391 /* - VIN1 ----------------------------------------------------------------- */
3392 static const unsigned int vin1_data8_pins[] = {
3393         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3394         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3395         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
3396         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3397 };
3398 static const unsigned int vin1_data8_mux[] = {
3399         VI1_DATA0_MARK, VI1_DATA1_MARK,
3400         VI1_DATA2_MARK, VI1_DATA3_MARK,
3401         VI1_DATA4_MARK, VI1_DATA5_MARK,
3402         VI1_DATA6_MARK, VI1_DATA7_MARK,
3403 };
3404 static const unsigned int vin1_sync_pins[] = {
3405         RCAR_GP_PIN(5, 0), /* HSYNC */
3406         RCAR_GP_PIN(5, 1), /* VSYNC */
3407 };
3408 static const unsigned int vin1_sync_mux[] = {
3409         VI1_HSYNC_N_MARK,
3410         VI1_VSYNC_N_MARK,
3411 };
3412 static const unsigned int vin1_field_pins[] = {
3413         RCAR_GP_PIN(5, 3),
3414 };
3415 static const unsigned int vin1_field_mux[] = {
3416         VI1_FIELD_MARK,
3417 };
3418 static const unsigned int vin1_clkenb_pins[] = {
3419         RCAR_GP_PIN(5, 2),
3420 };
3421 static const unsigned int vin1_clkenb_mux[] = {
3422         VI1_CLKENB_MARK,
3423 };
3424 static const unsigned int vin1_clk_pins[] = {
3425         RCAR_GP_PIN(5, 4),
3426 };
3427 static const unsigned int vin1_clk_mux[] = {
3428         VI1_CLK_MARK,
3429 };
3430 static const union vin_data vin1_b_data_pins = {
3431         .data24 = {
3432                 /* B */
3433                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3434                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3435                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3436                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3437                 /* G */
3438                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3439                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3440                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3441                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3442                 /* R */
3443                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3444                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3445                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3446                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3447         },
3448 };
3449 static const union vin_data vin1_b_data_mux = {
3450         .data24 = {
3451                 /* B */
3452                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3453                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3454                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3455                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3456                 /* G */
3457                 VI1_G0_B_MARK, VI1_G1_B_MARK,
3458                 VI1_G2_B_MARK, VI1_G3_B_MARK,
3459                 VI1_G4_B_MARK, VI1_G5_B_MARK,
3460                 VI1_G6_B_MARK, VI1_G7_B_MARK,
3461                 /* R */
3462                 VI1_R0_B_MARK, VI1_R1_B_MARK,
3463                 VI1_R2_B_MARK, VI1_R3_B_MARK,
3464                 VI1_R4_B_MARK, VI1_R5_B_MARK,
3465                 VI1_R6_B_MARK, VI1_R7_B_MARK,
3466         },
3467 };
3468 static const unsigned int vin1_b_data18_pins[] = {
3469         /* B */
3470         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3471         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3472         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3473         /* G */
3474         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3475         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3476         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3477         /* R */
3478         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3479         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3480         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3481 };
3482 static const unsigned int vin1_b_data18_mux[] = {
3483         /* B */
3484         VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3485         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3486         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3487         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3488         /* G */
3489         VI1_G0_B_MARK, VI1_G1_B_MARK,
3490         VI1_G2_B_MARK, VI1_G3_B_MARK,
3491         VI1_G4_B_MARK, VI1_G5_B_MARK,
3492         VI1_G6_B_MARK, VI1_G7_B_MARK,
3493         /* R */
3494         VI1_R0_B_MARK, VI1_R1_B_MARK,
3495         VI1_R2_B_MARK, VI1_R3_B_MARK,
3496         VI1_R4_B_MARK, VI1_R5_B_MARK,
3497         VI1_R6_B_MARK, VI1_R7_B_MARK,
3498 };
3499 static const unsigned int vin1_b_sync_pins[] = {
3500         RCAR_GP_PIN(3, 17), /* HSYNC */
3501         RCAR_GP_PIN(3, 18), /* VSYNC */
3502 };
3503 static const unsigned int vin1_b_sync_mux[] = {
3504         VI1_HSYNC_N_B_MARK,
3505         VI1_VSYNC_N_B_MARK,
3506 };
3507 static const unsigned int vin1_b_field_pins[] = {
3508         RCAR_GP_PIN(3, 20),
3509 };
3510 static const unsigned int vin1_b_field_mux[] = {
3511         VI1_FIELD_B_MARK,
3512 };
3513 static const unsigned int vin1_b_clkenb_pins[] = {
3514         RCAR_GP_PIN(3, 19),
3515 };
3516 static const unsigned int vin1_b_clkenb_mux[] = {
3517         VI1_CLKENB_B_MARK,
3518 };
3519 static const unsigned int vin1_b_clk_pins[] = {
3520         RCAR_GP_PIN(3, 16),
3521 };
3522 static const unsigned int vin1_b_clk_mux[] = {
3523         VI1_CLK_B_MARK,
3524 };
3525 /* - VIN2 ----------------------------------------------------------------- */
3526 static const unsigned int vin2_data8_pins[] = {
3527         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3528         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3529         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3530         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
3531 };
3532 static const unsigned int vin2_data8_mux[] = {
3533         VI2_DATA0_MARK, VI2_DATA1_MARK,
3534         VI2_DATA2_MARK, VI2_DATA3_MARK,
3535         VI2_DATA4_MARK, VI2_DATA5_MARK,
3536         VI2_DATA6_MARK, VI2_DATA7_MARK,
3537 };
3538 static const unsigned int vin2_sync_pins[] = {
3539         RCAR_GP_PIN(4, 15), /* HSYNC */
3540         RCAR_GP_PIN(4, 16), /* VSYNC */
3541 };
3542 static const unsigned int vin2_sync_mux[] = {
3543         VI2_HSYNC_N_MARK,
3544         VI2_VSYNC_N_MARK,
3545 };
3546 static const unsigned int vin2_field_pins[] = {
3547         RCAR_GP_PIN(4, 18),
3548 };
3549 static const unsigned int vin2_field_mux[] = {
3550         VI2_FIELD_MARK,
3551 };
3552 static const unsigned int vin2_clkenb_pins[] = {
3553         RCAR_GP_PIN(4, 17),
3554 };
3555 static const unsigned int vin2_clkenb_mux[] = {
3556         VI2_CLKENB_MARK,
3557 };
3558 static const unsigned int vin2_clk_pins[] = {
3559         RCAR_GP_PIN(4, 19),
3560 };
3561 static const unsigned int vin2_clk_mux[] = {
3562         VI2_CLK_MARK,
3563 };
3564
3565 static const struct sh_pfc_pin_group pinmux_groups[] = {
3566         SH_PFC_PIN_GROUP(du_rgb666),
3567         SH_PFC_PIN_GROUP(du_rgb888),
3568         SH_PFC_PIN_GROUP(du_clk_out_0),
3569         SH_PFC_PIN_GROUP(du_clk_out_1),
3570         SH_PFC_PIN_GROUP(du_sync),
3571         SH_PFC_PIN_GROUP(du_oddf),
3572         SH_PFC_PIN_GROUP(du_cde),
3573         SH_PFC_PIN_GROUP(du_disp),
3574         SH_PFC_PIN_GROUP(du0_clk_in),
3575         SH_PFC_PIN_GROUP(du1_clk_in),
3576         SH_PFC_PIN_GROUP(du1_clk_in_b),
3577         SH_PFC_PIN_GROUP(du1_clk_in_c),
3578         SH_PFC_PIN_GROUP(eth_link),
3579         SH_PFC_PIN_GROUP(eth_magic),
3580         SH_PFC_PIN_GROUP(eth_mdio),
3581         SH_PFC_PIN_GROUP(eth_rmii),
3582         SH_PFC_PIN_GROUP(i2c0),
3583         SH_PFC_PIN_GROUP(i2c0_b),
3584         SH_PFC_PIN_GROUP(i2c0_c),
3585         SH_PFC_PIN_GROUP(i2c1),
3586         SH_PFC_PIN_GROUP(i2c1_b),
3587         SH_PFC_PIN_GROUP(i2c1_c),
3588         SH_PFC_PIN_GROUP(i2c1_d),
3589         SH_PFC_PIN_GROUP(i2c1_e),
3590         SH_PFC_PIN_GROUP(i2c2),
3591         SH_PFC_PIN_GROUP(i2c2_b),
3592         SH_PFC_PIN_GROUP(i2c2_c),
3593         SH_PFC_PIN_GROUP(i2c2_d),
3594         SH_PFC_PIN_GROUP(i2c3),
3595         SH_PFC_PIN_GROUP(i2c3_b),
3596         SH_PFC_PIN_GROUP(i2c3_c),
3597         SH_PFC_PIN_GROUP(i2c3_d),
3598         SH_PFC_PIN_GROUP(i2c4),
3599         SH_PFC_PIN_GROUP(i2c4_b),
3600         SH_PFC_PIN_GROUP(i2c4_c),
3601         SH_PFC_PIN_GROUP(i2c7),
3602         SH_PFC_PIN_GROUP(i2c7_b),
3603         SH_PFC_PIN_GROUP(i2c7_c),
3604         SH_PFC_PIN_GROUP(i2c8),
3605         SH_PFC_PIN_GROUP(i2c8_b),
3606         SH_PFC_PIN_GROUP(i2c8_c),
3607         SH_PFC_PIN_GROUP(intc_irq0),
3608         SH_PFC_PIN_GROUP(intc_irq1),
3609         SH_PFC_PIN_GROUP(intc_irq2),
3610         SH_PFC_PIN_GROUP(intc_irq3),
3611         SH_PFC_PIN_GROUP(mmc_data1),
3612         SH_PFC_PIN_GROUP(mmc_data4),
3613         SH_PFC_PIN_GROUP(mmc_data8),
3614         SH_PFC_PIN_GROUP(mmc_ctrl),
3615         SH_PFC_PIN_GROUP(msiof0_clk),
3616         SH_PFC_PIN_GROUP(msiof0_sync),
3617         SH_PFC_PIN_GROUP(msiof0_ss1),
3618         SH_PFC_PIN_GROUP(msiof0_ss2),
3619         SH_PFC_PIN_GROUP(msiof0_rx),
3620         SH_PFC_PIN_GROUP(msiof0_tx),
3621         SH_PFC_PIN_GROUP(msiof0_clk_b),
3622         SH_PFC_PIN_GROUP(msiof0_sync_b),
3623         SH_PFC_PIN_GROUP(msiof0_ss1_b),
3624         SH_PFC_PIN_GROUP(msiof0_ss2_b),
3625         SH_PFC_PIN_GROUP(msiof0_rx_b),
3626         SH_PFC_PIN_GROUP(msiof0_tx_b),
3627         SH_PFC_PIN_GROUP(msiof0_clk_c),
3628         SH_PFC_PIN_GROUP(msiof0_sync_c),
3629         SH_PFC_PIN_GROUP(msiof0_ss1_c),
3630         SH_PFC_PIN_GROUP(msiof0_ss2_c),
3631         SH_PFC_PIN_GROUP(msiof0_rx_c),
3632         SH_PFC_PIN_GROUP(msiof0_tx_c),
3633         SH_PFC_PIN_GROUP(msiof1_clk),
3634         SH_PFC_PIN_GROUP(msiof1_sync),
3635         SH_PFC_PIN_GROUP(msiof1_ss1),
3636         SH_PFC_PIN_GROUP(msiof1_ss2),
3637         SH_PFC_PIN_GROUP(msiof1_rx),
3638         SH_PFC_PIN_GROUP(msiof1_tx),
3639         SH_PFC_PIN_GROUP(msiof1_clk_b),
3640         SH_PFC_PIN_GROUP(msiof1_sync_b),
3641         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3642         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3643         SH_PFC_PIN_GROUP(msiof1_rx_b),
3644         SH_PFC_PIN_GROUP(msiof1_tx_b),
3645         SH_PFC_PIN_GROUP(msiof1_clk_c),
3646         SH_PFC_PIN_GROUP(msiof1_sync_c),
3647         SH_PFC_PIN_GROUP(msiof1_rx_c),
3648         SH_PFC_PIN_GROUP(msiof1_tx_c),
3649         SH_PFC_PIN_GROUP(msiof1_clk_d),
3650         SH_PFC_PIN_GROUP(msiof1_sync_d),
3651         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3652         SH_PFC_PIN_GROUP(msiof1_rx_d),
3653         SH_PFC_PIN_GROUP(msiof1_tx_d),
3654         SH_PFC_PIN_GROUP(msiof1_clk_e),
3655         SH_PFC_PIN_GROUP(msiof1_sync_e),
3656         SH_PFC_PIN_GROUP(msiof1_rx_e),
3657         SH_PFC_PIN_GROUP(msiof1_tx_e),
3658         SH_PFC_PIN_GROUP(msiof2_clk),
3659         SH_PFC_PIN_GROUP(msiof2_sync),
3660         SH_PFC_PIN_GROUP(msiof2_ss1),
3661         SH_PFC_PIN_GROUP(msiof2_ss2),
3662         SH_PFC_PIN_GROUP(msiof2_rx),
3663         SH_PFC_PIN_GROUP(msiof2_tx),
3664         SH_PFC_PIN_GROUP(msiof2_clk_b),
3665         SH_PFC_PIN_GROUP(msiof2_sync_b),
3666         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3667         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3668         SH_PFC_PIN_GROUP(msiof2_rx_b),
3669         SH_PFC_PIN_GROUP(msiof2_tx_b),
3670         SH_PFC_PIN_GROUP(msiof2_clk_c),
3671         SH_PFC_PIN_GROUP(msiof2_sync_c),
3672         SH_PFC_PIN_GROUP(msiof2_rx_c),
3673         SH_PFC_PIN_GROUP(msiof2_tx_c),
3674         SH_PFC_PIN_GROUP(msiof2_clk_d),
3675         SH_PFC_PIN_GROUP(msiof2_sync_d),
3676         SH_PFC_PIN_GROUP(msiof2_ss1_d),
3677         SH_PFC_PIN_GROUP(msiof2_ss2_d),
3678         SH_PFC_PIN_GROUP(msiof2_rx_d),
3679         SH_PFC_PIN_GROUP(msiof2_tx_d),
3680         SH_PFC_PIN_GROUP(msiof2_clk_e),
3681         SH_PFC_PIN_GROUP(msiof2_sync_e),
3682         SH_PFC_PIN_GROUP(msiof2_rx_e),
3683         SH_PFC_PIN_GROUP(msiof2_tx_e),
3684         SH_PFC_PIN_GROUP(qspi_ctrl),
3685         SH_PFC_PIN_GROUP(qspi_data2),
3686         SH_PFC_PIN_GROUP(qspi_data4),
3687         SH_PFC_PIN_GROUP(qspi_ctrl_b),
3688         SH_PFC_PIN_GROUP(qspi_data2_b),
3689         SH_PFC_PIN_GROUP(qspi_data4_b),
3690         SH_PFC_PIN_GROUP(scif0_data),
3691         SH_PFC_PIN_GROUP(scif0_data_b),
3692         SH_PFC_PIN_GROUP(scif0_data_c),
3693         SH_PFC_PIN_GROUP(scif0_data_d),
3694         SH_PFC_PIN_GROUP(scif0_data_e),
3695         SH_PFC_PIN_GROUP(scif1_data),
3696         SH_PFC_PIN_GROUP(scif1_data_b),
3697         SH_PFC_PIN_GROUP(scif1_clk_b),
3698         SH_PFC_PIN_GROUP(scif1_data_c),
3699         SH_PFC_PIN_GROUP(scif1_data_d),
3700         SH_PFC_PIN_GROUP(scif2_data),
3701         SH_PFC_PIN_GROUP(scif2_data_b),
3702         SH_PFC_PIN_GROUP(scif2_clk_b),
3703         SH_PFC_PIN_GROUP(scif2_data_c),
3704         SH_PFC_PIN_GROUP(scif2_data_e),
3705         SH_PFC_PIN_GROUP(scif3_data),
3706         SH_PFC_PIN_GROUP(scif3_clk),
3707         SH_PFC_PIN_GROUP(scif3_data_b),
3708         SH_PFC_PIN_GROUP(scif3_clk_b),
3709         SH_PFC_PIN_GROUP(scif3_data_c),
3710         SH_PFC_PIN_GROUP(scif3_data_d),
3711         SH_PFC_PIN_GROUP(scif4_data),
3712         SH_PFC_PIN_GROUP(scif4_data_b),
3713         SH_PFC_PIN_GROUP(scif4_data_c),
3714         SH_PFC_PIN_GROUP(scif5_data),
3715         SH_PFC_PIN_GROUP(scif5_data_b),
3716         SH_PFC_PIN_GROUP(scifa0_data),
3717         SH_PFC_PIN_GROUP(scifa0_data_b),
3718         SH_PFC_PIN_GROUP(scifa1_data),
3719         SH_PFC_PIN_GROUP(scifa1_clk),
3720         SH_PFC_PIN_GROUP(scifa1_data_b),
3721         SH_PFC_PIN_GROUP(scifa1_clk_b),
3722         SH_PFC_PIN_GROUP(scifa1_data_c),
3723         SH_PFC_PIN_GROUP(scifa2_data),
3724         SH_PFC_PIN_GROUP(scifa2_clk),
3725         SH_PFC_PIN_GROUP(scifa2_data_b),
3726         SH_PFC_PIN_GROUP(scifa3_data),
3727         SH_PFC_PIN_GROUP(scifa3_clk),
3728         SH_PFC_PIN_GROUP(scifa3_data_b),
3729         SH_PFC_PIN_GROUP(scifa3_clk_b),
3730         SH_PFC_PIN_GROUP(scifa3_data_c),
3731         SH_PFC_PIN_GROUP(scifa3_clk_c),
3732         SH_PFC_PIN_GROUP(scifa4_data),
3733         SH_PFC_PIN_GROUP(scifa4_data_b),
3734         SH_PFC_PIN_GROUP(scifa4_data_c),
3735         SH_PFC_PIN_GROUP(scifa5_data),
3736         SH_PFC_PIN_GROUP(scifa5_data_b),
3737         SH_PFC_PIN_GROUP(scifa5_data_c),
3738         SH_PFC_PIN_GROUP(scifb0_data),
3739         SH_PFC_PIN_GROUP(scifb0_clk),
3740         SH_PFC_PIN_GROUP(scifb0_ctrl),
3741         SH_PFC_PIN_GROUP(scifb0_data_b),
3742         SH_PFC_PIN_GROUP(scifb0_clk_b),
3743         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3744         SH_PFC_PIN_GROUP(scifb0_data_c),
3745         SH_PFC_PIN_GROUP(scifb0_clk_c),
3746         SH_PFC_PIN_GROUP(scifb0_data_d),
3747         SH_PFC_PIN_GROUP(scifb0_clk_d),
3748         SH_PFC_PIN_GROUP(scifb1_data),
3749         SH_PFC_PIN_GROUP(scifb1_clk),
3750         SH_PFC_PIN_GROUP(scifb1_ctrl),
3751         SH_PFC_PIN_GROUP(scifb1_data_b),
3752         SH_PFC_PIN_GROUP(scifb1_clk_b),
3753         SH_PFC_PIN_GROUP(scifb1_data_c),
3754         SH_PFC_PIN_GROUP(scifb1_clk_c),
3755         SH_PFC_PIN_GROUP(scifb1_data_d),
3756         SH_PFC_PIN_GROUP(scifb2_data),
3757         SH_PFC_PIN_GROUP(scifb2_clk),
3758         SH_PFC_PIN_GROUP(scifb2_ctrl),
3759         SH_PFC_PIN_GROUP(scifb2_data_b),
3760         SH_PFC_PIN_GROUP(scifb2_clk_b),
3761         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3762         SH_PFC_PIN_GROUP(scifb2_data_c),
3763         SH_PFC_PIN_GROUP(scifb2_clk_c),
3764         SH_PFC_PIN_GROUP(scifb2_data_d),
3765         SH_PFC_PIN_GROUP(sdhi0_data1),
3766         SH_PFC_PIN_GROUP(sdhi0_data4),
3767         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3768         SH_PFC_PIN_GROUP(sdhi0_cd),
3769         SH_PFC_PIN_GROUP(sdhi0_wp),
3770         SH_PFC_PIN_GROUP(sdhi1_data1),
3771         SH_PFC_PIN_GROUP(sdhi1_data4),
3772         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3773         SH_PFC_PIN_GROUP(sdhi1_cd),
3774         SH_PFC_PIN_GROUP(sdhi1_wp),
3775         SH_PFC_PIN_GROUP(sdhi2_data1),
3776         SH_PFC_PIN_GROUP(sdhi2_data4),
3777         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3778         SH_PFC_PIN_GROUP(sdhi2_cd),
3779         SH_PFC_PIN_GROUP(sdhi2_wp),
3780         SH_PFC_PIN_GROUP(usb0),
3781         SH_PFC_PIN_GROUP(usb1),
3782         VIN_DATA_PIN_GROUP(vin0_data, 24),
3783         VIN_DATA_PIN_GROUP(vin0_data, 20),
3784         SH_PFC_PIN_GROUP(vin0_data18),
3785         VIN_DATA_PIN_GROUP(vin0_data, 16),
3786         VIN_DATA_PIN_GROUP(vin0_data, 12),
3787         VIN_DATA_PIN_GROUP(vin0_data, 10),
3788         VIN_DATA_PIN_GROUP(vin0_data, 8),
3789         SH_PFC_PIN_GROUP(vin0_sync),
3790         SH_PFC_PIN_GROUP(vin0_field),
3791         SH_PFC_PIN_GROUP(vin0_clkenb),
3792         SH_PFC_PIN_GROUP(vin0_clk),
3793         SH_PFC_PIN_GROUP(vin1_data8),
3794         SH_PFC_PIN_GROUP(vin1_sync),
3795         SH_PFC_PIN_GROUP(vin1_field),
3796         SH_PFC_PIN_GROUP(vin1_clkenb),
3797         SH_PFC_PIN_GROUP(vin1_clk),
3798         VIN_DATA_PIN_GROUP(vin1_b_data, 24),
3799         VIN_DATA_PIN_GROUP(vin1_b_data, 20),
3800         SH_PFC_PIN_GROUP(vin1_b_data18),
3801         VIN_DATA_PIN_GROUP(vin1_b_data, 16),
3802         VIN_DATA_PIN_GROUP(vin1_b_data, 12),
3803         VIN_DATA_PIN_GROUP(vin1_b_data, 10),
3804         VIN_DATA_PIN_GROUP(vin1_b_data, 8),
3805         SH_PFC_PIN_GROUP(vin1_b_sync),
3806         SH_PFC_PIN_GROUP(vin1_b_field),
3807         SH_PFC_PIN_GROUP(vin1_b_clkenb),
3808         SH_PFC_PIN_GROUP(vin1_b_clk),
3809         SH_PFC_PIN_GROUP(vin2_data8),
3810         SH_PFC_PIN_GROUP(vin2_sync),
3811         SH_PFC_PIN_GROUP(vin2_field),
3812         SH_PFC_PIN_GROUP(vin2_clkenb),
3813         SH_PFC_PIN_GROUP(vin2_clk),
3814 };
3815
3816 static const char * const du_groups[] = {
3817         "du_rgb666",
3818         "du_rgb888",
3819         "du_clk_out_0",
3820         "du_clk_out_1",
3821         "du_sync",
3822         "du_oddf",
3823         "du_cde",
3824         "du_disp",
3825 };
3826
3827 static const char * const du0_groups[] = {
3828         "du0_clk_in",
3829 };
3830
3831 static const char * const du1_groups[] = {
3832         "du1_clk_in",
3833         "du1_clk_in_b",
3834         "du1_clk_in_c",
3835 };
3836
3837 static const char * const eth_groups[] = {
3838         "eth_link",
3839         "eth_magic",
3840         "eth_mdio",
3841         "eth_rmii",
3842 };
3843
3844 static const char * const i2c0_groups[] = {
3845         "i2c0",
3846         "i2c0_b",
3847         "i2c0_c",
3848 };
3849
3850 static const char * const i2c1_groups[] = {
3851         "i2c1",
3852         "i2c1_b",
3853         "i2c1_c",
3854         "i2c1_d",
3855         "i2c1_e",
3856 };
3857
3858 static const char * const i2c2_groups[] = {
3859         "i2c2",
3860         "i2c2_b",
3861         "i2c2_c",
3862         "i2c2_d",
3863 };
3864
3865 static const char * const i2c3_groups[] = {
3866         "i2c3",
3867         "i2c3_b",
3868         "i2c3_c",
3869         "i2c3_d",
3870 };
3871
3872 static const char * const i2c4_groups[] = {
3873         "i2c4",
3874         "i2c4_b",
3875         "i2c4_c",
3876 };
3877
3878 static const char * const i2c7_groups[] = {
3879         "i2c7",
3880         "i2c7_b",
3881         "i2c7_c",
3882 };
3883
3884 static const char * const i2c8_groups[] = {
3885         "i2c8",
3886         "i2c8_b",
3887         "i2c8_c",
3888 };
3889
3890 static const char * const intc_groups[] = {
3891         "intc_irq0",
3892         "intc_irq1",
3893         "intc_irq2",
3894         "intc_irq3",
3895 };
3896
3897 static const char * const mmc_groups[] = {
3898         "mmc_data1",
3899         "mmc_data4",
3900         "mmc_data8",
3901         "mmc_ctrl",
3902 };
3903
3904 static const char * const msiof0_groups[] = {
3905         "msiof0_clk",
3906         "msiof0_sync",
3907         "msiof0_ss1",
3908         "msiof0_ss2",
3909         "msiof0_rx",
3910         "msiof0_tx",
3911         "msiof0_clk_b",
3912         "msiof0_sync_b",
3913         "msiof0_ss1_b",
3914         "msiof0_ss2_b",
3915         "msiof0_rx_b",
3916         "msiof0_tx_b",
3917         "msiof0_clk_c",
3918         "msiof0_sync_c",
3919         "msiof0_ss1_c",
3920         "msiof0_ss2_c",
3921         "msiof0_rx_c",
3922         "msiof0_tx_c",
3923 };
3924
3925 static const char * const msiof1_groups[] = {
3926         "msiof1_clk",
3927         "msiof1_sync",
3928         "msiof1_ss1",
3929         "msiof1_ss2",
3930         "msiof1_rx",
3931         "msiof1_tx",
3932         "msiof1_clk_b",
3933         "msiof1_sync_b",
3934         "msiof1_ss1_b",
3935         "msiof1_ss2_b",
3936         "msiof1_rx_b",
3937         "msiof1_tx_b",
3938         "msiof1_clk_c",
3939         "msiof1_sync_c",
3940         "msiof1_rx_c",
3941         "msiof1_tx_c",
3942         "msiof1_clk_d",
3943         "msiof1_sync_d",
3944         "msiof1_ss1_d",
3945         "msiof1_rx_d",
3946         "msiof1_tx_d",
3947         "msiof1_clk_e",
3948         "msiof1_sync_e",
3949         "msiof1_rx_e",
3950         "msiof1_tx_e",
3951 };
3952
3953 static const char * const msiof2_groups[] = {
3954         "msiof2_clk",
3955         "msiof2_sync",
3956         "msiof2_ss1",
3957         "msiof2_ss2",
3958         "msiof2_rx",
3959         "msiof2_tx",
3960         "msiof2_clk_b",
3961         "msiof2_sync_b",
3962         "msiof2_ss1_b",
3963         "msiof2_ss2_b",
3964         "msiof2_rx_b",
3965         "msiof2_tx_b",
3966         "msiof2_clk_c",
3967         "msiof2_sync_c",
3968         "msiof2_rx_c",
3969         "msiof2_tx_c",
3970         "msiof2_clk_d",
3971         "msiof2_sync_d",
3972         "msiof2_ss1_d",
3973         "msiof2_ss2_d",
3974         "msiof2_rx_d",
3975         "msiof2_tx_d",
3976         "msiof2_clk_e",
3977         "msiof2_sync_e",
3978         "msiof2_rx_e",
3979         "msiof2_tx_e",
3980 };
3981
3982 static const char * const qspi_groups[] = {
3983         "qspi_ctrl",
3984         "qspi_data2",
3985         "qspi_data4",
3986         "qspi_ctrl_b",
3987         "qspi_data2_b",
3988         "qspi_data4_b",
3989 };
3990
3991 static const char * const scif0_groups[] = {
3992         "scif0_data",
3993         "scif0_data_b",
3994         "scif0_data_c",
3995         "scif0_data_d",
3996         "scif0_data_e",
3997 };
3998
3999 static const char * const scif1_groups[] = {
4000         "scif1_data",
4001         "scif1_data_b",
4002         "scif1_clk_b",
4003         "scif1_data_c",
4004         "scif1_data_d",
4005 };
4006
4007 static const char * const scif2_groups[] = {
4008         "scif2_data",
4009         "scif2_data_b",
4010         "scif2_clk_b",
4011         "scif2_data_c",
4012         "scif2_data_e",
4013 };
4014 static const char * const scif3_groups[] = {
4015         "scif3_data",
4016         "scif3_clk",
4017         "scif3_data_b",
4018         "scif3_clk_b",
4019         "scif3_data_c",
4020         "scif3_data_d",
4021 };
4022 static const char * const scif4_groups[] = {
4023         "scif4_data",
4024         "scif4_data_b",
4025         "scif4_data_c",
4026 };
4027 static const char * const scif5_groups[] = {
4028         "scif5_data",
4029         "scif5_data_b",
4030 };
4031 static const char * const scifa0_groups[] = {
4032         "scifa0_data",
4033         "scifa0_data_b",
4034 };
4035 static const char * const scifa1_groups[] = {
4036         "scifa1_data",
4037         "scifa1_clk",
4038         "scifa1_data_b",
4039         "scifa1_clk_b",
4040         "scifa1_data_c",
4041 };
4042 static const char * const scifa2_groups[] = {
4043         "scifa2_data",
4044         "scifa2_clk",
4045         "scifa2_data_b",
4046 };
4047 static const char * const scifa3_groups[] = {
4048         "scifa3_data",
4049         "scifa3_clk",
4050         "scifa3_data_b",
4051         "scifa3_clk_b",
4052         "scifa3_data_c",
4053         "scifa3_clk_c",
4054 };
4055 static const char * const scifa4_groups[] = {
4056         "scifa4_data",
4057         "scifa4_data_b",
4058         "scifa4_data_c",
4059 };
4060 static const char * const scifa5_groups[] = {
4061         "scifa5_data",
4062         "scifa5_data_b",
4063         "scifa5_data_c",
4064 };
4065 static const char * const scifb0_groups[] = {
4066         "scifb0_data",
4067         "scifb0_clk",
4068         "scifb0_ctrl",
4069         "scifb0_data_b",
4070         "scifb0_clk_b",
4071         "scifb0_ctrl_b",
4072         "scifb0_data_c",
4073         "scifb0_clk_c",
4074         "scifb0_data_d",
4075         "scifb0_clk_d",
4076 };
4077 static const char * const scifb1_groups[] = {
4078         "scifb1_data",
4079         "scifb1_clk",
4080         "scifb1_ctrl",
4081         "scifb1_data_b",
4082         "scifb1_clk_b",
4083         "scifb1_data_c",
4084         "scifb1_clk_c",
4085         "scifb1_data_d",
4086 };
4087 static const char * const scifb2_groups[] = {
4088         "scifb2_data",
4089         "scifb2_clk",
4090         "scifb2_ctrl",
4091         "scifb2_data_b",
4092         "scifb2_clk_b",
4093         "scifb2_ctrl_b",
4094         "scifb0_data_c",
4095         "scifb2_clk_c",
4096         "scifb2_data_d",
4097 };
4098
4099 static const char * const sdhi0_groups[] = {
4100         "sdhi0_data1",
4101         "sdhi0_data4",
4102         "sdhi0_ctrl",
4103         "sdhi0_cd",
4104         "sdhi0_wp",
4105 };
4106
4107 static const char * const sdhi1_groups[] = {
4108         "sdhi1_data1",
4109         "sdhi1_data4",
4110         "sdhi1_ctrl",
4111         "sdhi1_cd",
4112         "sdhi1_wp",
4113 };
4114
4115 static const char * const sdhi2_groups[] = {
4116         "sdhi2_data1",
4117         "sdhi2_data4",
4118         "sdhi2_ctrl",
4119         "sdhi2_cd",
4120         "sdhi2_wp",
4121 };
4122
4123 static const char * const usb0_groups[] = {
4124         "usb0",
4125 };
4126 static const char * const usb1_groups[] = {
4127         "usb1",
4128 };
4129
4130 static const char * const vin0_groups[] = {
4131         "vin0_data24",
4132         "vin0_data20",
4133         "vin0_data18",
4134         "vin0_data16",
4135         "vin0_data12",
4136         "vin0_data10",
4137         "vin0_data8",
4138         "vin0_sync",
4139         "vin0_field",
4140         "vin0_clkenb",
4141         "vin0_clk",
4142 };
4143
4144 static const char * const vin1_groups[] = {
4145         "vin1_data8",
4146         "vin1_sync",
4147         "vin1_field",
4148         "vin1_clkenb",
4149         "vin1_clk",
4150         "vin1_b_data24",
4151         "vin1_b_data20",
4152         "vin1_b_data18",
4153         "vin1_b_data16",
4154         "vin1_b_data12",
4155         "vin1_b_data10",
4156         "vin1_b_data8",
4157         "vin1_b_sync",
4158         "vin1_b_field",
4159         "vin1_b_clkenb",
4160         "vin1_b_clk",
4161 };
4162
4163 static const char * const vin2_groups[] = {
4164         "vin2_data8",
4165         "vin2_sync",
4166         "vin2_field",
4167         "vin2_clkenb",
4168         "vin2_clk",
4169 };
4170
4171 static const struct sh_pfc_function pinmux_functions[] = {
4172         SH_PFC_FUNCTION(du),
4173         SH_PFC_FUNCTION(du0),
4174         SH_PFC_FUNCTION(du1),
4175         SH_PFC_FUNCTION(eth),
4176         SH_PFC_FUNCTION(i2c0),
4177         SH_PFC_FUNCTION(i2c1),
4178         SH_PFC_FUNCTION(i2c2),
4179         SH_PFC_FUNCTION(i2c3),
4180         SH_PFC_FUNCTION(i2c4),
4181         SH_PFC_FUNCTION(i2c7),
4182         SH_PFC_FUNCTION(i2c8),
4183         SH_PFC_FUNCTION(intc),
4184         SH_PFC_FUNCTION(mmc),
4185         SH_PFC_FUNCTION(msiof0),
4186         SH_PFC_FUNCTION(msiof1),
4187         SH_PFC_FUNCTION(msiof2),
4188         SH_PFC_FUNCTION(qspi),
4189         SH_PFC_FUNCTION(scif0),
4190         SH_PFC_FUNCTION(scif1),
4191         SH_PFC_FUNCTION(scif2),
4192         SH_PFC_FUNCTION(scif3),
4193         SH_PFC_FUNCTION(scif4),
4194         SH_PFC_FUNCTION(scif5),
4195         SH_PFC_FUNCTION(scifa0),
4196         SH_PFC_FUNCTION(scifa1),
4197         SH_PFC_FUNCTION(scifa2),
4198         SH_PFC_FUNCTION(scifa3),
4199         SH_PFC_FUNCTION(scifa4),
4200         SH_PFC_FUNCTION(scifa5),
4201         SH_PFC_FUNCTION(scifb0),
4202         SH_PFC_FUNCTION(scifb1),
4203         SH_PFC_FUNCTION(scifb2),
4204         SH_PFC_FUNCTION(sdhi0),
4205         SH_PFC_FUNCTION(sdhi1),
4206         SH_PFC_FUNCTION(sdhi2),
4207         SH_PFC_FUNCTION(usb0),
4208         SH_PFC_FUNCTION(usb1),
4209         SH_PFC_FUNCTION(vin0),
4210         SH_PFC_FUNCTION(vin1),
4211         SH_PFC_FUNCTION(vin2),
4212 };
4213
4214 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4215         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4216                 GP_0_31_FN, FN_IP1_22_20,
4217                 GP_0_30_FN, FN_IP1_19_17,
4218                 GP_0_29_FN, FN_IP1_16_14,
4219                 GP_0_28_FN, FN_IP1_13_11,
4220                 GP_0_27_FN, FN_IP1_10_8,
4221                 GP_0_26_FN, FN_IP1_7_6,
4222                 GP_0_25_FN, FN_IP1_5_4,
4223                 GP_0_24_FN, FN_IP1_3_2,
4224                 GP_0_23_FN, FN_IP1_1_0,
4225                 GP_0_22_FN, FN_IP0_30_29,
4226                 GP_0_21_FN, FN_IP0_28_27,
4227                 GP_0_20_FN, FN_IP0_26_25,
4228                 GP_0_19_FN, FN_IP0_24_23,
4229                 GP_0_18_FN, FN_IP0_22_21,
4230                 GP_0_17_FN, FN_IP0_20_19,
4231                 GP_0_16_FN, FN_IP0_18_16,
4232                 GP_0_15_FN, FN_IP0_15,
4233                 GP_0_14_FN, FN_IP0_14,
4234                 GP_0_13_FN, FN_IP0_13,
4235                 GP_0_12_FN, FN_IP0_12,
4236                 GP_0_11_FN, FN_IP0_11,
4237                 GP_0_10_FN, FN_IP0_10,
4238                 GP_0_9_FN, FN_IP0_9,
4239                 GP_0_8_FN, FN_IP0_8,
4240                 GP_0_7_FN, FN_IP0_7,
4241                 GP_0_6_FN, FN_IP0_6,
4242                 GP_0_5_FN, FN_IP0_5,
4243                 GP_0_4_FN, FN_IP0_4,
4244                 GP_0_3_FN, FN_IP0_3,
4245                 GP_0_2_FN, FN_IP0_2,
4246                 GP_0_1_FN, FN_IP0_1,
4247                 GP_0_0_FN, FN_IP0_0, }
4248         },
4249         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4250                 0, 0,
4251                 0, 0,
4252                 0, 0,
4253                 0, 0,
4254                 0, 0,
4255                 0, 0,
4256                 GP_1_25_FN, FN_IP3_21_20,
4257                 GP_1_24_FN, FN_IP3_19_18,
4258                 GP_1_23_FN, FN_IP3_17_16,
4259                 GP_1_22_FN, FN_IP3_15_14,
4260                 GP_1_21_FN, FN_IP3_13_12,
4261                 GP_1_20_FN, FN_IP3_11_9,
4262                 GP_1_19_FN, FN_RD_N,
4263                 GP_1_18_FN, FN_IP3_8_6,
4264                 GP_1_17_FN, FN_IP3_5_3,
4265                 GP_1_16_FN, FN_IP3_2_0,
4266                 GP_1_15_FN, FN_IP2_29_27,
4267                 GP_1_14_FN, FN_IP2_26_25,
4268                 GP_1_13_FN, FN_IP2_24_23,
4269                 GP_1_12_FN, FN_EX_CS0_N,
4270                 GP_1_11_FN, FN_IP2_22_21,
4271                 GP_1_10_FN, FN_IP2_20_19,
4272                 GP_1_9_FN, FN_IP2_18_16,
4273                 GP_1_8_FN, FN_IP2_15_13,
4274                 GP_1_7_FN, FN_IP2_12_10,
4275                 GP_1_6_FN, FN_IP2_9_7,
4276                 GP_1_5_FN, FN_IP2_6_5,
4277                 GP_1_4_FN, FN_IP2_4_3,
4278                 GP_1_3_FN, FN_IP2_2_0,
4279                 GP_1_2_FN, FN_IP1_31_29,
4280                 GP_1_1_FN, FN_IP1_28_26,
4281                 GP_1_0_FN, FN_IP1_25_23, }
4282         },
4283         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4284                 GP_2_31_FN, FN_IP6_7_6,
4285                 GP_2_30_FN, FN_IP6_5_3,
4286                 GP_2_29_FN, FN_IP6_2_0,
4287                 GP_2_28_FN, FN_AUDIO_CLKA,
4288                 GP_2_27_FN, FN_IP5_31_29,
4289                 GP_2_26_FN, FN_IP5_28_26,
4290                 GP_2_25_FN, FN_IP5_25_24,
4291                 GP_2_24_FN, FN_IP5_23_22,
4292                 GP_2_23_FN, FN_IP5_21_20,
4293                 GP_2_22_FN, FN_IP5_19_17,
4294                 GP_2_21_FN, FN_IP5_16_15,
4295                 GP_2_20_FN, FN_IP5_14_12,
4296                 GP_2_19_FN, FN_IP5_11_9,
4297                 GP_2_18_FN, FN_IP5_8_6,
4298                 GP_2_17_FN, FN_IP5_5_3,
4299                 GP_2_16_FN, FN_IP5_2_0,
4300                 GP_2_15_FN, FN_IP4_30_28,
4301                 GP_2_14_FN, FN_IP4_27_26,
4302                 GP_2_13_FN, FN_IP4_25_24,
4303                 GP_2_12_FN, FN_IP4_23_22,
4304                 GP_2_11_FN, FN_IP4_21,
4305                 GP_2_10_FN, FN_IP4_20,
4306                 GP_2_9_FN, FN_IP4_19,
4307                 GP_2_8_FN, FN_IP4_18_16,
4308                 GP_2_7_FN, FN_IP4_15_13,
4309                 GP_2_6_FN, FN_IP4_12_10,
4310                 GP_2_5_FN, FN_IP4_9_8,
4311                 GP_2_4_FN, FN_IP4_7_5,
4312                 GP_2_3_FN, FN_IP4_4_2,
4313                 GP_2_2_FN, FN_IP4_1_0,
4314                 GP_2_1_FN, FN_IP3_30_28,
4315                 GP_2_0_FN, FN_IP3_27_25 }
4316         },
4317         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4318                 GP_3_31_FN, FN_IP9_18_17,
4319                 GP_3_30_FN, FN_IP9_16,
4320                 GP_3_29_FN, FN_IP9_15_13,
4321                 GP_3_28_FN, FN_IP9_12,
4322                 GP_3_27_FN, FN_IP9_11,
4323                 GP_3_26_FN, FN_IP9_10_8,
4324                 GP_3_25_FN, FN_IP9_7,
4325                 GP_3_24_FN, FN_IP9_6,
4326                 GP_3_23_FN, FN_IP9_5_3,
4327                 GP_3_22_FN, FN_IP9_2_0,
4328                 GP_3_21_FN, FN_IP8_30_28,
4329                 GP_3_20_FN, FN_IP8_27_26,
4330                 GP_3_19_FN, FN_IP8_25_24,
4331                 GP_3_18_FN, FN_IP8_23_21,
4332                 GP_3_17_FN, FN_IP8_20_18,
4333                 GP_3_16_FN, FN_IP8_17_15,
4334                 GP_3_15_FN, FN_IP8_14_12,
4335                 GP_3_14_FN, FN_IP8_11_9,
4336                 GP_3_13_FN, FN_IP8_8_6,
4337                 GP_3_12_FN, FN_IP8_5_3,
4338                 GP_3_11_FN, FN_IP8_2_0,
4339                 GP_3_10_FN, FN_IP7_29_27,
4340                 GP_3_9_FN, FN_IP7_26_24,
4341                 GP_3_8_FN, FN_IP7_23_21,
4342                 GP_3_7_FN, FN_IP7_20_19,
4343                 GP_3_6_FN, FN_IP7_18_17,
4344                 GP_3_5_FN, FN_IP7_16_15,
4345                 GP_3_4_FN, FN_IP7_14_13,
4346                 GP_3_3_FN, FN_IP7_12_11,
4347                 GP_3_2_FN, FN_IP7_10_9,
4348                 GP_3_1_FN, FN_IP7_8_6,
4349                 GP_3_0_FN, FN_IP7_5_3 }
4350         },
4351         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4352                 GP_4_31_FN, FN_IP15_5_4,
4353                 GP_4_30_FN, FN_IP15_3_2,
4354                 GP_4_29_FN, FN_IP15_1_0,
4355                 GP_4_28_FN, FN_IP11_8_6,
4356                 GP_4_27_FN, FN_IP11_5_3,
4357                 GP_4_26_FN, FN_IP11_2_0,
4358                 GP_4_25_FN, FN_IP10_31_29,
4359                 GP_4_24_FN, FN_IP10_28_27,
4360                 GP_4_23_FN, FN_IP10_26_25,
4361                 GP_4_22_FN, FN_IP10_24_22,
4362                 GP_4_21_FN, FN_IP10_21_19,
4363                 GP_4_20_FN, FN_IP10_18_17,
4364                 GP_4_19_FN, FN_IP10_16_15,
4365                 GP_4_18_FN, FN_IP10_14_12,
4366                 GP_4_17_FN, FN_IP10_11_9,
4367                 GP_4_16_FN, FN_IP10_8_6,
4368                 GP_4_15_FN, FN_IP10_5_3,
4369                 GP_4_14_FN, FN_IP10_2_0,
4370                 GP_4_13_FN, FN_IP9_31_29,
4371                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
4372                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
4373                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
4374                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
4375                 GP_4_8_FN, FN_IP9_28_27,
4376                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
4377                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
4378                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
4379                 GP_4_4_FN, FN_IP9_26_25,
4380                 GP_4_3_FN, FN_IP9_24_23,
4381                 GP_4_2_FN, FN_IP9_22_21,
4382                 GP_4_1_FN, FN_IP9_20_19,
4383                 GP_4_0_FN, FN_VI0_CLK }
4384         },
4385         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4386                 GP_5_31_FN, FN_IP3_24_22,
4387                 GP_5_30_FN, FN_IP13_9_7,
4388                 GP_5_29_FN, FN_IP13_6_5,
4389                 GP_5_28_FN, FN_IP13_4_3,
4390                 GP_5_27_FN, FN_IP13_2_0,
4391                 GP_5_26_FN, FN_IP12_29_27,
4392                 GP_5_25_FN, FN_IP12_26_24,
4393                 GP_5_24_FN, FN_IP12_23_22,
4394                 GP_5_23_FN, FN_IP12_21_20,
4395                 GP_5_22_FN, FN_IP12_19_18,
4396                 GP_5_21_FN, FN_IP12_17_16,
4397                 GP_5_20_FN, FN_IP12_15_13,
4398                 GP_5_19_FN, FN_IP12_12_10,
4399                 GP_5_18_FN, FN_IP12_9_7,
4400                 GP_5_17_FN, FN_IP12_6_4,
4401                 GP_5_16_FN, FN_IP12_3_2,
4402                 GP_5_15_FN, FN_IP12_1_0,
4403                 GP_5_14_FN, FN_IP11_31_30,
4404                 GP_5_13_FN, FN_IP11_29_28,
4405                 GP_5_12_FN, FN_IP11_27,
4406                 GP_5_11_FN, FN_IP11_26,
4407                 GP_5_10_FN, FN_IP11_25,
4408                 GP_5_9_FN, FN_IP11_24,
4409                 GP_5_8_FN, FN_IP11_23,
4410                 GP_5_7_FN, FN_IP11_22,
4411                 GP_5_6_FN, FN_IP11_21,
4412                 GP_5_5_FN, FN_IP11_20,
4413                 GP_5_4_FN, FN_IP11_19,
4414                 GP_5_3_FN, FN_IP11_18_17,
4415                 GP_5_2_FN, FN_IP11_16_15,
4416                 GP_5_1_FN, FN_IP11_14_12,
4417                 GP_5_0_FN, FN_IP11_11_9 }
4418         },
4419         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4420                 GP_6_31_FN, FN_DU0_DOTCLKIN,
4421                 GP_6_30_FN, FN_USB1_OVC,
4422                 GP_6_29_FN, FN_IP14_31_29,
4423                 GP_6_28_FN, FN_IP14_28_26,
4424                 GP_6_27_FN, FN_IP14_25_23,
4425                 GP_6_26_FN, FN_IP14_22_20,
4426                 GP_6_25_FN, FN_IP14_19_17,
4427                 GP_6_24_FN, FN_IP14_16_14,
4428                 GP_6_23_FN, FN_IP14_13_11,
4429                 GP_6_22_FN, FN_IP14_10_8,
4430                 GP_6_21_FN, FN_IP14_7,
4431                 GP_6_20_FN, FN_IP14_6,
4432                 GP_6_19_FN, FN_IP14_5,
4433                 GP_6_18_FN, FN_IP14_4,
4434                 GP_6_17_FN, FN_IP14_3,
4435                 GP_6_16_FN, FN_IP14_2,
4436                 GP_6_15_FN, FN_IP14_1_0,
4437                 GP_6_14_FN, FN_IP13_30_28,
4438                 GP_6_13_FN, FN_IP13_27,
4439                 GP_6_12_FN, FN_IP13_26,
4440                 GP_6_11_FN, FN_IP13_25,
4441                 GP_6_10_FN, FN_IP13_24_23,
4442                 GP_6_9_FN, FN_IP13_22,
4443                 GP_6_8_FN, FN_SD1_CLK,
4444                 GP_6_7_FN, FN_IP13_21_19,
4445                 GP_6_6_FN, FN_IP13_18_16,
4446                 GP_6_5_FN, FN_IP13_15,
4447                 GP_6_4_FN, FN_IP13_14,
4448                 GP_6_3_FN, FN_IP13_13,
4449                 GP_6_2_FN, FN_IP13_12,
4450                 GP_6_1_FN, FN_IP13_11,
4451                 GP_6_0_FN, FN_IP13_10 }
4452         },
4453         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
4454                 0, 0,
4455                 0, 0,
4456                 0, 0,
4457                 0, 0,
4458                 0, 0,
4459                 0, 0,
4460                 GP_7_25_FN, FN_USB1_PWEN,
4461                 GP_7_24_FN, FN_USB0_OVC,
4462                 GP_7_23_FN, FN_USB0_PWEN,
4463                 GP_7_22_FN, FN_IP15_14_12,
4464                 GP_7_21_FN, FN_IP15_11_9,
4465                 GP_7_20_FN, FN_IP15_8_6,
4466                 GP_7_19_FN, FN_IP7_2_0,
4467                 GP_7_18_FN, FN_IP6_29_27,
4468                 GP_7_17_FN, FN_IP6_26_24,
4469                 GP_7_16_FN, FN_IP6_23_21,
4470                 GP_7_15_FN, FN_IP6_20_19,
4471                 GP_7_14_FN, FN_IP6_18_16,
4472                 GP_7_13_FN, FN_IP6_15_14,
4473                 GP_7_12_FN, FN_IP6_13_12,
4474                 GP_7_11_FN, FN_IP6_11_10,
4475                 GP_7_10_FN, FN_IP6_9_8,
4476                 GP_7_9_FN, FN_IP16_11_10,
4477                 GP_7_8_FN, FN_IP16_9_8,
4478                 GP_7_7_FN, FN_IP16_7_6,
4479                 GP_7_6_FN, FN_IP16_5_3,
4480                 GP_7_5_FN, FN_IP16_2_0,
4481                 GP_7_4_FN, FN_IP15_29_27,
4482                 GP_7_3_FN, FN_IP15_26_24,
4483                 GP_7_2_FN, FN_IP15_23_21,
4484                 GP_7_1_FN, FN_IP15_20_18,
4485                 GP_7_0_FN, FN_IP15_17_15 }
4486         },
4487         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4488                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
4489                              1, 1, 1, 1, 1, 1, 1, 1) {
4490                 /* IP0_31 [1] */
4491                 0, 0,
4492                 /* IP0_30_29 [2] */
4493                 FN_A6, FN_MSIOF1_SCK,
4494                 0, 0,
4495                 /* IP0_28_27 [2] */
4496                 FN_A5, FN_MSIOF0_RXD_B,
4497                 0, 0,
4498                 /* IP0_26_25 [2] */
4499                 FN_A4, FN_MSIOF0_TXD_B,
4500                 0, 0,
4501                 /* IP0_24_23 [2] */
4502                 FN_A3, FN_MSIOF0_SS2_B,
4503                 0, 0,
4504                 /* IP0_22_21 [2] */
4505                 FN_A2, FN_MSIOF0_SS1_B,
4506                 0, 0,
4507                 /* IP0_20_19 [2] */
4508                 FN_A1, FN_MSIOF0_SYNC_B,
4509                 0, 0,
4510                 /* IP0_18_16 [3] */
4511                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
4512                 0, 0, 0,
4513                 /* IP0_15 [1] */
4514                 FN_D15, 0,
4515                 /* IP0_14 [1] */
4516                 FN_D14, 0,
4517                 /* IP0_13 [1] */
4518                 FN_D13, 0,
4519                 /* IP0_12 [1] */
4520                 FN_D12, 0,
4521                 /* IP0_11 [1] */
4522                 FN_D11, 0,
4523                 /* IP0_10 [1] */
4524                 FN_D10, 0,
4525                 /* IP0_9 [1] */
4526                 FN_D9, 0,
4527                 /* IP0_8 [1] */
4528                 FN_D8, 0,
4529                 /* IP0_7 [1] */
4530                 FN_D7, 0,
4531                 /* IP0_6 [1] */
4532                 FN_D6, 0,
4533                 /* IP0_5 [1] */
4534                 FN_D5, 0,
4535                 /* IP0_4 [1] */
4536                 FN_D4, 0,
4537                 /* IP0_3 [1] */
4538                 FN_D3, 0,
4539                 /* IP0_2 [1] */
4540                 FN_D2, 0,
4541                 /* IP0_1 [1] */
4542                 FN_D1, 0,
4543                 /* IP0_0 [1] */
4544                 FN_D0, 0, }
4545         },
4546         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4547                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
4548                 /* IP1_31_29 [3] */
4549                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
4550                 0, 0, 0,
4551                 /* IP1_28_26 [3] */
4552                 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
4553                 0, 0, 0, 0,
4554                 /* IP1_25_23 [3] */
4555                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
4556                 0, 0, 0,
4557                 /* IP1_22_20 [3] */
4558                 FN_A15, FN_BPFCLK_C,
4559                 0, 0, 0, 0, 0, 0,
4560                 /* IP1_19_17 [3] */
4561                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
4562                 0, 0, 0,
4563                 /* IP1_16_14 [3] */
4564                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
4565                 0, 0, 0, 0,
4566                 /* IP1_13_11 [3] */
4567                 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
4568                 0, 0, 0, 0,
4569                 /* IP1_10_8 [3] */
4570                 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
4571                 0, 0, 0, 0,
4572                 /* IP1_7_6 [2] */
4573                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
4574                 /* IP1_5_4 [2] */
4575                 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
4576                 /* IP1_3_2 [2] */
4577                 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
4578                 /* IP1_1_0 [2] */
4579                 FN_A7, FN_MSIOF1_SYNC,
4580                 0, 0, }
4581         },
4582         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4583                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
4584                 /* IP2_31_20 [2] */
4585                 0, 0, 0, 0,
4586                 /* IP2_29_27 [3] */
4587                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
4588                 FN_ATAG0_N, 0, FN_EX_WAIT1,
4589                 0, 0,
4590                 /* IP2_26_25 [2] */
4591                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
4592                 /* IP2_24_23 [2] */
4593                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
4594                 /* IP2_22_21 [2] */
4595                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
4596                 /* IP2_20_19 [2] */
4597                 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
4598                 /* IP2_18_16 [3] */
4599                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
4600                 0, 0,
4601                 /* IP2_15_13 [3] */
4602                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
4603                 0, 0, 0,
4604                 /* IP2_12_0 [3] */
4605                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
4606                 0, 0, 0,
4607                 /* IP2_9_7 [3] */
4608                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
4609                 0, 0, 0,
4610                 /* IP2_6_5 [2] */
4611                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
4612                 /* IP2_4_3 [2] */
4613                 FN_A20, FN_SPCLK, 0, 0,
4614                 /* IP2_2_0 [3] */
4615                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
4616                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
4617         },
4618         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4619                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
4620                 /* IP3_31 [1] */
4621                 0, 0,
4622                 /* IP3_30_28 [3] */
4623                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
4624                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
4625                 0, 0, 0,
4626                 /* IP3_27_25 [3] */
4627                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
4628                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
4629                 0, 0, 0,
4630                 /* IP3_24_22 [3] */
4631                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
4632                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
4633                 /* IP3_21_20 [2] */
4634                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
4635                 /* IP3_19_18 [2] */
4636                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
4637                 /* IP3_17_16 [2] */
4638                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
4639                 /* IP3_15_14 [2] */
4640                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
4641                 /* IP3_13_12 [2] */
4642                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
4643                 /* IP3_11_9 [3] */
4644                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
4645                 0, 0, 0,
4646                 /* IP3_8_6 [3] */
4647                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
4648                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
4649                 /* IP3_5_3 [3] */
4650                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
4651                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
4652                 /* IP3_2_0 [3] */
4653                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
4654                 0, 0, 0, }
4655         },
4656         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4657                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
4658                 /* IP4_31 [1] */
4659                 0, 0,
4660                 /* IP4_30_28 [3] */
4661                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
4662                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
4663                 0, 0,
4664                 /* IP4_27_26 [2] */
4665                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
4666                 /* IP4_25_24 [2] */
4667                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
4668                 /* IP4_23_22 [2] */
4669                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
4670                 /* IP4_21 [1] */
4671                 FN_SSI_SDATA3, 0,
4672                 /* IP4_20 [1] */
4673                 FN_SSI_WS34, 0,
4674                 /* IP4_19 [1] */
4675                 FN_SSI_SCK34, 0,
4676                 /* IP4_18_16 [3] */
4677                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
4678                 0, 0, 0, 0,
4679                 /* IP4_15_13 [3] */
4680                 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
4681                 FN_GLO_Q1_D, FN_HCTS1_N_E,
4682                 0, 0,
4683                 /* IP4_12_10 [3] */
4684                 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
4685                 0, 0, 0,
4686                 /* IP4_9_8 [2] */
4687                 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
4688                 /* IP4_7_5 [3] */
4689                 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
4690                 0, 0, 0,
4691                 /* IP4_4_2 [3] */
4692                 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
4693                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
4694                 0, 0, 0,
4695                 /* IP4_1_0 [2] */
4696                 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
4697         },
4698         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4699                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
4700                 /* IP5_31_29 [3] */
4701                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
4702                 0, 0, 0, 0, 0,
4703                 /* IP5_28_26 [3] */
4704                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
4705                 0, 0, 0, 0,
4706                 /* IP5_25_24 [2] */
4707                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
4708                 /* IP5_23_22 [2] */
4709                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
4710                 /* IP5_21_20 [2] */
4711                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
4712                 /* IP5_19_17 [3] */
4713                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
4714                 0, 0, 0, 0,
4715                 /* IP5_16_15 [2] */
4716                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
4717                 /* IP5_14_12 [3] */
4718                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
4719                 0, 0, 0, 0,
4720                 /* IP5_11_9 [3] */
4721                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
4722                 0, 0, 0, 0,
4723                 /* IP5_8_6 [3] */
4724                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
4725                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
4726                 0, 0,
4727                 /* IP5_5_3 [3] */
4728                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
4729                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
4730                 0, 0,
4731                 /* IP5_2_0 [3] */
4732                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
4733                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
4734                 0, 0, }
4735         },
4736         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4737                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
4738                 /* IP6_31_30 [2] */
4739                 0, 0, 0, 0,
4740                 /* IP6_29_27 [3] */
4741                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
4742                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
4743                 0, 0, 0,
4744                 /* IP6_26_24 [3] */
4745                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
4746                 FN_GPS_CLK_C, FN_GPS_CLK_D,
4747                 0, 0, 0,
4748                 /* IP6_23_21 [3] */
4749                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
4750                 FN_SDA1_E, FN_MSIOF2_SYNC_E,
4751                 0, 0, 0,
4752                 /* IP6_20_19 [2] */
4753                 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
4754                 /* IP6_18_16 [3] */
4755                 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
4756                 0, 0, 0,
4757                 /* IP6_15_14 [2] */
4758                 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
4759                 /* IP6_13_12 [2] */
4760                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
4761                 /* IP6_11_10 [2] */
4762                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
4763                 /* IP6_9_8 [2] */
4764                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
4765                 /* IP6_7_6 [2] */
4766                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
4767                 /* IP6_5_3 [3] */
4768                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
4769                 FN_SCIFA2_RXD, FN_FMIN_E,
4770                 0, 0,
4771                 /* IP6_2_0 [3] */
4772                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
4773                 FN_SCIF_CLK, 0, FN_BPFCLK_E,
4774                 0, 0, }
4775         },
4776         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4777                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
4778                 /* IP7_31_30 [2] */
4779                 0, 0, 0, 0,
4780                 /* IP7_29_27 [3] */
4781                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
4782                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
4783                 0, 0,
4784                 /* IP7_26_24 [3] */
4785                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
4786                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
4787                 0, 0,
4788                 /* IP7_23_21 [3] */
4789                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
4790                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
4791                 0, 0,
4792                 /* IP7_20_19 [2] */
4793                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
4794                 /* IP7_18_17 [2] */
4795                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
4796                 /* IP7_16_15 [2] */
4797                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
4798                 /* IP7_14_13 [2] */
4799                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
4800                 /* IP7_12_11 [2] */
4801                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
4802                 /* IP7_10_9 [2] */
4803                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
4804                 /* IP7_8_6 [3] */
4805                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
4806                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
4807                 0, 0,
4808                 /* IP7_5_3 [3] */
4809                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
4810                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
4811                 0, 0,
4812                 /* IP7_2_0 [3] */
4813                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
4814                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
4815                 0, 0, }
4816         },
4817         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4818                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
4819                 /* IP8_31 [1] */
4820                 0, 0,
4821                 /* IP8_30_28 [3] */
4822                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
4823                 0, 0, 0,
4824                 /* IP8_27_26 [2] */
4825                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
4826                 /* IP8_25_24 [2] */
4827                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
4828                 /* IP8_23_21 [3] */
4829                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
4830                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
4831                 0, 0,
4832                 /* IP8_20_18 [3] */
4833                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
4834                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
4835                 0, 0,
4836                 /* IP8_17_15 [3] */
4837                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
4838                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
4839                 0, 0,
4840                 /* IP8_14_12 [3] */
4841                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
4842                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
4843                 0, 0, 0,
4844                 /* IP8_11_9 [3] */
4845                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
4846                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
4847                 0, 0, 0,
4848                 /* IP8_8_6 [3] */
4849                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
4850                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
4851                 0, 0,
4852                 /* IP8_5_3 [3] */
4853                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
4854                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
4855                 0, 0,
4856                 /* IP8_2_0 [3] */
4857                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
4858                 0, 0, 0, }
4859         },
4860         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4861                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
4862                 /* IP9_31_29 [3] */
4863                 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
4864                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
4865                 /* IP9_28_27 [2] */
4866                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
4867                 /* IP9_26_25 [2] */
4868                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
4869                 /* IP9_24_23 [2] */
4870                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
4871                 /* IP9_22_21 [2] */
4872                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
4873                 /* IP9_20_19 [2] */
4874                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
4875                 /* IP9_18_17 [2] */
4876                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
4877                 /* IP9_16 [1] */
4878                 FN_DU1_DISP, FN_QPOLA,
4879                 /* IP9_15_13 [3] */
4880                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
4881                 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
4882                 0, 0, 0,
4883                 /* IP9_12 [1] */
4884                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
4885                 /* IP9_11 [1] */
4886                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
4887                 /* IP9_10_8 [3] */
4888                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
4889                 FN_TX3_B, FN_SCL2_B, FN_PWM4,
4890                 0, 0,
4891                 /* IP9_7 [1] */
4892                 FN_DU1_DOTCLKOUT0, FN_QCLK,
4893                 /* IP9_6 [1] */
4894                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
4895                 /* IP9_5_3 [3] */
4896                 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
4897                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
4898                 0, 0, 0,
4899                 /* IP9_2_0 [3] */
4900                 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
4901                 0, 0, 0, }
4902         },
4903         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4904                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
4905                 /* IP10_31_29 [3] */
4906                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
4907                 0, 0, 0,
4908                 /* IP10_28_27 [2] */
4909                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
4910                 /* IP10_26_25 [2] */
4911                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
4912                 /* IP10_24_22 [3] */
4913                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
4914                 0, 0, 0,
4915                 /* IP10_21_29 [3] */
4916                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
4917                 FN_TS_SDATA0_C, FN_ATACS11_N,
4918                 0, 0, 0,
4919                 /* IP10_18_17 [2] */
4920                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
4921                 /* IP10_16_15 [2] */
4922                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
4923                 /* IP10_14_12 [3] */
4924                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
4925                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
4926                 /* IP10_11_9 [3] */
4927                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
4928                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
4929                 0, 0,
4930                 /* IP10_8_6 [3] */
4931                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
4932                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
4933                 /* IP10_5_3 [3] */
4934                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
4935                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
4936                 /* IP10_2_0 [3] */
4937                 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
4938                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
4939         },
4940         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4941                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4942                              3, 3, 3, 3, 3) {
4943                 /* IP11_31_30 [2] */
4944                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
4945                 /* IP11_29_28 [2] */
4946                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
4947                 /* IP11_27 [1] */
4948                 FN_VI1_DATA7, FN_AVB_MDC,
4949                 /* IP11_26 [1] */
4950                 FN_VI1_DATA6, FN_AVB_MAGIC,
4951                 /* IP11_25 [1] */
4952                 FN_VI1_DATA5, FN_AVB_RX_DV,
4953                 /* IP11_24 [1] */
4954                 FN_VI1_DATA4, FN_AVB_MDIO,
4955                 /* IP11_23 [1] */
4956                 FN_VI1_DATA3, FN_AVB_RX_ER,
4957                 /* IP11_22 [1] */
4958                 FN_VI1_DATA2, FN_AVB_RXD7,
4959                 /* IP11_21 [1] */
4960                 FN_VI1_DATA1, FN_AVB_RXD6,
4961                 /* IP11_20 [1] */
4962                 FN_VI1_DATA0, FN_AVB_RXD5,
4963                 /* IP11_19 [1] */
4964                 FN_VI1_CLK, FN_AVB_RXD4,
4965                 /* IP11_18_17 [2] */
4966                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
4967                 /* IP11_16_15 [2] */
4968                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
4969                 /* IP11_14_12 [3] */
4970                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
4971                 FN_RX4_B, FN_SCIFA4_RXD_B,
4972                 0, 0, 0,
4973                 /* IP11_11_9 [3] */
4974                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
4975                 FN_TX4_B, FN_SCIFA4_TXD_B,
4976                 0, 0, 0,
4977                 /* IP11_8_6 [3] */
4978                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
4979                 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
4980                 /* IP11_5_3 [3] */
4981                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
4982                 0, 0, 0,
4983                 /* IP11_2_0 [3] */
4984                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
4985                 0, 0, 0, }
4986         },
4987         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4988                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
4989                 /* IP12_31_30 [2] */
4990                 0, 0, 0, 0,
4991                 /* IP12_29_27 [3] */
4992                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
4993                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
4994                 0, 0, 0,
4995                 /* IP12_26_24 [3] */
4996                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
4997                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
4998                 0, 0, 0,
4999                 /* IP12_23_22 [2] */
5000                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
5001                 /* IP12_21_20 [2] */
5002                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
5003                 /* IP12_19_18 [2] */
5004                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
5005                 /* IP12_17_16 [2] */
5006                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
5007                 /* IP12_15_13 [3] */
5008                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
5009                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
5010                 0, 0, 0,
5011                 /* IP12_12_10 [3] */
5012                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
5013                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
5014                 0, 0, 0,
5015                 /* IP12_9_7 [3] */
5016                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
5017                 FN_SDA2_D, FN_MSIOF1_SCK_E,
5018                 0, 0, 0,
5019                 /* IP12_6_4 [3] */
5020                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
5021                 FN_SCL2_D, FN_MSIOF1_RXD_E,
5022                 0, 0, 0,
5023                 /* IP12_3_2 [2] */
5024                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
5025                 /* IP12_1_0 [2] */
5026                 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
5027         },
5028         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5029                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
5030                              3, 2, 2, 3) {
5031                 /* IP13_31 [1] */
5032                 0, 0,
5033                 /* IP13_30_28 [3] */
5034                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
5035                 0, 0, 0, 0,
5036                 /* IP13_27 [1] */
5037                 FN_SD1_DATA3, FN_IERX_B,
5038                 /* IP13_26 [1] */
5039                 FN_SD1_DATA2, FN_IECLK_B,
5040                 /* IP13_25 [1] */
5041                 FN_SD1_DATA1, FN_IETX_B,
5042                 /* IP13_24_23 [2] */
5043                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
5044                 /* IP13_22 [1] */
5045                 FN_SD1_CMD, FN_REMOCON_B,
5046                 /* IP13_21_19 [3] */
5047                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
5048                 FN_SCIFA5_RXD_B, FN_RX3_C,
5049                 0, 0,
5050                 /* IP13_18_16 [3] */
5051                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
5052                 FN_SCIFA5_TXD_B, FN_TX3_C,
5053                 0, 0,
5054                 /* IP13_15 [1] */
5055                 FN_SD0_DATA3, FN_SSL_B,
5056                 /* IP13_14 [1] */
5057                 FN_SD0_DATA2, FN_IO3_B,
5058                 /* IP13_13 [1] */
5059                 FN_SD0_DATA1, FN_IO2_B,
5060                 /* IP13_12 [1] */
5061                 FN_SD0_DATA0, FN_MISO_IO1_B,
5062                 /* IP13_11 [1] */
5063                 FN_SD0_CMD, FN_MOSI_IO0_B,
5064                 /* IP13_10 [1] */
5065                 FN_SD0_CLK, FN_SPCLK_B,
5066                 /* IP13_9_7 [3] */
5067                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
5068                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
5069                 0, 0, 0,
5070                 /* IP13_6_5 [2] */
5071                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
5072                 /* IP13_4_3 [2] */
5073                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
5074                 /* IP13_2_0 [3] */
5075                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
5076                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
5077                 0, 0, 0, }
5078         },
5079         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5080                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
5081                 /* IP14_31_29 [3] */
5082                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
5083                 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
5084                 /* IP14_28_26 [3] */
5085                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
5086                 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
5087                 /* IP14_25_23 [3] */
5088                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
5089                 0, 0, 0,
5090                 /* IP14_22_20 [3] */
5091                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
5092                 0, 0, 0,
5093                 /* IP14_19_17 [3] */
5094                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
5095                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
5096                 0, 0,
5097                 /* IP14_16_14 [3] */
5098                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
5099                 FN_VI1_CLK_C, FN_VI1_G0_B,
5100                 0, 0,
5101                 /* IP14_13_11 [3] */
5102                 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
5103                 0, 0, 0,
5104                 /* IP14_10_8 [3] */
5105                 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
5106                 0, 0, 0,
5107                 /* IP14_7 [1] */
5108                 FN_SD2_DATA3, FN_MMC_D3,
5109                 /* IP14_6 [1] */
5110                 FN_SD2_DATA2, FN_MMC_D2,
5111                 /* IP14_5 [1] */
5112                 FN_SD2_DATA1, FN_MMC_D1,
5113                 /* IP14_4 [1] */
5114                 FN_SD2_DATA0, FN_MMC_D0,
5115                 /* IP14_3 [1] */
5116                 FN_SD2_CMD, FN_MMC_CMD,
5117                 /* IP14_2 [1] */
5118                 FN_SD2_CLK, FN_MMC_CLK,
5119                 /* IP14_1_0 [2] */
5120                 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
5121         },
5122         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5123                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
5124                 /* IP15_31_30 [2] */
5125                 0, 0, 0, 0,
5126                 /* IP15_29_27 [3] */
5127                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
5128                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
5129                 0, 0,
5130                 /* IP15_26_24 [3] */
5131                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
5132                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
5133                 0, 0,
5134                 /* IP15_23_21 [3] */
5135                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
5136                 FN_TCLK2, FN_VI1_DATA3_C, 0,
5137                 /* IP15_20_18 [3] */
5138                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
5139                 0, 0, 0,
5140                 /* IP15_17_15 [3] */
5141                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
5142                 FN_TCLK1, FN_VI1_DATA1_C,
5143                 0, 0,
5144                 /* IP15_14_12 [3] */
5145                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
5146                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
5147                 0, 0,
5148                 /* IP15_11_9 [3] */
5149                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
5150                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
5151                 0, 0,
5152                 /* IP15_8_6 [3] */
5153                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
5154                 FN_PWM5_B, FN_SCIFA3_TXD_C,
5155                 0, 0, 0,
5156                 /* IP15_5_4 [2] */
5157                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
5158                 /* IP15_3_2 [2] */
5159                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
5160                 /* IP15_1_0 [2] */
5161                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
5162         },
5163         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5164                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
5165                 /* IP16_31_28 [4] */
5166                 0, 0, 0, 0, 0, 0, 0, 0,
5167                 0, 0, 0, 0, 0, 0, 0, 0,
5168                 /* IP16_27_24 [4] */
5169                 0, 0, 0, 0, 0, 0, 0, 0,
5170                 0, 0, 0, 0, 0, 0, 0, 0,
5171                 /* IP16_23_20 [4] */
5172                 0, 0, 0, 0, 0, 0, 0, 0,
5173                 0, 0, 0, 0, 0, 0, 0, 0,
5174                 /* IP16_19_16 [4] */
5175                 0, 0, 0, 0, 0, 0, 0, 0,
5176                 0, 0, 0, 0, 0, 0, 0, 0,
5177                 /* IP16_15_12 [4] */
5178                 0, 0, 0, 0, 0, 0, 0, 0,
5179                 0, 0, 0, 0, 0, 0, 0, 0,
5180                 /* IP16_11_10 [2] */
5181                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
5182                 /* IP16_9_8 [2] */
5183                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
5184                 /* IP16_7_6 [2] */
5185                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
5186                 /* IP16_5_3 [3] */
5187                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
5188                 FN_GLO_SS_C, FN_VI1_DATA7_C,
5189                 0, 0, 0,
5190                 /* IP16_2_0 [3] */
5191                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
5192                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
5193                 0, 0, 0, }
5194         },
5195         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5196                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
5197                              3, 2, 2, 2, 1, 2, 2, 2) {
5198                 /* RESEVED [1] */
5199                 0, 0,
5200                 /* SEL_SCIF1 [2] */
5201                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5202                 /* SEL_SCIFB [2] */
5203                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
5204                 /* SEL_SCIFB2 [2] */
5205                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
5206                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
5207                 /* SEL_SCIFB1 [3] */
5208                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
5209                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
5210                 0, 0, 0, 0,
5211                 /* SEL_SCIFA1 [2] */
5212                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5213                 /* SEL_SSI9 [1] */
5214                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5215                 /* SEL_SCFA [1] */
5216                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5217                 /* SEL_QSP [1] */
5218                 FN_SEL_QSP_0, FN_SEL_QSP_1,
5219                 /* SEL_SSI7 [1] */
5220                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5221                 /* SEL_HSCIF1 [3] */
5222                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
5223                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
5224                 0, 0, 0,
5225                 /* RESEVED [2] */
5226                 0, 0, 0, 0,
5227                 /* SEL_VI1 [2] */
5228                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
5229                 /* RESEVED [2] */
5230                 0, 0, 0, 0,
5231                 /* SEL_TMU [1] */
5232                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5233                 /* SEL_LBS [2] */
5234                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
5235                 /* SEL_TSIF0 [2] */
5236                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5237                 /* SEL_SOF0 [2] */
5238                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
5239         },
5240         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5241                              3, 1, 1, 3, 2, 1, 1, 2, 2,
5242                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
5243                 /* SEL_SCIF0 [3] */
5244                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
5245                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
5246                 0, 0, 0,
5247                 /* RESEVED [1] */
5248                 0, 0,
5249                 /* SEL_SCIF [1] */
5250                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
5251                 /* SEL_CAN0 [3] */
5252                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5253                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
5254                 0, 0,
5255                 /* SEL_CAN1 [2] */
5256                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5257                 /* RESEVED [1] */
5258                 0, 0,
5259                 /* SEL_SCIFA2 [1] */
5260                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5261                 /* SEL_SCIF4 [2] */
5262                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
5263                 /* RESEVED [2] */
5264                 0, 0, 0, 0,
5265                 /* SEL_ADG [1] */
5266                 FN_SEL_ADG_0, FN_SEL_ADG_1,
5267                 /* SEL_FM [3] */
5268                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
5269                 FN_SEL_FM_3, FN_SEL_FM_4,
5270                 0, 0, 0,
5271                 /* SEL_SCIFA5 [2] */
5272                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
5273                 /* RESEVED [1] */
5274                 0, 0,
5275                 /* SEL_GPS [2] */
5276                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
5277                 /* SEL_SCIFA4 [2] */
5278                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
5279                 /* SEL_SCIFA3 [2] */
5280                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
5281                 /* SEL_SIM [1] */
5282                 FN_SEL_SIM_0, FN_SEL_SIM_1,
5283                 /* RESEVED [1] */
5284                 0, 0,
5285                 /* SEL_SSI8 [1] */
5286                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
5287         },
5288         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5289                              2, 2, 2, 2, 2, 2, 2, 2,
5290                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
5291                 /* SEL_HSCIF2 [2] */
5292                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
5293                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
5294                 /* SEL_CANCLK [2] */
5295                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5296                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
5297                 /* SEL_IIC8 [2] */
5298                 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
5299                 /* SEL_IIC7 [2] */
5300                 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
5301                 /* SEL_IIC4 [2] */
5302                 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
5303                 /* SEL_IIC3 [2] */
5304                 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
5305                 /* SEL_SCIF3 [2] */
5306                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
5307                 /* SEL_IEB [2] */
5308                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5309                 /* SEL_MMC [1] */
5310                 FN_SEL_MMC_0, FN_SEL_MMC_1,
5311                 /* SEL_SCIF5 [1] */
5312                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
5313                 /* RESEVED [2] */
5314                 0, 0, 0, 0,
5315                 /* SEL_IIC2 [2] */
5316                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5317                 /* SEL_IIC1 [3] */
5318                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
5319                 FN_SEL_IIC1_4,
5320                 0, 0, 0,
5321                 /* SEL_IIC0 [2] */
5322                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
5323                 /* RESEVED [2] */
5324                 0, 0, 0, 0,
5325                 /* RESEVED [2] */
5326                 0, 0, 0, 0,
5327                 /* RESEVED [1] */
5328                 0, 0, }
5329         },
5330         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
5331                              3, 2, 2, 1, 1, 1, 1, 3, 2,
5332                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
5333                 /* SEL_SOF1 [3] */
5334                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
5335                 FN_SEL_SOF1_4,
5336                 0, 0, 0,
5337                 /* SEL_HSCIF0 [2] */
5338                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
5339                 /* SEL_DIS [2] */
5340                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
5341                 /* RESEVED [1] */
5342                 0, 0,
5343                 /* SEL_RAD [1] */
5344                 FN_SEL_RAD_0, FN_SEL_RAD_1,
5345                 /* SEL_RCN [1] */
5346                 FN_SEL_RCN_0, FN_SEL_RCN_1,
5347                 /* SEL_RSP [1] */
5348                 FN_SEL_RSP_0, FN_SEL_RSP_1,
5349                 /* SEL_SCIF2 [3] */
5350                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
5351                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
5352                 0, 0, 0,
5353                 /* RESEVED [2] */
5354                 0, 0, 0, 0,
5355                 /* RESEVED [2] */
5356                 0, 0, 0, 0,
5357                 /* SEL_SOF2 [3] */
5358                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
5359                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
5360                 0, 0, 0,
5361                 /* RESEVED [1] */
5362                 0, 0,
5363                 /* SEL_SSI1 [1] */
5364                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5365                 /* SEL_SSI0 [1] */
5366                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
5367                 /* SEL_SSP [2] */
5368                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
5369                 /* RESEVED [2] */
5370                 0, 0, 0, 0,
5371                 /* RESEVED [2] */
5372                 0, 0, 0, 0,
5373                 /* RESEVED [2] */
5374                 0, 0, 0, 0, }
5375         },
5376         { },
5377 };
5378
5379 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
5380         .name = "r8a77910_pfc",
5381         .unlock_reg = 0xe6060000, /* PMMR */
5382
5383         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5384
5385         .pins = pinmux_pins,
5386         .nr_pins = ARRAY_SIZE(pinmux_pins),
5387         .groups = pinmux_groups,
5388         .nr_groups = ARRAY_SIZE(pinmux_groups),
5389         .functions = pinmux_functions,
5390         .nr_functions = ARRAY_SIZE(pinmux_functions),
5391
5392         .cfg_regs = pinmux_config_regs,
5393
5394         .gpio_data = pinmux_data,
5395         .gpio_data_size = ARRAY_SIZE(pinmux_data),
5396 };