drivers/pinctrl/sh-pfc/pfc-r8a7790.c

   1 /*
   2  * R8A7790 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Electronics Corporation
   5  * Copyright (C) 2013  Magnus Damm
   6  * Copyright (C) 2012  Renesas Solutions Corp.
   7  * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/platform_data/gpio-rcar.h>
  26
  27 #include "core.h"
  28 #include "sh_pfc.h"
  29
  30 #define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
  31
  32 #define PORT_GP_32(bank, fn, sfx)                                       \
  33         PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
  34         PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
  35         PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
  36         PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
  37         PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
  38         PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
  39         PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
  40         PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
  41         PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
  42         PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
  43         PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
  44         PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
  45         PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
  46         PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
  47         PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
  48         PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
  49
  50 #define PORT_GP_32_REV(bank, fn, sfx)                                   \
  51         PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
  52         PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
  53         PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
  54         PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
  55         PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
  56         PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
  57         PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
  58         PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
  59         PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
  60         PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
  61         PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
  62         PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
  63         PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
  64         PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
  65         PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
  66         PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
  67
  68 #define CPU_ALL_PORT(fn, sfx)                                           \
  69         PORT_GP_32(0, fn, sfx),                                         \
  70         PORT_GP_32(1, fn, sfx),                                         \
  71         PORT_GP_32(2, fn, sfx),                                         \
  72         PORT_GP_32(3, fn, sfx),                                         \
  73         PORT_GP_32(4, fn, sfx),                                         \
  74         PORT_GP_32(5, fn, sfx)
  75
  76 #define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
  77
  78 #define _GP_GPIO(bank, pin, _name, sfx)                                 \
  79         [(bank * 32) + pin] = {                                         \
  80                 .name = __stringify(_name),                             \
  81                 .enum_id = _name##_DATA,                                \
  82         }
  83
  84 #define _GP_DATA(bank, pin, name, sfx)                                  \
  85         PINMUX_DATA(name##_DATA, name##_FN)
  86
  87 #define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
  88 #define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
  89 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
  90
  91 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
  92 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
  93                                                           FN_##ipsr, FN_##fn)
  94
  95 enum {
  96         PINMUX_RESERVED = 0,
  97
  98         PINMUX_DATA_BEGIN,
  99         GP_ALL(DATA),
 100         PINMUX_DATA_END,
 101
 102         PINMUX_FUNCTION_BEGIN,
 103         GP_ALL(FN),
 104
 105         /* GPSR0 */
 106         FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
 107         FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
 108         FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
 109         FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
 110         FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
 111         FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
 112         FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
 113         FN_IP3_14_12, FN_IP3_17_15,
 114
 115         /* GPSR1 */
 116         FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
 117         FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
 118         FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
 119         FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
 120         FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
 121         FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
 122         FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
 123
 124         /* GPSR2 */
 125         FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
 126         FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
 127         FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
 128         FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
 129         FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
 130         FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
 131         FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
 132
 133         /* GPSR3 */
 134         FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
 135         FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
 136         FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
 137         FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
 138         FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
 139         FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
 140         FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
 141
 142         /* GPSR4 */
 143         FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
 144         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
 145         FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
 146         FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
 147         FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
 148         FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
 149         FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
 150         FN_IP14_15_12, FN_IP14_18_16,
 151
 152         /* GPSR5 */
 153         FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
 154         FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
 155         FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
 156         FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
 157         FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
 158         FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
 159         FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
 160
 161         /* IPSR0 */
 162         FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
 163         FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
 164         FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
 165         FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
 166         FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
 167         FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
 168         FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
 169         FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
 170         FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
 171         FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
 172         FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
 173         FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
 174         FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
 175         FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
 176
 177         /* IPSR1 */
 178         FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
 179         FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
 180         FN_SCIFA1_TXD_C, FN_AVB_TXD2,
 181         FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
 182         FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
 183         FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
 184         FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
 185         FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
 186         FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
 187         FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
 188         FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
 189         FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
 190         FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
 191         FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
 192         FN_A0, FN_PWM3, FN_A1, FN_PWM4,
 193
 194         /* IPSR2 */
 195         FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
 196         FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
 197         FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
 198         FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
 199         FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
 200         FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
 201         FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
 202         FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
 203         FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
 204         FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
 205         FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
 206
 207         /* IPSR3 */
 208         FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
 209         FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
 210         FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
 211         FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
 212         FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
 213         FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
 214         FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
 215         FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
 216         FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
 217         FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
 218         FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
 219         FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
 220         FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
 221
 222         /* IPSR4 */
 223         FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
 224         FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
 225         FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
 226         FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
 227         FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
 228         FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
 229         FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
 230         FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
 231         FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
 232         FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
 233         FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
 234         FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
 235         FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
 236         FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
 237         FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
 238
 239         /* IPSR5 */
 240         FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
 241         FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
 242         FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
 243         FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
 244         FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
 245         FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
 246         FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
 247         FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
 248         FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
 249         FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
 250         FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
 251         FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
 252         FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
 253         FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
 254         FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
 255         FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
 256         FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
 257         FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
 258         FN_SSI_WS78_B,
 259
 260         /* IPSR6 */
 261         FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
 262         FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
 263         FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
 264         FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
 265         FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
 266         FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
 267         FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
 268         FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
 269         FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
 270         FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
 271         FN_I2C2_SCL_E, FN_ETH_RX_ER,
 272         FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
 273         FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
 274         FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
 275         FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
 276         FN_HRX0_E, FN_STP_ISSYNC_0_B,
 277         FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
 278         FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
 279         FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
 280         FN_ETH_REF_CLK, FN_HCTS0_N_E,
 281         FN_STP_IVCXO27_1_B, FN_HRX0_F,
 282
 283         /* IPSR7 */
 284         FN_ETH_MDIO, FN_HRTS0_N_E,
 285         FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
 286         FN_HTX0_F, FN_BPFCLK_G,
 287         FN_ETH_TX_EN, FN_SIM0_CLK_C,
 288         FN_HRTS0_N_F, FN_ETH_MAGIC,
 289         FN_SIM0_RST_C, FN_ETH_TXD0,
 290         FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
 291         FN_ETH_MDC, FN_STP_ISD_1_B,
 292         FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
 293         FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
 294         FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
 295         FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
 296         FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
 297         FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
 298         FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
 299         FN_ATACS00_N, FN_AVB_RXD1,
 300         FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
 301
 302         /* IPSR8 */
 303         FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
 304         FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
 305         FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
 306         FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
 307         FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
 308         FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
 309         FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
 310         FN_VI1_CLK, FN_AVB_RX_DV,
 311         FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
 312         FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
 313         FN_SCIFA1_RXD_D, FN_AVB_MDC,
 314         FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
 315         FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
 316         FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
 317         FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
 318         FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
 319         FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
 320         FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
 321
 322         /* IPSR9 */
 323         FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
 324         FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
 325         FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
 326         FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
 327         FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
 328         FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
 329         FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
 330         FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
 331         FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
 332         FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
 333         FN_AVB_TX_EN, FN_SD1_CMD,
 334         FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
 335         FN_SD1_DAT0, FN_AVB_TX_CLK,
 336         FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
 337         FN_SCIFB0_TXD_B, FN_SD1_DAT2,
 338         FN_AVB_COL, FN_SCIFB0_CTS_N_B,
 339         FN_SD1_DAT3, FN_AVB_RXD0,
 340         FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
 341         FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
 342         FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
 343         FN_VI3_CLK_B,
 344
 345         /* IPSR10 */
 346         FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
 347         FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
 348         FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
 349         FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
 350         FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
 351         FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
 352         FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
 353         FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
 354         FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
 355         FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
 356         FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
 357         FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
 358         FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
 359         FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
 360         FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
 361         FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
 362         FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
 363         FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
 364         FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
 365         FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
 366         FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
 367         FN_GLO_I0_B, FN_VI3_DATA6_B,
 368
 369         /* IPSR11 */
 370         FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
 371         FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
 372         FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
 373         FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
 374         FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
 375         FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
 376         FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
 377         FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
 378         FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
 379         FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
 380         FN_FMIN_E, FN_FMIN_F,
 381         FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
 382         FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
 383         FN_I2C2_SDA_B, FN_MLB_DAT,
 384         FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
 385         FN_SSI_SCK0129, FN_CAN_CLK_B,
 386         FN_MOUT0,
 387
 388         /* IPSR12 */
 389         FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
 390         FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
 391         FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
 392         FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
 393         FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
 394         FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
 395         FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
 396         FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
 397         FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
 398         FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
 399         FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
 400         FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
 401         FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
 402         FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
 403         FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
 404         FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
 405         FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
 406         FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
 407         FN_CAN_DEBUGOUT4,
 408
 409         /* IPSR13 */
 410         FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
 411         FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
 412         FN_SCIFB1_CTS_N, FN_BPFCLK_D,
 413         FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
 414         FN_BPFCLK_F, FN_SSI_WS6,
 415         FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
 416         FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
 417         FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
 418         FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
 419         FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
 420         FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
 421         FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
 422         FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
 423         FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
 424         FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
 425         FN_BPFCLK_E, FN_SSI_SDATA7_B,
 426         FN_FMIN_G, FN_SSI_SDATA8,
 427         FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
 428         FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
 429         FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
 430         FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
 431         FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
 432
 433         /* IPSR14 */
 434         FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
 435         FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
 436         FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
 437         FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
 438         FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
 439         FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
 440         FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
 441         FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
 442         FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
 443         FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
 444         FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
 445         FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
 446         FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
 447         FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
 448         FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
 449         FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
 450         FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
 451         FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
 452         FN_HRTS0_N_C,
 453
 454         /* IPSR15 */
 455         FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
 456         FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
 457         FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
 458         FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
 459         FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
 460         FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
 461         FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
 462         FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
 463         FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
 464         FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
 465         FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
 466         FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
 467         FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
 468         FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
 469         FN_DU2_DG6, FN_LCDOUT14,
 470
 471         /* IPSR16 */
 472         FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
 473         FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
 474         FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
 475         FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
 476         FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
 477         FN_TCLK1_B,
 478
 479         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 480         FN_SEL_SCIF1_4,
 481         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
 482         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
 483         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 484         FN_SEL_SCIFB1_4,
 485         FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
 486         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
 487         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
 488         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 489         FN_SEL_SOF1_0, FN_SEL_SOF1_1,
 490         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 491         FN_SEL_SSI6_0, FN_SEL_SSI6_1,
 492         FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
 493         FN_SEL_VI3_0, FN_SEL_VI3_1,
 494         FN_SEL_VI2_0, FN_SEL_VI2_1,
 495         FN_SEL_VI1_0, FN_SEL_VI1_1,
 496         FN_SEL_VI0_0, FN_SEL_VI0_1,
 497         FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
 498         FN_SEL_LBS_0, FN_SEL_LBS_1,
 499         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 500         FN_SEL_SOF3_0, FN_SEL_SOF3_1,
 501         FN_SEL_SOF0_0, FN_SEL_SOF0_1,
 502
 503         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 504         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 505         FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
 506         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 507         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
 508         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
 509         FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 510         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
 511         FN_SEL_ADI_0, FN_SEL_ADI_1,
 512         FN_SEL_SSP_0, FN_SEL_SSP_1,
 513         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
 514         FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
 515         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
 516         FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
 517         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
 518         FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
 519         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 520
 521         FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
 522         FN_SEL_IIC0_0, FN_SEL_IIC0_1,
 523         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 524         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 525         FN_SEL_IIC2_4,
 526         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 527         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 528         FN_SEL_I2C2_4,
 529         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
 530         PINMUX_FUNCTION_END,
 531
 532         PINMUX_MARK_BEGIN,
 533
 534         VI1_DATA7_VI1_B7_MARK,
 535
 536         USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
 537         USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
 538         DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
 539
 540         D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
 541         D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
 542         VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
 543         VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
 544         VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
 545         SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
 546         VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
 547         SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
 548         VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
 549         IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
 550         I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
 551         VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
 552         D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
 553         VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
 554
 555         D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
 556         VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
 557         SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
 558         VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
 559         SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
 560         VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
 561         D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
 562         VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
 563         D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
 564         VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
 565         SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
 566         VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
 567         D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
 568         VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
 569         A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
 570
 571         A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
 572         PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
 573         TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
 574         A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
 575         SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
 576         A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
 577         VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
 578         A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
 579         VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
 580         A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
 581         VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
 582
 583         A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
 584         VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
 585         A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
 586         VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
 587         A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
 588         MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
 589         VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
 590         ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
 591         ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
 592         A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
 593         AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
 594         ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
 595         VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
 596
 597         A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
 598         A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
 599         VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
 600         VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
 601         VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
 602         VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
 603         VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
 604         VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
 605         CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
 606         VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
 607         VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
 608         MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
 609         HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
 610         VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
 611         VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
 612
 613         EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
 614         VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
 615         EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
 616         VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
 617         INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
 618         MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
 619         VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
 620         I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
 621         CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
 622         CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
 623         VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
 624         INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
 625         VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
 626         WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
 627         VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
 628         IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
 629         VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
 630         MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
 631         VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
 632         SSI_WS78_B_MARK,
 633
 634         DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
 635         VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
 636         DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
 637         SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
 638         INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
 639         DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
 640         MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
 641         SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
 642         ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
 643         TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
 644         I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
 645         STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
 646         IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
 647         STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
 648         SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
 649         HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
 650         TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
 651         RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
 652         STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
 653         ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
 654         STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
 655
 656         ETH_MDIO_MARK, HRTS0_N_E_MARK,
 657         SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
 658         HTX0_F_MARK, BPFCLK_G_MARK,
 659         ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
 660         HRTS0_N_F_MARK, ETH_MAGIC_MARK,
 661         SIM0_RST_C_MARK, ETH_TXD0_MARK,
 662         STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
 663         ETH_MDC_MARK, STP_ISD_1_B_MARK,
 664         TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
 665         SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
 666         GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
 667         STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
 668         PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
 669         PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
 670         AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
 671         ATACS00_N_MARK, AVB_RXD1_MARK,
 672         VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
 673
 674         VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
 675         VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
 676         AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
 677         AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
 678         AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
 679         AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
 680         VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
 681         VI1_CLK_MARK, AVB_RX_DV_MARK,
 682         VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
 683         AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
 684         SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
 685         VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
 686         VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
 687         AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
 688         AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
 689         AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
 690         SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
 691         SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
 692
 693         SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
 694         SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
 695         SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
 696         SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
 697         SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
 698         GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
 699         I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
 700         MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
 701         GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
 702         I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
 703         AVB_TX_EN_MARK, SD1_CMD_MARK,
 704         AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
 705         SD1_DAT0_MARK, AVB_TX_CLK_MARK,
 706         SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
 707         SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
 708         AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
 709         SD1_DAT3_MARK, AVB_RXD0_MARK,
 710         SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
 711         TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
 712         IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
 713         VI3_CLK_B_MARK,
 714
 715         SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
 716         GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
 717         SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
 718         VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
 719         VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
 720         VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
 721         TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
 722         SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
 723         VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
 724         TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
 725         SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
 726         VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
 727         TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
 728         SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
 729         VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
 730         GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
 731         MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
 732         HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
 733         VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
 734         TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
 735         VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
 736         GLO_I0_B_MARK, VI3_DATA6_B_MARK,
 737
 738         SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
 739         GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
 740         TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
 741         SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
 742         MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
 743         SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
 744         MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
 745         SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
 746         VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
 747         MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
 748         FMIN_E_MARK, FMIN_F_MARK,
 749         MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
 750         MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
 751         I2C2_SDA_B_MARK, MLB_DAT_MARK,
 752         SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
 753         SSI_SCK0129_MARK, CAN_CLK_B_MARK,
 754         MOUT0_MARK,
 755
 756         SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
 757         SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
 758         SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
 759         SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
 760         SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
 761         MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
 762         STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
 763         CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
 764         SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
 765         SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
 766         MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
 767         SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
 768         MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
 769         SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
 770         CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
 771         IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
 772         CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
 773         IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
 774         CAN_DEBUGOUT4_MARK,
 775
 776         SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
 777         LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
 778         SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
 779         DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
 780         BPFCLK_F_MARK, SSI_WS6_MARK,
 781         SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
 782         LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
 783         FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
 784         CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
 785         SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
 786         CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
 787         SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
 788         LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
 789         STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
 790         TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
 791         BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
 792         FMIN_G_MARK, SSI_SDATA8_MARK,
 793         STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
 794         CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
 795         STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
 796         SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
 797         SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
 798
 799         AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
 800         DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
 801         REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
 802         MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
 803         I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
 804         DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
 805         TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
 806         HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
 807         LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
 808         SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
 809         MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
 810         SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
 811         DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 812         SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
 813         LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
 814         CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
 815         SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
 816         MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
 817         HRTS0_N_C_MARK,
 818
 819         SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
 820         LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
 821         TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
 822         SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
 823         IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
 824         DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
 825         DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
 826         LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
 827         LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
 828         LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
 829         DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
 830         SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
 831         HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
 832         DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
 833         DU2_DG6_MARK, LCDOUT14_MARK,
 834
 835         MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
 836         DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
 837         MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
 838         ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
 839         USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
 840         TCLK1_B_MARK,
 841         PINMUX_MARK_END,
 842 };
 843
 844 static const pinmux_enum_t pinmux_data[] = {
 845         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 846
 847         PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
 848         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 849         PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
 850         PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
 851         PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
 852         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 853         PINMUX_DATA(AVS2_MARK, FN_AVS2),
 854         PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
 855         PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
 856
 857         PINMUX_IPSR_DATA(IP0_2_0, D0),
 858         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
 859         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
 860         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
 861         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
 862         PINMUX_IPSR_DATA(IP0_5_3, D1),
 863         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
 864         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
 865         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
 866         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
 867         PINMUX_IPSR_DATA(IP0_8_6, D2),
 868         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
 869         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
 870         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
 871         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
 872         PINMUX_IPSR_DATA(IP0_11_9, D3),
 873         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
 874         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
 875         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
 876         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
 877         PINMUX_IPSR_DATA(IP0_15_12, D4),
 878         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
 879         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
 880         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
 881         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
 882         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
 883         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
 884         PINMUX_IPSR_DATA(IP0_19_16, D5),
 885         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
 886         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
 887         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
 888         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
 889         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
 890         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
 891         PINMUX_IPSR_DATA(IP0_22_20, D6),
 892         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
 893         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
 894         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
 895         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
 896         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
 897         PINMUX_IPSR_DATA(IP0_26_23, D7),
 898         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
 899         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
 900         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
 901         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
 902         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
 903         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
 904         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
 905         PINMUX_IPSR_DATA(IP0_30_27, D8),
 906         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
 907         PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
 908         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
 909         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
 910         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
 911
 912         PINMUX_IPSR_DATA(IP1_3_0, D9),
 913         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
 914         PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
 915         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
 916         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
 917         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
 918         PINMUX_IPSR_DATA(IP1_7_4, D10),
 919         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
 920         PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
 921         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
 922         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
 923         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
 924         PINMUX_IPSR_DATA(IP1_11_8, D11),
 925         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
 926         PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
 927         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
 928         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
 929         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
 930         PINMUX_IPSR_DATA(IP1_14_12, D12),
 931         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
 932         PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
 933         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
 934         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
 935         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
 936         PINMUX_IPSR_DATA(IP1_17_15, D13),
 937         PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
 938         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
 939         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
 940         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
 941         PINMUX_IPSR_DATA(IP1_21_18, D14),
 942         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
 943         PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
 944         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
 945         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
 946         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
 947         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
 948         PINMUX_IPSR_DATA(IP1_25_22, D15),
 949         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
 950         PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
 951         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
 952         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
 953         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
 954         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
 955         PINMUX_IPSR_DATA(IP1_27_26, A0),
 956         PINMUX_IPSR_DATA(IP1_27_26, PWM3),
 957         PINMUX_IPSR_DATA(IP1_29_28, A1),
 958         PINMUX_IPSR_DATA(IP1_29_28, PWM4),
 959
 960         PINMUX_IPSR_DATA(IP2_2_0, A2),
 961         PINMUX_IPSR_DATA(IP2_2_0, PWM5),
 962         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
 963         PINMUX_IPSR_DATA(IP2_5_3, A3),
 964         PINMUX_IPSR_DATA(IP2_5_3, PWM6),
 965         PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
 966         PINMUX_IPSR_DATA(IP2_8_6, A4),
 967         PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
 968         PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
 969         PINMUX_IPSR_DATA(IP2_11_9, A5),
 970         PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
 971         PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
 972         PINMUX_IPSR_DATA(IP2_14_12, A6),
 973         PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
 974         PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
 975         PINMUX_IPSR_DATA(IP2_17_15, A7),
 976         PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
 977         PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
 978         PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
 979         PINMUX_IPSR_DATA(IP2_21_18, A8),
 980         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
 981         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
 982         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
 983         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
 984         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
 985         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
 986         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
 987         PINMUX_IPSR_DATA(IP2_25_22, A9),
 988         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
 989         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
 990         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
 991         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
 992         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
 993         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
 994         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
 995         PINMUX_IPSR_DATA(IP2_28_26, A10),
 996         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
 997         PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
 998         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
 999         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
1000         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
1001
1002         PINMUX_IPSR_DATA(IP3_3_0, A11),
1003         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1004         PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
1005         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
1006         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
1007         PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
1008         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
1009         PINMUX_IPSR_DATA(IP3_7_4, A12),
1010         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
1011         PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
1012         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
1013         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
1014         PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
1015         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
1016         PINMUX_IPSR_DATA(IP3_11_8, A13),
1017         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1018         PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
1019         PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
1020         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
1021         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
1022         PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
1023         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
1024         PINMUX_IPSR_DATA(IP3_14_12, A14),
1025         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
1026         PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
1027         PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
1028         PINMUX_IPSR_DATA(IP3_17_15, A15),
1029         PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
1030         PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
1031         PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
1032         PINMUX_IPSR_DATA(IP3_19_18, A16),
1033         PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
1034         PINMUX_IPSR_DATA(IP3_22_20, A17),
1035         PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
1036         PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
1037         PINMUX_IPSR_DATA(IP3_25_23, A18),
1038         PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
1039         PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
1040         PINMUX_IPSR_DATA(IP3_28_26, A19),
1041         PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
1042         PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
1043         PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
1044         PINMUX_IPSR_DATA(IP3_31_29, A20),
1045         PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
1046         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
1047         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
1048         PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
1049
1050         PINMUX_IPSR_DATA(IP4_2_0, A21),
1051         PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
1052         PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
1053         PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1054         PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1055         PINMUX_IPSR_DATA(IP4_5_3, A22),
1056         PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1057         PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1058         PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1059         PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1060         PINMUX_IPSR_DATA(IP4_8_6, A23),
1061         PINMUX_IPSR_DATA(IP4_8_6, IO2),
1062         PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1063         PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1064         PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1065         PINMUX_IPSR_DATA(IP4_11_9, A24),
1066         PINMUX_IPSR_DATA(IP4_11_9, IO3),
1067         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1068         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1069         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1070         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1071         PINMUX_IPSR_DATA(IP4_14_12, A25),
1072         PINMUX_IPSR_DATA(IP4_14_12, SSL),
1073         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1074         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1075         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1076         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1077         PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1078         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1079         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1080         PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1081         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1082         PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1083         PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1084         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1085         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1086         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1087         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1088         PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1089         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1090         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1091         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1092         PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1093         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1094         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1095         PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1096         PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1097         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1098         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1099         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1100         PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1101         PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1102         PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1103         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1104         PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1105         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1106         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1107         PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1108
1109         PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1110         PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1111         PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1112         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1113         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1114         PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1115         PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
1116         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1117         PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1118         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1119         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1120         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1121         PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1122         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1123         PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1124         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1125         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1126         PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1127         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1128         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1129         PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1130         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1131         PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1132         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1133         PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1134         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1135         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1136         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1137         PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1138         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1139         PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1140         PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1141         PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1142         PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1143         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1144         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1145         PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1146         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1147         PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1148         PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1149         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1150         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1151         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1152         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1153         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1154         PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1155         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1156         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1157         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1158         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1159         PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1160         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1161         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
1162         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1163         PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1164         PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1165         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1166         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1167         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1168         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1169         PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1170         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1171         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1172         PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1173         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1174         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1175
1176         PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1177         PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1178         PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1179         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1180         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1181         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1182         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1183         PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1184         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1185         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1186         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1187         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1188         PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1189         PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1190         PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1191         PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1192         PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1193         PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1194         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1195         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1196         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1197         PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1198         PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1199         PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1200         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1201         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1202         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1203         PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1204         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1205         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1206         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1207         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1208         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1209         PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1210         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1211         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1212         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1213         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1214         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1215         PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1216         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1217         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1218         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1219         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1220         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1221         PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1222         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1223         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1224         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1225         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1226         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1227         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1228         PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1229         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1230         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1231         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1232         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1233         PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1234         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1235         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1236         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1237
1238         PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1239         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1240         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1241         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1242         PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1243         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1244         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
1245         PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1246         PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1247         PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1248         PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1249         PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1250         PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1251         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1252         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1253         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1254         PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1255         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1256         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1257         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1258         PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1259         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1260         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1261         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1262         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1263         PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1264         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1265         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1266         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1267         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1268         PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1269         PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1270         PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1271         PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1272         PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1273         PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
1274         PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
1275         PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1276         PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1277         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1278         PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1279         PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1280         PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1281         PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1282         PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1283
1284         PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1285         PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1286         PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1287         PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1288         PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1289         PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1290         PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1291         PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1292         PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1293         PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1294         PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1295         PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1296         PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1297         PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1298         PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1299         PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1300         PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1301         PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1302         PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1303         PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1304         PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1305         PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1306         PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1307         PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1308         PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1309         PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1310         PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1311         PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1312         PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1313         PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1314         PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1315         PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1316         PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1317         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1318         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1319         PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1320         PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1321         PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
1322         PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1323         PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1324         PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1325         PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1326         PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1327         PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1328         PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1329
1330         PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1331         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1332         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1333         PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1334         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1335         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1336         PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1337         PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1338         PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1339         PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1340         PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1341         PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1342         PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1343         PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1344         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1345         PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1346         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1347         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1348         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1349         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1350         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1351         PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1352         PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1353         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1354         PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1355         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1356         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1357         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1358         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1359         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1360         PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1361         PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1362         PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1363         PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1364         PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1365         PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1366         PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1367         PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1368         PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1369         PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1370         PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1371         PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1372         PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1373         PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1374         PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1375         PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1376         PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1377         PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1378         PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1379         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1380         PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1381         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1382         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1383         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1384         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1385         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1386         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1387
1388         PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1389         PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1390         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1391         PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1392         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1393         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1394         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1395         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1396         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1397         PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1398         PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1399         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1400         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1401         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1402         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1403         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1404         PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1405         PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1406         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1407         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1408         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1409         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1410         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1411         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1412         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1413         PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1414         PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1415         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1416         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1417         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1418         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1419         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1420         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1421         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1422         PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1423         PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1424         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
1425         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1426         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1427         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1428         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1429         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1430         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1431         PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1432         PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1433         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
1434         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1435         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1436         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1437         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1438         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1439         PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1440         PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1441         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1442         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1443         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1444         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1445         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1446         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1447         PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1448         PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1449         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1450         PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1451         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1452         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1453         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1454         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1455         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1456         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1457
1458         PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1459         PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1460         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1461         PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1462         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1463         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1464         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1465         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1466         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1467         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1468         PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1469         PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1470         PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1471         PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1472         PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1473         PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1474         PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1475         PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1476         PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1477         PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1478         PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1479         PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1480         PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1481         PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1482         PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1483         PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1484         PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1485         PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1486         PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1487         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1488         PINMUX_IPSR_DATA(IP11_17_15, VSP),
1489         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1490         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1491         PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1492         PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1493         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1494         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1495         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
1496         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
1497         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
1498         PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1499         PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1500         PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1501         PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1502         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1503         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
1504         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1505         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1506         PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1507         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1508         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1509         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
1510         PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1511         PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1512         PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1513
1514         PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1515         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1516         PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1517         PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1518         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1519         PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1520         PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1521         PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1522         PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1523         PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1524         PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1525         PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
1526         PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1527         PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1528         PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1529         PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1530         PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1531         PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1532         PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1533         PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1534         PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1535         PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1536         PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1537         PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1538         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1539         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1540         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1541         PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1542         PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1543         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1544         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1545         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1546         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1547         PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1548         PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1549         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1550         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1551         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1552         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1553         PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1554         PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1555         PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1556         PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1557         PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1558         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1559         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1560         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1561         PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1562         PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1563         PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1564         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1565         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1566         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1567         PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1568         PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1569         PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1570
1571         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1572         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1573         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1574         PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1575         PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1576         PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1577         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1578         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1579         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
1580         PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1581         PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1582         PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1583         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
1584         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1585         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1586         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1587         PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1588         PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1589         PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1590         PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1591         PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
1592         PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1593         PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1594         PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1595         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1596         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1597         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1598         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1599         PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1600         PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1601         PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1602         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1603         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1604         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1605         PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1606         PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1607         PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1608         PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1609         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1610         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1611         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1612         PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1613         PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1614         PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1615         PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1616         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
1617         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1618         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
1619         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1620         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1621         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1622         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1623         PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1624         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1625         PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1626         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1627         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1628         PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1629         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1630         PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1631         PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1632         PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1633         PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1634
1635         PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1636         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1637         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1638         PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1639         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1640         PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1641         PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1642         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1643         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1644         PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1645         PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1646         PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1647         PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1648         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1649         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1650         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1651         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1652         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1653         PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1654         PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1655         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1656         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1657         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1658         PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1659         PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1660         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1661         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1662         PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
1663         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1664         PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1665         PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1666         PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
1667         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1668         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1669         PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1670         PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1671         PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
1672         PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1673         PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1674         PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1675         PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1676         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1677         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1678         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1679         PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1680         PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1681         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1682         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1683         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1684         PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1685         PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1686         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1687         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1688         PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1689         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1690         PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1691         PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1692         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1693         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1694         PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
1695         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1696         PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1697         PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1698         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1699
1700         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1701         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1702         PINMUX_IPSR_DATA(IP15_2_0, SCK2),
1703         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1704         PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1705         PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1706         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1707         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1708         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1709         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
1710         PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1711         PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1712         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1713         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1714         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1715         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1716         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
1717         PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1718         PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1719         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1720         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1721         PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1722         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1723         PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1724         PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1725         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1726         PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1727         PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1728         PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1729         PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1730         PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1731         PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1732         PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1733         PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1734         PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1735         PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1736         PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1737         PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1738         PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1739         PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1740         PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1741         PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1742         PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1743         PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1744         PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1745         PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1746         PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1747         PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1748         PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1749         PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1750         PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1751         PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1752         PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1753         PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1754         PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1755         PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1756         PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1757         PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1758         PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1759         PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1760
1761         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1762         PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1763         PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1764         PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1765         PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1766         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1767         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1768         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1769         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1770         PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1771         PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1772         PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1773         PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1774         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1775         PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1776         PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1777         PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1778         PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1779 };
1780
1781 static struct sh_pfc_pin pinmux_pins[] = {
1782         PINMUX_GPIO_GP_ALL(),
1783 };
1784
1785 /* - ETH -------------------------------------------------------------------- */
1786 static const unsigned int eth_link_pins[] = {
1787         /* LINK */
1788         RCAR_GP_PIN(2, 22),
1789 };
1790 static const unsigned int eth_link_mux[] = {
1791         ETH_LINK_MARK,
1792 };
1793 static const unsigned int eth_magic_pins[] = {
1794         /* MAGIC */
1795         RCAR_GP_PIN(2, 27),
1796 };
1797 static const unsigned int eth_magic_mux[] = {
1798         ETH_MAGIC_MARK,
1799 };
1800 static const unsigned int eth_mdio_pins[] = {
1801         /* MDC, MDIO */
1802         RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1803 };
1804 static const unsigned int eth_mdio_mux[] = {
1805         ETH_MDC_MARK, ETH_MDIO_MARK,
1806 };
1807 static const unsigned int eth_rmii_pins[] = {
1808         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1809         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1810         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1811         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1812 };
1813 static const unsigned int eth_rmii_mux[] = {
1814         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1815         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1816 };
1817 /* - HSCIF0 ----------------------------------------------------------------- */
1818 static const unsigned int hscif0_data_pins[] = {
1819         /* RX, TX */
1820         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1821 };
1822 static const unsigned int hscif0_data_mux[] = {
1823         HRX0_MARK, HTX0_MARK,
1824 };
1825 static const unsigned int hscif0_clk_pins[] = {
1826         /* SCK */
1827         RCAR_GP_PIN(5, 7),
1828 };
1829 static const unsigned int hscif0_clk_mux[] = {
1830         HSCK0_MARK,
1831 };
1832 static const unsigned int hscif0_ctrl_pins[] = {
1833         /* RTS, CTS */
1834         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1835 };
1836 static const unsigned int hscif0_ctrl_mux[] = {
1837         HRTS0_N_MARK, HCTS0_N_MARK,
1838 };
1839 static const unsigned int hscif0_data_b_pins[] = {
1840         /* RX, TX */
1841         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
1842 };
1843 static const unsigned int hscif0_data_b_mux[] = {
1844         HRX0_B_MARK, HTX0_B_MARK,
1845 };
1846 static const unsigned int hscif0_ctrl_b_pins[] = {
1847         /* RTS, CTS */
1848         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
1849 };
1850 static const unsigned int hscif0_ctrl_b_mux[] = {
1851         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1852 };
1853 static const unsigned int hscif0_data_c_pins[] = {
1854         /* RX, TX */
1855         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
1856 };
1857 static const unsigned int hscif0_data_c_mux[] = {
1858         HRX0_C_MARK, HTX0_C_MARK,
1859 };
1860 static const unsigned int hscif0_ctrl_c_pins[] = {
1861         /* RTS, CTS */
1862         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
1863 };
1864 static const unsigned int hscif0_ctrl_c_mux[] = {
1865         HRTS0_N_C_MARK, HCTS0_N_C_MARK,
1866 };
1867 static const unsigned int hscif0_data_d_pins[] = {
1868         /* RX, TX */
1869         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1870 };
1871 static const unsigned int hscif0_data_d_mux[] = {
1872         HRX0_D_MARK, HTX0_D_MARK,
1873 };
1874 static const unsigned int hscif0_ctrl_d_pins[] = {
1875         /* RTS, CTS */
1876         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
1877 };
1878 static const unsigned int hscif0_ctrl_d_mux[] = {
1879         HRTS0_N_D_MARK, HCTS0_N_D_MARK,
1880 };
1881 static const unsigned int hscif0_data_e_pins[] = {
1882         /* RX, TX */
1883         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1884 };
1885 static const unsigned int hscif0_data_e_mux[] = {
1886         HRX0_E_MARK, HTX0_E_MARK,
1887 };
1888 static const unsigned int hscif0_ctrl_e_pins[] = {
1889         /* RTS, CTS */
1890         RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1891 };
1892 static const unsigned int hscif0_ctrl_e_mux[] = {
1893         HRTS0_N_E_MARK, HCTS0_N_E_MARK,
1894 };
1895 static const unsigned int hscif0_data_f_pins[] = {
1896         /* RX, TX */
1897         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
1898 };
1899 static const unsigned int hscif0_data_f_mux[] = {
1900         HRX0_F_MARK, HTX0_F_MARK,
1901 };
1902 static const unsigned int hscif0_ctrl_f_pins[] = {
1903         /* RTS, CTS */
1904         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
1905 };
1906 static const unsigned int hscif0_ctrl_f_mux[] = {
1907         HRTS0_N_F_MARK, HCTS0_N_F_MARK,
1908 };
1909 /* - HSCIF1 ----------------------------------------------------------------- */
1910 static const unsigned int hscif1_data_pins[] = {
1911         /* RX, TX */
1912         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1913 };
1914 static const unsigned int hscif1_data_mux[] = {
1915         HRX1_MARK, HTX1_MARK,
1916 };
1917 static const unsigned int hscif1_clk_pins[] = {
1918         /* SCK */
1919         RCAR_GP_PIN(4, 27),
1920 };
1921 static const unsigned int hscif1_clk_mux[] = {
1922         HSCK1_MARK,
1923 };
1924 static const unsigned int hscif1_ctrl_pins[] = {
1925         /* RTS, CTS */
1926         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
1927 };
1928 static const unsigned int hscif1_ctrl_mux[] = {
1929         HRTS1_N_MARK, HCTS1_N_MARK,
1930 };
1931 static const unsigned int hscif1_data_b_pins[] = {
1932         /* RX, TX */
1933         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
1934 };
1935 static const unsigned int hscif1_data_b_mux[] = {
1936         HRX1_B_MARK, HTX1_B_MARK,
1937 };
1938 static const unsigned int hscif1_clk_b_pins[] = {
1939         /* SCK */
1940         RCAR_GP_PIN(1, 28),
1941 };
1942 static const unsigned int hscif1_clk_b_mux[] = {
1943         HSCK1_B_MARK,
1944 };
1945 static const unsigned int hscif1_ctrl_b_pins[] = {
1946         /* RTS, CTS */
1947         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1948 };
1949 static const unsigned int hscif1_ctrl_b_mux[] = {
1950         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1951 };
1952 /* - INTC ------------------------------------------------------------------- */
1953 static const unsigned int intc_irq0_pins[] = {
1954         /* IRQ */
1955         RCAR_GP_PIN(1, 25),
1956 };
1957 static const unsigned int intc_irq0_mux[] = {
1958         IRQ0_MARK,
1959 };
1960 static const unsigned int intc_irq1_pins[] = {
1961         /* IRQ */
1962         RCAR_GP_PIN(1, 27),
1963 };
1964 static const unsigned int intc_irq1_mux[] = {
1965         IRQ1_MARK,
1966 };
1967 static const unsigned int intc_irq2_pins[] = {
1968         /* IRQ */
1969         RCAR_GP_PIN(1, 29),
1970 };
1971 static const unsigned int intc_irq2_mux[] = {
1972         IRQ2_MARK,
1973 };
1974 static const unsigned int intc_irq3_pins[] = {
1975         /* IRQ */
1976         RCAR_GP_PIN(1, 23),
1977 };
1978 static const unsigned int intc_irq3_mux[] = {
1979         IRQ3_MARK,
1980 };
1981 /* - MMCIF0 ----------------------------------------------------------------- */
1982 static const unsigned int mmc0_data1_pins[] = {
1983         /* D[0] */
1984         RCAR_GP_PIN(3, 18),
1985 };
1986 static const unsigned int mmc0_data1_mux[] = {
1987         MMC0_D0_MARK,
1988 };
1989 static const unsigned int mmc0_data4_pins[] = {
1990         /* D[0:3] */
1991         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1992         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1993 };
1994 static const unsigned int mmc0_data4_mux[] = {
1995         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1996 };
1997 static const unsigned int mmc0_data8_pins[] = {
1998         /* D[0:7] */
1999         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2000         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2001         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2002         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2003 };
2004 static const unsigned int mmc0_data8_mux[] = {
2005         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2006         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2007 };
2008 static const unsigned int mmc0_ctrl_pins[] = {
2009         /* CLK, CMD */
2010         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2011 };
2012 static const unsigned int mmc0_ctrl_mux[] = {
2013         MMC0_CLK_MARK, MMC0_CMD_MARK,
2014 };
2015 /* - MMCIF1 ----------------------------------------------------------------- */
2016 static const unsigned int mmc1_data1_pins[] = {
2017         /* D[0] */
2018         RCAR_GP_PIN(3, 26),
2019 };
2020 static const unsigned int mmc1_data1_mux[] = {
2021         MMC1_D0_MARK,
2022 };
2023 static const unsigned int mmc1_data4_pins[] = {
2024         /* D[0:3] */
2025         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2026         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2027 };
2028 static const unsigned int mmc1_data4_mux[] = {
2029         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2030 };
2031 static const unsigned int mmc1_data8_pins[] = {
2032         /* D[0:7] */
2033         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2034         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2035         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2036         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2037 };
2038 static const unsigned int mmc1_data8_mux[] = {
2039         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2040         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2041 };
2042 static const unsigned int mmc1_ctrl_pins[] = {
2043         /* CLK, CMD */
2044         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2045 };
2046 static const unsigned int mmc1_ctrl_mux[] = {
2047         MMC1_CLK_MARK, MMC1_CMD_MARK,
2048 };
2049 /* - MSIOF0 ----------------------------------------------------------------- */
2050 static const unsigned int msiof0_clk_pins[] = {
2051         /* SCK */
2052         RCAR_GP_PIN(5, 12),
2053 };
2054 static const unsigned int msiof0_clk_mux[] = {
2055         MSIOF0_SCK_MARK,
2056 };
2057 static const unsigned int msiof0_sync_pins[] = {
2058         /* SYNC */
2059         RCAR_GP_PIN(5, 13),
2060 };
2061 static const unsigned int msiof0_sync_mux[] = {
2062         MSIOF0_SYNC_MARK,
2063 };
2064 static const unsigned int msiof0_ss1_pins[] = {
2065         /* SS1 */
2066         RCAR_GP_PIN(5, 14),
2067 };
2068 static const unsigned int msiof0_ss1_mux[] = {
2069         MSIOF0_SS1_MARK,
2070 };
2071 static const unsigned int msiof0_ss2_pins[] = {
2072         /* SS2 */
2073         RCAR_GP_PIN(5, 16),
2074 };
2075 static const unsigned int msiof0_ss2_mux[] = {
2076         MSIOF0_SS2_MARK,
2077 };
2078 static const unsigned int msiof0_rx_pins[] = {
2079         /* RXD */
2080         RCAR_GP_PIN(5, 17),
2081 };
2082 static const unsigned int msiof0_rx_mux[] = {
2083         MSIOF0_RXD_MARK,
2084 };
2085 static const unsigned int msiof0_tx_pins[] = {
2086         /* TXD */
2087         RCAR_GP_PIN(5, 15),
2088 };
2089 static const unsigned int msiof0_tx_mux[] = {
2090         MSIOF0_TXD_MARK,
2091 };
2092 /* - MSIOF1 ----------------------------------------------------------------- */
2093 static const unsigned int msiof1_clk_pins[] = {
2094         /* SCK */
2095         RCAR_GP_PIN(4, 8),
2096 };
2097 static const unsigned int msiof1_clk_mux[] = {
2098         MSIOF1_SCK_MARK,
2099 };
2100 static const unsigned int msiof1_sync_pins[] = {
2101         /* SYNC */
2102         RCAR_GP_PIN(4, 9),
2103 };
2104 static const unsigned int msiof1_sync_mux[] = {
2105         MSIOF1_SYNC_MARK,
2106 };
2107 static const unsigned int msiof1_ss1_pins[] = {
2108         /* SS1 */
2109         RCAR_GP_PIN(4, 10),
2110 };
2111 static const unsigned int msiof1_ss1_mux[] = {
2112         MSIOF1_SS1_MARK,
2113 };
2114 static const unsigned int msiof1_ss2_pins[] = {
2115         /* SS2 */
2116         RCAR_GP_PIN(4, 11),
2117 };
2118 static const unsigned int msiof1_ss2_mux[] = {
2119         MSIOF1_SS2_MARK,
2120 };
2121 static const unsigned int msiof1_rx_pins[] = {
2122         /* RXD */
2123         RCAR_GP_PIN(4, 13),
2124 };
2125 static const unsigned int msiof1_rx_mux[] = {
2126         MSIOF1_RXD_MARK,
2127 };
2128 static const unsigned int msiof1_tx_pins[] = {
2129         /* TXD */
2130         RCAR_GP_PIN(4, 12),
2131 };
2132 static const unsigned int msiof1_tx_mux[] = {
2133         MSIOF1_TXD_MARK,
2134 };
2135 /* - MSIOF2 ----------------------------------------------------------------- */
2136 static const unsigned int msiof2_clk_pins[] = {
2137         /* SCK */
2138         RCAR_GP_PIN(0, 27),
2139 };
2140 static const unsigned int msiof2_clk_mux[] = {
2141         MSIOF2_SCK_MARK,
2142 };
2143 static const unsigned int msiof2_sync_pins[] = {
2144         /* SYNC */
2145         RCAR_GP_PIN(0, 26),
2146 };
2147 static const unsigned int msiof2_sync_mux[] = {
2148         MSIOF2_SYNC_MARK,
2149 };
2150 static const unsigned int msiof2_ss1_pins[] = {
2151         /* SS1 */
2152         RCAR_GP_PIN(0, 30),
2153 };
2154 static const unsigned int msiof2_ss1_mux[] = {
2155         MSIOF2_SS1_MARK,
2156 };
2157 static const unsigned int msiof2_ss2_pins[] = {
2158         /* SS2 */
2159         RCAR_GP_PIN(0, 31),
2160 };
2161 static const unsigned int msiof2_ss2_mux[] = {
2162         MSIOF2_SS2_MARK,
2163 };
2164 static const unsigned int msiof2_rx_pins[] = {
2165         /* RXD */
2166         RCAR_GP_PIN(0, 29),
2167 };
2168 static const unsigned int msiof2_rx_mux[] = {
2169         MSIOF2_RXD_MARK,
2170 };
2171 static const unsigned int msiof2_tx_pins[] = {
2172         /* TXD */
2173         RCAR_GP_PIN(0, 28),
2174 };
2175 static const unsigned int msiof2_tx_mux[] = {
2176         MSIOF2_TXD_MARK,
2177 };
2178 /* - MSIOF3 ----------------------------------------------------------------- */
2179 static const unsigned int msiof3_clk_pins[] = {
2180         /* SCK */
2181         RCAR_GP_PIN(5, 4),
2182 };
2183 static const unsigned int msiof3_clk_mux[] = {
2184         MSIOF3_SCK_MARK,
2185 };
2186 static const unsigned int msiof3_sync_pins[] = {
2187         /* SYNC */
2188         RCAR_GP_PIN(4, 30),
2189 };
2190 static const unsigned int msiof3_sync_mux[] = {
2191         MSIOF3_SYNC_MARK,
2192 };
2193 static const unsigned int msiof3_ss1_pins[] = {
2194         /* SS1 */
2195         RCAR_GP_PIN(4, 31),
2196 };
2197 static const unsigned int msiof3_ss1_mux[] = {
2198         MSIOF3_SS1_MARK,
2199 };
2200 static const unsigned int msiof3_ss2_pins[] = {
2201         /* SS2 */
2202         RCAR_GP_PIN(4, 27),
2203 };
2204 static const unsigned int msiof3_ss2_mux[] = {
2205         MSIOF3_SS2_MARK,
2206 };
2207 static const unsigned int msiof3_rx_pins[] = {
2208         /* RXD */
2209         RCAR_GP_PIN(5, 2),
2210 };
2211 static const unsigned int msiof3_rx_mux[] = {
2212         MSIOF3_RXD_MARK,
2213 };
2214 static const unsigned int msiof3_tx_pins[] = {
2215         /* TXD */
2216         RCAR_GP_PIN(5, 3),
2217 };
2218 static const unsigned int msiof3_tx_mux[] = {
2219         MSIOF3_TXD_MARK,
2220 };
2221 /* - SCIF0 ------------------------------------------------------------------ */
2222 static const unsigned int scif0_data_pins[] = {
2223         /* RX, TX */
2224         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2225 };
2226 static const unsigned int scif0_data_mux[] = {
2227         RX0_MARK, TX0_MARK,
2228 };
2229 static const unsigned int scif0_clk_pins[] = {
2230         /* SCK */
2231         RCAR_GP_PIN(4, 27),
2232 };
2233 static const unsigned int scif0_clk_mux[] = {
2234         SCK0_MARK,
2235 };
2236 static const unsigned int scif0_ctrl_pins[] = {
2237         /* RTS, CTS */
2238         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2239 };
2240 static const unsigned int scif0_ctrl_mux[] = {
2241         RTS0_N_MARK, CTS0_N_MARK,
2242 };
2243 static const unsigned int scif0_data_b_pins[] = {
2244         /* RX, TX */
2245         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2246 };
2247 static const unsigned int scif0_data_b_mux[] = {
2248         RX0_B_MARK, TX0_B_MARK,
2249 };
2250 /* - SCIF1 ------------------------------------------------------------------ */
2251 static const unsigned int scif1_data_pins[] = {
2252         /* RX, TX */
2253         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2254 };
2255 static const unsigned int scif1_data_mux[] = {
2256         RX1_MARK, TX1_MARK,
2257 };
2258 static const unsigned int scif1_clk_pins[] = {
2259         /* SCK */
2260         RCAR_GP_PIN(4, 20),
2261 };
2262 static const unsigned int scif1_clk_mux[] = {
2263         SCK1_MARK,
2264 };
2265 static const unsigned int scif1_ctrl_pins[] = {
2266         /* RTS, CTS */
2267         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2268 };
2269 static const unsigned int scif1_ctrl_mux[] = {
2270         RTS1_N_MARK, CTS1_N_MARK,
2271 };
2272 static const unsigned int scif1_data_b_pins[] = {
2273         /* RX, TX */
2274         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2275 };
2276 static const unsigned int scif1_data_b_mux[] = {
2277         RX1_B_MARK, TX1_B_MARK,
2278 };
2279 static const unsigned int scif1_data_c_pins[] = {
2280         /* RX, TX */
2281         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2282 };
2283 static const unsigned int scif1_data_c_mux[] = {
2284         RX1_C_MARK, TX1_C_MARK,
2285 };
2286 static const unsigned int scif1_data_d_pins[] = {
2287         /* RX, TX */
2288         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2289 };
2290 static const unsigned int scif1_data_d_mux[] = {
2291         RX1_D_MARK, TX1_D_MARK,
2292 };
2293 static const unsigned int scif1_clk_d_pins[] = {
2294         /* SCK */
2295         RCAR_GP_PIN(3, 17),
2296 };
2297 static const unsigned int scif1_clk_d_mux[] = {
2298         SCK1_D_MARK,
2299 };
2300 static const unsigned int scif1_data_e_pins[] = {
2301         /* RX, TX */
2302         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2303 };
2304 static const unsigned int scif1_data_e_mux[] = {
2305         RX1_E_MARK, TX1_E_MARK,
2306 };
2307 static const unsigned int scif1_clk_e_pins[] = {
2308         /* SCK */
2309         RCAR_GP_PIN(2, 20),
2310 };
2311 static const unsigned int scif1_clk_e_mux[] = {
2312         SCK1_E_MARK,
2313 };
2314 /* - SCIF2 ------------------------------------------------------------------ */
2315 static const unsigned int scif2_data_pins[] = {
2316         /* RX, TX */
2317         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2318 };
2319 static const unsigned int scif2_data_mux[] = {
2320         RX2_MARK, TX2_MARK,
2321 };
2322 static const unsigned int scif2_clk_pins[] = {
2323         /* SCK */
2324         RCAR_GP_PIN(5, 4),
2325 };
2326 static const unsigned int scif2_clk_mux[] = {
2327         SCK2_MARK,
2328 };
2329 static const unsigned int scif2_data_b_pins[] = {
2330         /* RX, TX */
2331         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2332 };
2333 static const unsigned int scif2_data_b_mux[] = {
2334         RX2_B_MARK, TX2_B_MARK,
2335 };
2336 /* - SCIFA0 ----------------------------------------------------------------- */
2337 static const unsigned int scifa0_data_pins[] = {
2338         /* RXD, TXD */
2339         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2340 };
2341 static const unsigned int scifa0_data_mux[] = {
2342         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2343 };
2344 static const unsigned int scifa0_clk_pins[] = {
2345         /* SCK */
2346         RCAR_GP_PIN(4, 27),
2347 };
2348 static const unsigned int scifa0_clk_mux[] = {
2349         SCIFA0_SCK_MARK,
2350 };
2351 static const unsigned int scifa0_ctrl_pins[] = {
2352         /* RTS, CTS */
2353         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2354 };
2355 static const unsigned int scifa0_ctrl_mux[] = {
2356         SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2357 };
2358 static const unsigned int scifa0_data_b_pins[] = {
2359         /* RXD, TXD */
2360         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2361 };
2362 static const unsigned int scifa0_data_b_mux[] = {
2363         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2364 };
2365 static const unsigned int scifa0_clk_b_pins[] = {
2366         /* SCK */
2367         RCAR_GP_PIN(1, 19),
2368 };
2369 static const unsigned int scifa0_clk_b_mux[] = {
2370         SCIFA0_SCK_B_MARK,
2371 };
2372 static const unsigned int scifa0_ctrl_b_pins[] = {
2373         /* RTS, CTS */
2374         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2375 };
2376 static const unsigned int scifa0_ctrl_b_mux[] = {
2377         SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2378 };
2379 /* - SCIFA1 ----------------------------------------------------------------- */
2380 static const unsigned int scifa1_data_pins[] = {
2381         /* RXD, TXD */
2382         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2383 };
2384 static const unsigned int scifa1_data_mux[] = {
2385         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2386 };
2387 static const unsigned int scifa1_clk_pins[] = {
2388         /* SCK */
2389         RCAR_GP_PIN(4, 20),
2390 };
2391 static const unsigned int scifa1_clk_mux[] = {
2392         SCIFA1_SCK_MARK,
2393 };
2394 static const unsigned int scifa1_ctrl_pins[] = {
2395         /* RTS, CTS */
2396         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2397 };
2398 static const unsigned int scifa1_ctrl_mux[] = {
2399         SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2400 };
2401 static const unsigned int scifa1_data_b_pins[] = {
2402         /* RXD, TXD */
2403         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2404 };
2405 static const unsigned int scifa1_data_b_mux[] = {
2406         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2407 };
2408 static const unsigned int scifa1_clk_b_pins[] = {
2409         /* SCK */
2410         RCAR_GP_PIN(0, 23),
2411 };
2412 static const unsigned int scifa1_clk_b_mux[] = {
2413         SCIFA1_SCK_B_MARK,
2414 };
2415 static const unsigned int scifa1_ctrl_b_pins[] = {
2416         /* RTS, CTS */
2417         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2418 };
2419 static const unsigned int scifa1_ctrl_b_mux[] = {
2420         SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2421 };
2422 static const unsigned int scifa1_data_c_pins[] = {
2423         /* RXD, TXD */
2424         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2425 };
2426 static const unsigned int scifa1_data_c_mux[] = {
2427         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2428 };
2429 static const unsigned int scifa1_clk_c_pins[] = {
2430         /* SCK */
2431         RCAR_GP_PIN(0, 8),
2432 };
2433 static const unsigned int scifa1_clk_c_mux[] = {
2434         SCIFA1_SCK_C_MARK,
2435 };
2436 static const unsigned int scifa1_ctrl_c_pins[] = {
2437         /* RTS, CTS */
2438         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2439 };
2440 static const unsigned int scifa1_ctrl_c_mux[] = {
2441         SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2442 };
2443 static const unsigned int scifa1_data_d_pins[] = {
2444         /* RXD, TXD */
2445         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2446 };
2447 static const unsigned int scifa1_data_d_mux[] = {
2448         SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2449 };
2450 static const unsigned int scifa1_clk_d_pins[] = {
2451         /* SCK */
2452         RCAR_GP_PIN(2, 10),
2453 };
2454 static const unsigned int scifa1_clk_d_mux[] = {
2455         SCIFA1_SCK_D_MARK,
2456 };
2457 static const unsigned int scifa1_ctrl_d_pins[] = {
2458         /* RTS, CTS */
2459         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2460 };
2461 static const unsigned int scifa1_ctrl_d_mux[] = {
2462         SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2463 };
2464 /* - SCIFA2 ----------------------------------------------------------------- */
2465 static const unsigned int scifa2_data_pins[] = {
2466         /* RXD, TXD */
2467         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2468 };
2469 static const unsigned int scifa2_data_mux[] = {
2470         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2471 };
2472 static const unsigned int scifa2_clk_pins[] = {
2473         /* SCK */
2474         RCAR_GP_PIN(5, 4),
2475 };
2476 static const unsigned int scifa2_clk_mux[] = {
2477         SCIFA2_SCK_MARK,
2478 };
2479 static const unsigned int scifa2_ctrl_pins[] = {
2480         /* RTS, CTS */
2481         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2482 };
2483 static const unsigned int scifa2_ctrl_mux[] = {
2484         SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
2485 };
2486 static const unsigned int scifa2_data_b_pins[] = {
2487         /* RXD, TXD */
2488         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2489 };
2490 static const unsigned int scifa2_data_b_mux[] = {
2491         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2492 };
2493 static const unsigned int scifa2_data_c_pins[] = {
2494         /* RXD, TXD */
2495         RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
2496 };
2497 static const unsigned int scifa2_data_c_mux[] = {
2498         SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
2499 };
2500 static const unsigned int scifa2_clk_c_pins[] = {
2501         /* SCK */
2502         RCAR_GP_PIN(5, 29),
2503 };
2504 static const unsigned int scifa2_clk_c_mux[] = {
2505         SCIFA2_SCK_C_MARK,
2506 };
2507 /* - SCIFB0 ----------------------------------------------------------------- */
2508 static const unsigned int scifb0_data_pins[] = {
2509         /* RXD, TXD */
2510         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2511 };
2512 static const unsigned int scifb0_data_mux[] = {
2513         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2514 };
2515 static const unsigned int scifb0_clk_pins[] = {
2516         /* SCK */
2517         RCAR_GP_PIN(4, 8),
2518 };
2519 static const unsigned int scifb0_clk_mux[] = {
2520         SCIFB0_SCK_MARK,
2521 };
2522 static const unsigned int scifb0_ctrl_pins[] = {
2523         /* RTS, CTS */
2524         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2525 };
2526 static const unsigned int scifb0_ctrl_mux[] = {
2527         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2528 };
2529 static const unsigned int scifb0_data_b_pins[] = {
2530         /* RXD, TXD */
2531         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2532 };
2533 static const unsigned int scifb0_data_b_mux[] = {
2534         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2535 };
2536 static const unsigned int scifb0_clk_b_pins[] = {
2537         /* SCK */
2538         RCAR_GP_PIN(3, 9),
2539 };
2540 static const unsigned int scifb0_clk_b_mux[] = {
2541         SCIFB0_SCK_B_MARK,
2542 };
2543 static const unsigned int scifb0_ctrl_b_pins[] = {
2544         /* RTS, CTS */
2545         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2546 };
2547 static const unsigned int scifb0_ctrl_b_mux[] = {
2548         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2549 };
2550 static const unsigned int scifb0_data_c_pins[] = {
2551         /* RXD, TXD */
2552         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2553 };
2554 static const unsigned int scifb0_data_c_mux[] = {
2555         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2556 };
2557 /* - SCIFB1 ----------------------------------------------------------------- */
2558 static const unsigned int scifb1_data_pins[] = {
2559         /* RXD, TXD */
2560         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2561 };
2562 static const unsigned int scifb1_data_mux[] = {
2563         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2564 };
2565 static const unsigned int scifb1_clk_pins[] = {
2566         /* SCK */
2567         RCAR_GP_PIN(4, 14),
2568 };
2569 static const unsigned int scifb1_clk_mux[] = {
2570         SCIFB1_SCK_MARK,
2571 };
2572 static const unsigned int scifb1_ctrl_pins[] = {
2573         /* RTS, CTS */
2574         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
2575 };
2576 static const unsigned int scifb1_ctrl_mux[] = {
2577         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2578 };
2579 static const unsigned int scifb1_data_b_pins[] = {
2580         /* RXD, TXD */
2581         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2582 };
2583 static const unsigned int scifb1_data_b_mux[] = {
2584         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2585 };
2586 static const unsigned int scifb1_clk_b_pins[] = {
2587         /* SCK */
2588         RCAR_GP_PIN(3, 1),
2589 };
2590 static const unsigned int scifb1_clk_b_mux[] = {
2591         SCIFB1_SCK_B_MARK,
2592 };
2593 static const unsigned int scifb1_ctrl_b_pins[] = {
2594         /* RTS, CTS */
2595         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
2596 };
2597 static const unsigned int scifb1_ctrl_b_mux[] = {
2598         SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
2599 };
2600 static const unsigned int scifb1_data_c_pins[] = {
2601         /* RXD, TXD */
2602         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2603 };
2604 static const unsigned int scifb1_data_c_mux[] = {
2605         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2606 };
2607 static const unsigned int scifb1_data_d_pins[] = {
2608         /* RXD, TXD */
2609         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2610 };
2611 static const unsigned int scifb1_data_d_mux[] = {
2612         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2613 };
2614 static const unsigned int scifb1_data_e_pins[] = {
2615         /* RXD, TXD */
2616         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2617 };
2618 static const unsigned int scifb1_data_e_mux[] = {
2619         SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
2620 };
2621 static const unsigned int scifb1_clk_e_pins[] = {
2622         /* SCK */
2623         RCAR_GP_PIN(3, 17),
2624 };
2625 static const unsigned int scifb1_clk_e_mux[] = {
2626         SCIFB1_SCK_E_MARK,
2627 };
2628 static const unsigned int scifb1_data_f_pins[] = {
2629         /* RXD, TXD */
2630         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2631 };
2632 static const unsigned int scifb1_data_f_mux[] = {
2633         SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
2634 };
2635 static const unsigned int scifb1_data_g_pins[] = {
2636         /* RXD, TXD */
2637         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2638 };
2639 static const unsigned int scifb1_data_g_mux[] = {
2640         SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
2641 };
2642 static const unsigned int scifb1_clk_g_pins[] = {
2643         /* SCK */
2644         RCAR_GP_PIN(2, 20),
2645 };
2646 static const unsigned int scifb1_clk_g_mux[] = {
2647         SCIFB1_SCK_G_MARK,
2648 };
2649 /* - SCIFB2 ----------------------------------------------------------------- */
2650 static const unsigned int scifb2_data_pins[] = {
2651         /* RXD, TXD */
2652         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2653 };
2654 static const unsigned int scifb2_data_mux[] = {
2655         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2656 };
2657 static const unsigned int scifb2_clk_pins[] = {
2658         /* SCK */
2659         RCAR_GP_PIN(4, 21),
2660 };
2661 static const unsigned int scifb2_clk_mux[] = {
2662         SCIFB2_SCK_MARK,
2663 };
2664 static const unsigned int scifb2_ctrl_pins[] = {
2665         /* RTS, CTS */
2666         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
2667 };
2668 static const unsigned int scifb2_ctrl_mux[] = {
2669         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2670 };
2671 static const unsigned int scifb2_data_b_pins[] = {
2672         /* RXD, TXD */
2673         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
2674 };
2675 static const unsigned int scifb2_data_b_mux[] = {
2676         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
2677 };
2678 static const unsigned int scifb2_clk_b_pins[] = {
2679         /* SCK */
2680         RCAR_GP_PIN(0, 31),
2681 };
2682 static const unsigned int scifb2_clk_b_mux[] = {
2683         SCIFB2_SCK_B_MARK,
2684 };
2685 static const unsigned int scifb2_ctrl_b_pins[] = {
2686         /* RTS, CTS */
2687         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
2688 };
2689 static const unsigned int scifb2_ctrl_b_mux[] = {
2690         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
2691 };
2692 static const unsigned int scifb2_data_c_pins[] = {
2693         /* RXD, TXD */
2694         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2695 };
2696 static const unsigned int scifb2_data_c_mux[] = {
2697         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2698 };
2699 /* - SDHI0 ------------------------------------------------------------------ */
2700 static const unsigned int sdhi0_data1_pins[] = {
2701         /* D0 */
2702         RCAR_GP_PIN(3, 2),
2703 };
2704 static const unsigned int sdhi0_data1_mux[] = {
2705         SD0_DAT0_MARK,
2706 };
2707 static const unsigned int sdhi0_data4_pins[] = {
2708         /* D[0:3] */
2709         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2710 };
2711 static const unsigned int sdhi0_data4_mux[] = {
2712         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2713 };
2714 static const unsigned int sdhi0_ctrl_pins[] = {
2715         /* CLK, CMD */
2716         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2717 };
2718 static const unsigned int sdhi0_ctrl_mux[] = {
2719         SD0_CLK_MARK, SD0_CMD_MARK,
2720 };
2721 static const unsigned int sdhi0_cd_pins[] = {
2722         /* CD */
2723         RCAR_GP_PIN(3, 6),
2724 };
2725 static const unsigned int sdhi0_cd_mux[] = {
2726         SD0_CD_MARK,
2727 };
2728 static const unsigned int sdhi0_wp_pins[] = {
2729         /* WP */
2730         RCAR_GP_PIN(3, 7),
2731 };
2732 static const unsigned int sdhi0_wp_mux[] = {
2733         SD0_WP_MARK,
2734 };
2735 /* - SDHI1 ------------------------------------------------------------------ */
2736 static const unsigned int sdhi1_data1_pins[] = {
2737         /* D0 */
2738         RCAR_GP_PIN(3, 10),
2739 };
2740 static const unsigned int sdhi1_data1_mux[] = {
2741         SD1_DAT0_MARK,
2742 };
2743 static const unsigned int sdhi1_data4_pins[] = {
2744         /* D[0:3] */
2745         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2746 };
2747 static const unsigned int sdhi1_data4_mux[] = {
2748         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2749 };
2750 static const unsigned int sdhi1_ctrl_pins[] = {
2751         /* CLK, CMD */
2752         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2753 };
2754 static const unsigned int sdhi1_ctrl_mux[] = {
2755         SD1_CLK_MARK, SD1_CMD_MARK,
2756 };
2757 static const unsigned int sdhi1_cd_pins[] = {
2758         /* CD */
2759         RCAR_GP_PIN(3, 14),
2760 };
2761 static const unsigned int sdhi1_cd_mux[] = {
2762         SD1_CD_MARK,
2763 };
2764 static const unsigned int sdhi1_wp_pins[] = {
2765         /* WP */
2766         RCAR_GP_PIN(3, 15),
2767 };
2768 static const unsigned int sdhi1_wp_mux[] = {
2769         SD1_WP_MARK,
2770 };
2771 /* - SDHI2 ------------------------------------------------------------------ */
2772 static const unsigned int sdhi2_data1_pins[] = {
2773         /* D0 */
2774         RCAR_GP_PIN(3, 18),
2775 };
2776 static const unsigned int sdhi2_data1_mux[] = {
2777         SD2_DAT0_MARK,
2778 };
2779 static const unsigned int sdhi2_data4_pins[] = {
2780         /* D[0:3] */
2781         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2782 };
2783 static const unsigned int sdhi2_data4_mux[] = {
2784         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2785 };
2786 static const unsigned int sdhi2_ctrl_pins[] = {
2787         /* CLK, CMD */
2788         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2789 };
2790 static const unsigned int sdhi2_ctrl_mux[] = {
2791         SD2_CLK_MARK, SD2_CMD_MARK,
2792 };
2793 static const unsigned int sdhi2_cd_pins[] = {
2794         /* CD */
2795         RCAR_GP_PIN(3, 22),
2796 };
2797 static const unsigned int sdhi2_cd_mux[] = {
2798         SD2_CD_MARK,
2799 };
2800 static const unsigned int sdhi2_wp_pins[] = {
2801         /* WP */
2802         RCAR_GP_PIN(3, 23),
2803 };
2804 static const unsigned int sdhi2_wp_mux[] = {
2805         SD2_WP_MARK,
2806 };
2807 /* - SDHI3 ------------------------------------------------------------------ */
2808 static const unsigned int sdhi3_data1_pins[] = {
2809         /* D0 */
2810         RCAR_GP_PIN(3, 26),
2811 };
2812 static const unsigned int sdhi3_data1_mux[] = {
2813         SD3_DAT0_MARK,
2814 };
2815 static const unsigned int sdhi3_data4_pins[] = {
2816         /* D[0:3] */
2817         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2818 };
2819 static const unsigned int sdhi3_data4_mux[] = {
2820         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2821 };
2822 static const unsigned int sdhi3_ctrl_pins[] = {
2823         /* CLK, CMD */
2824         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2825 };
2826 static const unsigned int sdhi3_ctrl_mux[] = {
2827         SD3_CLK_MARK, SD3_CMD_MARK,
2828 };
2829 static const unsigned int sdhi3_cd_pins[] = {
2830         /* CD */
2831         RCAR_GP_PIN(3, 30),
2832 };
2833 static const unsigned int sdhi3_cd_mux[] = {
2834         SD3_CD_MARK,
2835 };
2836 static const unsigned int sdhi3_wp_pins[] = {
2837         /* WP */
2838         RCAR_GP_PIN(3, 31),
2839 };
2840 static const unsigned int sdhi3_wp_mux[] = {
2841         SD3_WP_MARK,
2842 };
2843 /* - TPU0 ------------------------------------------------------------------- */
2844 static const unsigned int tpu0_to0_pins[] = {
2845         /* TO */
2846         RCAR_GP_PIN(0, 20),
2847 };
2848 static const unsigned int tpu0_to0_mux[] = {
2849         TPU0TO0_MARK,
2850 };
2851 static const unsigned int tpu0_to1_pins[] = {
2852         /* TO */
2853         RCAR_GP_PIN(0, 21),
2854 };
2855 static const unsigned int tpu0_to1_mux[] = {
2856         TPU0TO1_MARK,
2857 };
2858 static const unsigned int tpu0_to2_pins[] = {
2859         /* TO */
2860         RCAR_GP_PIN(0, 22),
2861 };
2862 static const unsigned int tpu0_to2_mux[] = {
2863         TPU0TO2_MARK,
2864 };
2865 static const unsigned int tpu0_to3_pins[] = {
2866         /* TO */
2867         RCAR_GP_PIN(0, 23),
2868 };
2869 static const unsigned int tpu0_to3_mux[] = {
2870         TPU0TO3_MARK,
2871 };
2872 /* - USB0 ------------------------------------------------------------------- */
2873 static const unsigned int usb0_pins[] = {
2874         /* PWEN, OVC/VBUS */
2875         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2876 };
2877 static const unsigned int usb0_mux[] = {
2878         USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
2879 };
2880 /* - USB1 ------------------------------------------------------------------- */
2881 static const unsigned int usb1_pins[] = {
2882         /* PWEN, OVC */
2883         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2884 };
2885 static const unsigned int usb1_mux[] = {
2886         USB1_PWEN_MARK, USB1_OVC_MARK,
2887 };
2888 /* - USB2 ------------------------------------------------------------------- */
2889 static const unsigned int usb2_pins[] = {
2890         /* PWEN, OVC */
2891         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2892 };
2893 static const unsigned int usb2_mux[] = {
2894         USB2_PWEN_MARK, USB2_OVC_MARK,
2895 };
2896
2897 static const struct sh_pfc_pin_group pinmux_groups[] = {
2898         SH_PFC_PIN_GROUP(eth_link),
2899         SH_PFC_PIN_GROUP(eth_magic),
2900         SH_PFC_PIN_GROUP(eth_mdio),
2901         SH_PFC_PIN_GROUP(eth_rmii),
2902         SH_PFC_PIN_GROUP(hscif0_data),
2903         SH_PFC_PIN_GROUP(hscif0_clk),
2904         SH_PFC_PIN_GROUP(hscif0_ctrl),
2905         SH_PFC_PIN_GROUP(hscif0_data_b),
2906         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2907         SH_PFC_PIN_GROUP(hscif0_data_c),
2908         SH_PFC_PIN_GROUP(hscif0_ctrl_c),
2909         SH_PFC_PIN_GROUP(hscif0_data_d),
2910         SH_PFC_PIN_GROUP(hscif0_ctrl_d),
2911         SH_PFC_PIN_GROUP(hscif0_data_e),
2912         SH_PFC_PIN_GROUP(hscif0_ctrl_e),
2913         SH_PFC_PIN_GROUP(hscif0_data_f),
2914         SH_PFC_PIN_GROUP(hscif0_ctrl_f),
2915         SH_PFC_PIN_GROUP(hscif1_data),
2916         SH_PFC_PIN_GROUP(hscif1_clk),
2917         SH_PFC_PIN_GROUP(hscif1_ctrl),
2918         SH_PFC_PIN_GROUP(hscif1_data_b),
2919         SH_PFC_PIN_GROUP(hscif1_clk_b),
2920         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2921         SH_PFC_PIN_GROUP(intc_irq0),
2922         SH_PFC_PIN_GROUP(intc_irq1),
2923         SH_PFC_PIN_GROUP(intc_irq2),
2924         SH_PFC_PIN_GROUP(intc_irq3),
2925         SH_PFC_PIN_GROUP(mmc0_data1),
2926         SH_PFC_PIN_GROUP(mmc0_data4),
2927         SH_PFC_PIN_GROUP(mmc0_data8),
2928         SH_PFC_PIN_GROUP(mmc0_ctrl),
2929         SH_PFC_PIN_GROUP(mmc1_data1),
2930         SH_PFC_PIN_GROUP(mmc1_data4),
2931         SH_PFC_PIN_GROUP(mmc1_data8),
2932         SH_PFC_PIN_GROUP(mmc1_ctrl),
2933         SH_PFC_PIN_GROUP(msiof0_clk),
2934         SH_PFC_PIN_GROUP(msiof0_sync),
2935         SH_PFC_PIN_GROUP(msiof0_ss1),
2936         SH_PFC_PIN_GROUP(msiof0_ss2),
2937         SH_PFC_PIN_GROUP(msiof0_rx),
2938         SH_PFC_PIN_GROUP(msiof0_tx),
2939         SH_PFC_PIN_GROUP(msiof1_clk),
2940         SH_PFC_PIN_GROUP(msiof1_sync),
2941         SH_PFC_PIN_GROUP(msiof1_ss1),
2942         SH_PFC_PIN_GROUP(msiof1_ss2),
2943         SH_PFC_PIN_GROUP(msiof1_rx),
2944         SH_PFC_PIN_GROUP(msiof1_tx),
2945         SH_PFC_PIN_GROUP(msiof2_clk),
2946         SH_PFC_PIN_GROUP(msiof2_sync),
2947         SH_PFC_PIN_GROUP(msiof2_ss1),
2948         SH_PFC_PIN_GROUP(msiof2_ss2),
2949         SH_PFC_PIN_GROUP(msiof2_rx),
2950         SH_PFC_PIN_GROUP(msiof2_tx),
2951         SH_PFC_PIN_GROUP(msiof3_clk),
2952         SH_PFC_PIN_GROUP(msiof3_sync),
2953         SH_PFC_PIN_GROUP(msiof3_ss1),
2954         SH_PFC_PIN_GROUP(msiof3_ss2),
2955         SH_PFC_PIN_GROUP(msiof3_rx),
2956         SH_PFC_PIN_GROUP(msiof3_tx),
2957         SH_PFC_PIN_GROUP(scif0_data),
2958         SH_PFC_PIN_GROUP(scif0_clk),
2959         SH_PFC_PIN_GROUP(scif0_ctrl),
2960         SH_PFC_PIN_GROUP(scif0_data_b),
2961         SH_PFC_PIN_GROUP(scif1_data),
2962         SH_PFC_PIN_GROUP(scif1_clk),
2963         SH_PFC_PIN_GROUP(scif1_ctrl),
2964         SH_PFC_PIN_GROUP(scif1_data_b),
2965         SH_PFC_PIN_GROUP(scif1_data_c),
2966         SH_PFC_PIN_GROUP(scif1_data_d),
2967         SH_PFC_PIN_GROUP(scif1_clk_d),
2968         SH_PFC_PIN_GROUP(scif1_data_e),
2969         SH_PFC_PIN_GROUP(scif1_clk_e),
2970         SH_PFC_PIN_GROUP(scif2_data),
2971         SH_PFC_PIN_GROUP(scif2_clk),
2972         SH_PFC_PIN_GROUP(scif2_data_b),
2973         SH_PFC_PIN_GROUP(scifa0_data),
2974         SH_PFC_PIN_GROUP(scifa0_clk),
2975         SH_PFC_PIN_GROUP(scifa0_ctrl),
2976         SH_PFC_PIN_GROUP(scifa0_data_b),
2977         SH_PFC_PIN_GROUP(scifa0_clk_b),
2978         SH_PFC_PIN_GROUP(scifa0_ctrl_b),
2979         SH_PFC_PIN_GROUP(scifa1_data),
2980         SH_PFC_PIN_GROUP(scifa1_clk),
2981         SH_PFC_PIN_GROUP(scifa1_ctrl),
2982         SH_PFC_PIN_GROUP(scifa1_data_b),
2983         SH_PFC_PIN_GROUP(scifa1_clk_b),
2984         SH_PFC_PIN_GROUP(scifa1_ctrl_b),
2985         SH_PFC_PIN_GROUP(scifa1_data_c),
2986         SH_PFC_PIN_GROUP(scifa1_clk_c),
2987         SH_PFC_PIN_GROUP(scifa1_ctrl_c),
2988         SH_PFC_PIN_GROUP(scifa1_data_d),
2989         SH_PFC_PIN_GROUP(scifa1_clk_d),
2990         SH_PFC_PIN_GROUP(scifa1_ctrl_d),
2991         SH_PFC_PIN_GROUP(scifa2_data),
2992         SH_PFC_PIN_GROUP(scifa2_clk),
2993         SH_PFC_PIN_GROUP(scifa2_ctrl),
2994         SH_PFC_PIN_GROUP(scifa2_data_b),
2995         SH_PFC_PIN_GROUP(scifa2_data_c),
2996         SH_PFC_PIN_GROUP(scifa2_clk_c),
2997         SH_PFC_PIN_GROUP(scifb0_data),
2998         SH_PFC_PIN_GROUP(scifb0_clk),
2999         SH_PFC_PIN_GROUP(scifb0_ctrl),
3000         SH_PFC_PIN_GROUP(scifb0_data_b),
3001         SH_PFC_PIN_GROUP(scifb0_clk_b),
3002         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3003         SH_PFC_PIN_GROUP(scifb0_data_c),
3004         SH_PFC_PIN_GROUP(scifb1_data),
3005         SH_PFC_PIN_GROUP(scifb1_clk),
3006         SH_PFC_PIN_GROUP(scifb1_ctrl),
3007         SH_PFC_PIN_GROUP(scifb1_data_b),
3008         SH_PFC_PIN_GROUP(scifb1_clk_b),
3009         SH_PFC_PIN_GROUP(scifb1_ctrl_b),
3010         SH_PFC_PIN_GROUP(scifb1_data_c),
3011         SH_PFC_PIN_GROUP(scifb1_data_d),
3012         SH_PFC_PIN_GROUP(scifb1_data_e),
3013         SH_PFC_PIN_GROUP(scifb1_clk_e),
3014         SH_PFC_PIN_GROUP(scifb1_data_f),
3015         SH_PFC_PIN_GROUP(scifb1_data_g),
3016         SH_PFC_PIN_GROUP(scifb1_clk_g),
3017         SH_PFC_PIN_GROUP(scifb2_data),
3018         SH_PFC_PIN_GROUP(scifb2_clk),
3019         SH_PFC_PIN_GROUP(scifb2_ctrl),
3020         SH_PFC_PIN_GROUP(scifb2_data_b),
3021         SH_PFC_PIN_GROUP(scifb2_clk_b),
3022         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3023         SH_PFC_PIN_GROUP(scifb2_data_c),
3024         SH_PFC_PIN_GROUP(sdhi0_data1),
3025         SH_PFC_PIN_GROUP(sdhi0_data4),
3026         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3027         SH_PFC_PIN_GROUP(sdhi0_cd),
3028         SH_PFC_PIN_GROUP(sdhi0_wp),
3029         SH_PFC_PIN_GROUP(sdhi1_data1),
3030         SH_PFC_PIN_GROUP(sdhi1_data4),
3031         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3032         SH_PFC_PIN_GROUP(sdhi1_cd),
3033         SH_PFC_PIN_GROUP(sdhi1_wp),
3034         SH_PFC_PIN_GROUP(sdhi2_data1),
3035         SH_PFC_PIN_GROUP(sdhi2_data4),
3036         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3037         SH_PFC_PIN_GROUP(sdhi2_cd),
3038         SH_PFC_PIN_GROUP(sdhi2_wp),
3039         SH_PFC_PIN_GROUP(sdhi3_data1),
3040         SH_PFC_PIN_GROUP(sdhi3_data4),
3041         SH_PFC_PIN_GROUP(sdhi3_ctrl),
3042         SH_PFC_PIN_GROUP(sdhi3_cd),
3043         SH_PFC_PIN_GROUP(sdhi3_wp),
3044         SH_PFC_PIN_GROUP(tpu0_to0),
3045         SH_PFC_PIN_GROUP(tpu0_to1),
3046         SH_PFC_PIN_GROUP(tpu0_to2),
3047         SH_PFC_PIN_GROUP(tpu0_to3),
3048         SH_PFC_PIN_GROUP(usb0),
3049         SH_PFC_PIN_GROUP(usb1),
3050         SH_PFC_PIN_GROUP(usb2),
3051 };
3052
3053 static const char * const eth_groups[] = {
3054         "eth_link",
3055         "eth_magic",
3056         "eth_mdio",
3057         "eth_rmii",
3058 };
3059
3060 static const char * const hscif0_groups[] = {
3061         "hscif0_data",
3062         "hscif0_clk",
3063         "hscif0_ctrl",
3064         "hscif0_data_b",
3065         "hscif0_ctrl_b",
3066         "hscif0_data_c",
3067         "hscif0_ctrl_c",
3068         "hscif0_data_d",
3069         "hscif0_ctrl_d",
3070         "hscif0_data_e",
3071         "hscif0_ctrl_e",
3072         "hscif0_data_f",
3073         "hscif0_ctrl_f",
3074 };
3075
3076 static const char * const hscif1_groups[] = {
3077         "hscif1_data",
3078         "hscif1_clk",
3079         "hscif1_ctrl",
3080         "hscif1_data_b",
3081         "hscif1_clk_b",
3082         "hscif1_ctrl_b",
3083 };
3084
3085 static const char * const intc_groups[] = {
3086         "intc_irq0",
3087         "intc_irq1",
3088         "intc_irq2",
3089         "intc_irq3",
3090 };
3091
3092 static const char * const mmc0_groups[] = {
3093         "mmc0_data1",
3094         "mmc0_data4",
3095         "mmc0_data8",
3096         "mmc0_ctrl",
3097 };
3098
3099 static const char * const mmc1_groups[] = {
3100         "mmc1_data1",
3101         "mmc1_data4",
3102         "mmc1_data8",
3103         "mmc1_ctrl",
3104 };
3105
3106 static const char * const msiof0_groups[] = {
3107         "msiof0_clk",
3108         "msiof0_sync",
3109         "msiof0_ss1",
3110         "msiof0_ss2",
3111         "msiof0_rx",
3112         "msiof0_tx",
3113 };
3114
3115 static const char * const msiof1_groups[] = {
3116         "msiof1_clk",
3117         "msiof1_sync",
3118         "msiof1_ss1",
3119         "msiof1_ss2",
3120         "msiof1_rx",
3121         "msiof1_tx",
3122 };
3123
3124 static const char * const msiof2_groups[] = {
3125         "msiof2_clk",
3126         "msiof2_sync",
3127         "msiof2_ss1",
3128         "msiof2_ss2",
3129         "msiof2_rx",
3130         "msiof2_tx",
3131 };
3132
3133 static const char * const msiof3_groups[] = {
3134         "msiof3_clk",
3135         "msiof3_sync",
3136         "msiof3_ss1",
3137         "msiof3_ss2",
3138         "msiof3_rx",
3139         "msiof3_tx",
3140 };
3141
3142 static const char * const scif0_groups[] = {
3143         "scif0_data",
3144         "scif0_clk",
3145         "scif0_ctrl",
3146         "scif0_data_b",
3147 };
3148
3149 static const char * const scif1_groups[] = {
3150         "scif1_data",
3151         "scif1_clk",
3152         "scif1_ctrl",
3153         "scif1_data_b",
3154         "scif1_data_c",
3155         "scif1_data_d",
3156         "scif1_clk_d",
3157         "scif1_data_e",
3158         "scif1_clk_e",
3159 };
3160
3161 static const char * const scif2_groups[] = {
3162         "scif2_data",
3163         "scif2_clk",
3164         "scif2_data_b",
3165 };
3166
3167 static const char * const scifa0_groups[] = {
3168         "scifa0_data",
3169         "scifa0_clk",
3170         "scifa0_ctrl",
3171         "scifa0_data_b",
3172         "scifa0_clk_b",
3173         "scifa0_ctrl_b",
3174 };
3175
3176 static const char * const scifa1_groups[] = {
3177         "scifa1_data",
3178         "scifa1_clk",
3179         "scifa1_ctrl",
3180         "scifa1_data_b",
3181         "scifa1_clk_b",
3182         "scifa1_ctrl_b",
3183         "scifa1_data_c",
3184         "scifa1_clk_c",
3185         "scifa1_ctrl_c",
3186         "scifa1_data_d",
3187         "scifa1_clk_d",
3188         "scifa1_ctrl_d",
3189 };
3190
3191 static const char * const scifa2_groups[] = {
3192         "scifa2_data",
3193         "scifa2_clk",
3194         "scifa2_ctrl",
3195         "scifa2_data_b",
3196         "scifa2_data_c",
3197         "scifa2_clk_c",
3198 };
3199
3200 static const char * const scifb0_groups[] = {
3201         "scifb0_data",
3202         "scifb0_clk",
3203         "scifb0_ctrl",
3204         "scifb0_data_b",
3205         "scifb0_clk_b",
3206         "scifb0_ctrl_b",
3207         "scifb0_data_c",
3208 };
3209
3210 static const char * const scifb1_groups[] = {
3211         "scifb1_data",
3212         "scifb1_clk",
3213         "scifb1_ctrl",
3214         "scifb1_data_b",
3215         "scifb1_clk_b",
3216         "scifb1_ctrl_b",
3217         "scifb1_data_c",
3218         "scifb1_data_d",
3219         "scifb1_data_e",
3220         "scifb1_clk_e",
3221         "scifb1_data_f",
3222         "scifb1_data_g",
3223         "scifb1_clk_g",
3224 };
3225
3226 static const char * const scifb2_groups[] = {
3227         "scifb2_data",
3228         "scifb2_clk",
3229         "scifb2_ctrl",
3230         "scifb2_data_b",
3231         "scifb2_clk_b",
3232         "scifb2_ctrl_b",
3233         "scifb2_data_c",
3234 };
3235
3236 static const char * const sdhi0_groups[] = {
3237         "sdhi0_data1",
3238         "sdhi0_data4",
3239         "sdhi0_ctrl",
3240         "sdhi0_cd",
3241         "sdhi0_wp",
3242 };
3243
3244 static const char * const sdhi1_groups[] = {
3245         "sdhi1_data1",
3246         "sdhi1_data4",
3247         "sdhi1_ctrl",
3248         "sdhi1_cd",
3249         "sdhi1_wp",
3250 };
3251
3252 static const char * const sdhi2_groups[] = {
3253         "sdhi2_data1",
3254         "sdhi2_data4",
3255         "sdhi2_ctrl",
3256         "sdhi2_cd",
3257         "sdhi2_wp",
3258 };
3259
3260 static const char * const sdhi3_groups[] = {
3261         "sdhi3_data1",
3262         "sdhi3_data4",
3263         "sdhi3_ctrl",
3264         "sdhi3_cd",
3265         "sdhi3_wp",
3266 };
3267
3268 static const char * const tpu0_groups[] = {
3269         "tpu0_to0",
3270         "tpu0_to1",
3271         "tpu0_to2",
3272         "tpu0_to3",
3273 };
3274
3275 static const char * const usb0_groups[] = {
3276         "usb0",
3277 };
3278
3279 static const char * const usb1_groups[] = {
3280         "usb1",
3281 };
3282
3283 static const char * const usb2_groups[] = {
3284         "usb2",
3285 };
3286
3287 static const struct sh_pfc_function pinmux_functions[] = {
3288         SH_PFC_FUNCTION(eth),
3289         SH_PFC_FUNCTION(hscif0),
3290         SH_PFC_FUNCTION(hscif1),
3291         SH_PFC_FUNCTION(intc),
3292         SH_PFC_FUNCTION(mmc0),
3293         SH_PFC_FUNCTION(mmc1),
3294         SH_PFC_FUNCTION(msiof0),
3295         SH_PFC_FUNCTION(msiof1),
3296         SH_PFC_FUNCTION(msiof2),
3297         SH_PFC_FUNCTION(msiof3),
3298         SH_PFC_FUNCTION(scif0),
3299         SH_PFC_FUNCTION(scif1),
3300         SH_PFC_FUNCTION(scif2),
3301         SH_PFC_FUNCTION(scifa0),
3302         SH_PFC_FUNCTION(scifa1),
3303         SH_PFC_FUNCTION(scifa2),
3304         SH_PFC_FUNCTION(scifb0),
3305         SH_PFC_FUNCTION(scifb1),
3306         SH_PFC_FUNCTION(scifb2),
3307         SH_PFC_FUNCTION(sdhi0),
3308         SH_PFC_FUNCTION(sdhi1),
3309         SH_PFC_FUNCTION(sdhi2),
3310         SH_PFC_FUNCTION(sdhi3),
3311         SH_PFC_FUNCTION(tpu0),
3312         SH_PFC_FUNCTION(usb0),
3313         SH_PFC_FUNCTION(usb1),
3314         SH_PFC_FUNCTION(usb2),
3315 };
3316
3317 static struct pinmux_cfg_reg pinmux_config_regs[] = {
3318         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3319                 GP_0_31_FN, FN_IP3_17_15,
3320                 GP_0_30_FN, FN_IP3_14_12,
3321                 GP_0_29_FN, FN_IP3_11_8,
3322                 GP_0_28_FN, FN_IP3_7_4,
3323                 GP_0_27_FN, FN_IP3_3_0,
3324                 GP_0_26_FN, FN_IP2_28_26,
3325                 GP_0_25_FN, FN_IP2_25_22,
3326                 GP_0_24_FN, FN_IP2_21_18,
3327                 GP_0_23_FN, FN_IP2_17_15,
3328                 GP_0_22_FN, FN_IP2_14_12,
3329                 GP_0_21_FN, FN_IP2_11_9,
3330                 GP_0_20_FN, FN_IP2_8_6,
3331                 GP_0_19_FN, FN_IP2_5_3,
3332                 GP_0_18_FN, FN_IP2_2_0,
3333                 GP_0_17_FN, FN_IP1_29_28,
3334                 GP_0_16_FN, FN_IP1_27_26,
3335                 GP_0_15_FN, FN_IP1_25_22,
3336                 GP_0_14_FN, FN_IP1_21_18,
3337                 GP_0_13_FN, FN_IP1_17_15,
3338                 GP_0_12_FN, FN_IP1_14_12,
3339                 GP_0_11_FN, FN_IP1_11_8,
3340                 GP_0_10_FN, FN_IP1_7_4,
3341                 GP_0_9_FN, FN_IP1_3_0,
3342                 GP_0_8_FN, FN_IP0_30_27,
3343                 GP_0_7_FN, FN_IP0_26_23,
3344                 GP_0_6_FN, FN_IP0_22_20,
3345                 GP_0_5_FN, FN_IP0_19_16,
3346                 GP_0_4_FN, FN_IP0_15_12,
3347                 GP_0_3_FN, FN_IP0_11_9,
3348                 GP_0_2_FN, FN_IP0_8_6,
3349                 GP_0_1_FN, FN_IP0_5_3,
3350                 GP_0_0_FN, FN_IP0_2_0 }
3351         },
3352         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3353                 0, 0,
3354                 0, 0,
3355                 GP_1_29_FN, FN_IP6_13_11,
3356                 GP_1_28_FN, FN_IP6_10_9,
3357                 GP_1_27_FN, FN_IP6_8_6,
3358                 GP_1_26_FN, FN_IP6_5_3,
3359                 GP_1_25_FN, FN_IP6_2_0,
3360                 GP_1_24_FN, FN_IP5_29_27,
3361                 GP_1_23_FN, FN_IP5_26_24,
3362                 GP_1_22_FN, FN_IP5_23_21,
3363                 GP_1_21_FN, FN_IP5_20_18,
3364                 GP_1_20_FN, FN_IP5_17_15,
3365                 GP_1_19_FN, FN_IP5_14_13,
3366                 GP_1_18_FN, FN_IP5_12_10,
3367                 GP_1_17_FN, FN_IP5_9_6,
3368                 GP_1_16_FN, FN_IP5_5_3,
3369                 GP_1_15_FN, FN_IP5_2_0,
3370                 GP_1_14_FN, FN_IP4_29_27,
3371                 GP_1_13_FN, FN_IP4_26_24,
3372                 GP_1_12_FN, FN_IP4_23_21,
3373                 GP_1_11_FN, FN_IP4_20_18,
3374                 GP_1_10_FN, FN_IP4_17_15,
3375                 GP_1_9_FN, FN_IP4_14_12,
3376                 GP_1_8_FN, FN_IP4_11_9,
3377                 GP_1_7_FN, FN_IP4_8_6,
3378                 GP_1_6_FN, FN_IP4_5_3,
3379                 GP_1_5_FN, FN_IP4_2_0,
3380                 GP_1_4_FN, FN_IP3_31_29,
3381                 GP_1_3_FN, FN_IP3_28_26,
3382                 GP_1_2_FN, FN_IP3_25_23,
3383                 GP_1_1_FN, FN_IP3_22_20,
3384                 GP_1_0_FN, FN_IP3_19_18, }
3385         },
3386         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3387                 0, 0,
3388                 0, 0,
3389                 GP_2_29_FN, FN_IP7_15_13,
3390                 GP_2_28_FN, FN_IP7_12_10,
3391                 GP_2_27_FN, FN_IP7_9_8,
3392                 GP_2_26_FN, FN_IP7_7_6,
3393                 GP_2_25_FN, FN_IP7_5_3,
3394                 GP_2_24_FN, FN_IP7_2_0,
3395                 GP_2_23_FN, FN_IP6_31_29,
3396                 GP_2_22_FN, FN_IP6_28_26,
3397                 GP_2_21_FN, FN_IP6_25_23,
3398                 GP_2_20_FN, FN_IP6_22_20,
3399                 GP_2_19_FN, FN_IP6_19_17,
3400                 GP_2_18_FN, FN_IP6_16_14,
3401                 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
3402                 GP_2_16_FN, FN_IP8_27,
3403                 GP_2_15_FN, FN_IP8_26,
3404                 GP_2_14_FN, FN_IP8_25_24,
3405                 GP_2_13_FN, FN_IP8_23_22,
3406                 GP_2_12_FN, FN_IP8_21_20,
3407                 GP_2_11_FN, FN_IP8_19_18,
3408                 GP_2_10_FN, FN_IP8_17_16,
3409                 GP_2_9_FN, FN_IP8_15_14,
3410                 GP_2_8_FN, FN_IP8_13_12,
3411                 GP_2_7_FN, FN_IP8_11_10,
3412                 GP_2_6_FN, FN_IP8_9_8,
3413                 GP_2_5_FN, FN_IP8_7_6,
3414                 GP_2_4_FN, FN_IP8_5_4,
3415                 GP_2_3_FN, FN_IP8_3_2,
3416                 GP_2_2_FN, FN_IP8_1_0,
3417                 GP_2_1_FN, FN_IP7_30_29,
3418                 GP_2_0_FN, FN_IP7_28_27 }
3419         },
3420         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3421                 GP_3_31_FN, FN_IP11_21_18,
3422                 GP_3_30_FN, FN_IP11_17_15,
3423                 GP_3_29_FN, FN_IP11_14_13,
3424                 GP_3_28_FN, FN_IP11_12_11,
3425                 GP_3_27_FN, FN_IP11_10_9,
3426                 GP_3_26_FN, FN_IP11_8_7,
3427                 GP_3_25_FN, FN_IP11_6_5,
3428                 GP_3_24_FN, FN_IP11_4,
3429                 GP_3_23_FN, FN_IP11_3_0,
3430                 GP_3_22_FN, FN_IP10_29_26,
3431                 GP_3_21_FN, FN_IP10_25_23,
3432                 GP_3_20_FN, FN_IP10_22_19,
3433                 GP_3_19_FN, FN_IP10_18_15,
3434                 GP_3_18_FN, FN_IP10_14_11,
3435                 GP_3_17_FN, FN_IP10_10_7,
3436                 GP_3_16_FN, FN_IP10_6_4,
3437                 GP_3_15_FN, FN_IP10_3_0,
3438                 GP_3_14_FN, FN_IP9_31_28,
3439                 GP_3_13_FN, FN_IP9_27_26,
3440                 GP_3_12_FN, FN_IP9_25_24,
3441                 GP_3_11_FN, FN_IP9_23_22,
3442                 GP_3_10_FN, FN_IP9_21_20,
3443                 GP_3_9_FN, FN_IP9_19_18,
3444                 GP_3_8_FN, FN_IP9_17_16,
3445                 GP_3_7_FN, FN_IP9_15_12,
3446                 GP_3_6_FN, FN_IP9_11_8,
3447                 GP_3_5_FN, FN_IP9_7_6,
3448                 GP_3_4_FN, FN_IP9_5_4,
3449                 GP_3_3_FN, FN_IP9_3_2,
3450                 GP_3_2_FN, FN_IP9_1_0,
3451                 GP_3_1_FN, FN_IP8_30_29,
3452                 GP_3_0_FN, FN_IP8_28 }
3453         },
3454         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3455                 GP_4_31_FN, FN_IP14_18_16,
3456                 GP_4_30_FN, FN_IP14_15_12,
3457                 GP_4_29_FN, FN_IP14_11_9,
3458                 GP_4_28_FN, FN_IP14_8_6,
3459                 GP_4_27_FN, FN_IP14_5_3,
3460                 GP_4_26_FN, FN_IP14_2_0,
3461                 GP_4_25_FN, FN_IP13_30_29,
3462                 GP_4_24_FN, FN_IP13_28_26,
3463                 GP_4_23_FN, FN_IP13_25_23,
3464                 GP_4_22_FN, FN_IP13_22_19,
3465                 GP_4_21_FN, FN_IP13_18_16,
3466                 GP_4_20_FN, FN_IP13_15_13,
3467                 GP_4_19_FN, FN_IP13_12_10,
3468                 GP_4_18_FN, FN_IP13_9_7,
3469                 GP_4_17_FN, FN_IP13_6_3,
3470                 GP_4_16_FN, FN_IP13_2_0,
3471                 GP_4_15_FN, FN_IP12_30_28,
3472                 GP_4_14_FN, FN_IP12_27_25,
3473                 GP_4_13_FN, FN_IP12_24_23,
3474                 GP_4_12_FN, FN_IP12_22_20,
3475                 GP_4_11_FN, FN_IP12_19_17,
3476                 GP_4_10_FN, FN_IP12_16_14,
3477                 GP_4_9_FN, FN_IP12_13_11,
3478                 GP_4_8_FN, FN_IP12_10_8,
3479                 GP_4_7_FN, FN_IP12_7_6,
3480                 GP_4_6_FN, FN_IP12_5_4,
3481                 GP_4_5_FN, FN_IP12_3_2,
3482                 GP_4_4_FN, FN_IP12_1_0,
3483                 GP_4_3_FN, FN_IP11_31_30,
3484                 GP_4_2_FN, FN_IP11_29_27,
3485                 GP_4_1_FN, FN_IP11_26_24,
3486                 GP_4_0_FN, FN_IP11_23_22 }
3487         },
3488         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3489                 GP_5_31_FN, FN_IP7_24_22,
3490                 GP_5_30_FN, FN_IP7_21_19,
3491                 GP_5_29_FN, FN_IP7_18_16,
3492                 GP_5_28_FN, FN_DU_DOTCLKIN2,
3493                 GP_5_27_FN, FN_IP7_26_25,
3494                 GP_5_26_FN, FN_DU_DOTCLKIN0,
3495                 GP_5_25_FN, FN_AVS2,
3496                 GP_5_24_FN, FN_AVS1,
3497                 GP_5_23_FN, FN_USB2_OVC,
3498                 GP_5_22_FN, FN_USB2_PWEN,
3499                 GP_5_21_FN, FN_IP16_7,
3500                 GP_5_20_FN, FN_IP16_6,
3501                 GP_5_19_FN, FN_USB0_OVC_VBUS,
3502                 GP_5_18_FN, FN_USB0_PWEN,
3503                 GP_5_17_FN, FN_IP16_5_3,
3504                 GP_5_16_FN, FN_IP16_2_0,
3505                 GP_5_15_FN, FN_IP15_29_28,
3506                 GP_5_14_FN, FN_IP15_27_26,
3507                 GP_5_13_FN, FN_IP15_25_23,
3508                 GP_5_12_FN, FN_IP15_22_20,
3509                 GP_5_11_FN, FN_IP15_19_18,
3510                 GP_5_10_FN, FN_IP15_17_16,
3511                 GP_5_9_FN, FN_IP15_15_14,
3512                 GP_5_8_FN, FN_IP15_13_12,
3513                 GP_5_7_FN, FN_IP15_11_9,
3514                 GP_5_6_FN, FN_IP15_8_6,
3515                 GP_5_5_FN, FN_IP15_5_3,
3516                 GP_5_4_FN, FN_IP15_2_0,
3517                 GP_5_3_FN, FN_IP14_30_28,
3518                 GP_5_2_FN, FN_IP14_27_25,
3519                 GP_5_1_FN, FN_IP14_24_22,
3520                 GP_5_0_FN, FN_IP14_21_19 }
3521         },
3522         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3523                              1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
3524                 /* IP0_31 [1] */
3525                 0, 0,
3526                 /* IP0_30_27 [4] */
3527                 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
3528                 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
3529                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3530                 /* IP0_26_23 [4] */
3531                 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
3532                 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
3533                 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
3534                 /* IP0_22_20 [3] */
3535                 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
3536                 FN_I2C2_SCL_C, 0, 0,
3537                 /* IP0_19_16 [4] */
3538                 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
3539                 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
3540                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3541                 /* IP0_15_12 [4] */
3542                 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
3543                 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
3544                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3545                 /* IP0_11_9 [3] */
3546                 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
3547                 0, 0, 0,
3548                 /* IP0_8_6 [3] */
3549                 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
3550                 0, 0, 0,
3551                 /* IP0_5_3 [3] */
3552                 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
3553                 0, 0, 0,
3554                 /* IP0_2_0 [3] */
3555                 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
3556                 0, 0, 0, }
3557         },
3558         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3559                              2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
3560                 /* IP1_31_30 [2] */
3561                 0, 0, 0, 0,
3562                 /* IP1_29_28 [2] */
3563                 FN_A1, FN_PWM4, 0, 0,
3564                 /* IP1_27_26 [2] */
3565                 FN_A0, FN_PWM3, 0, 0,
3566                 /* IP1_25_22 [4] */
3567                 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
3568                 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
3569                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3570                 /* IP1_21_18 [4] */
3571                 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
3572                 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
3573                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3574                 /* IP1_17_15 [3] */
3575                 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
3576                 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
3577                 0, 0, 0,
3578                 /* IP1_14_12 [3] */
3579                 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
3580                 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
3581                 0, 0,
3582                 /* IP1_11_8 [4] */
3583                 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
3584                 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
3585                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3586                 /* IP1_7_4 [4] */
3587                 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
3588                 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
3589                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3590                 /* IP1_3_0 [4] */
3591                 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
3592                 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
3593                 0, 0, 0, 0, 0, 0, 0, 0, 0, }
3594         },
3595         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3596                              3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
3597                 /* IP2_31_29 [3] */
3598                 0, 0, 0, 0, 0, 0, 0, 0,
3599                 /* IP2_28_26 [3] */
3600                 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
3601                 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
3602                 /* IP2_25_22 [4] */
3603                 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
3604                 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
3605                 0, 0, 0, 0, 0, 0, 0, 0,
3606                 /* IP2_21_18 [4] */
3607                 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
3608                 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
3609                 0, 0, 0, 0, 0, 0, 0, 0,
3610                 /* IP2_17_15 [3] */
3611                 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
3612                 0, 0, 0, 0,
3613                 /* IP2_14_12 [3] */
3614                 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
3615                 /* IP2_11_9 [3] */
3616                 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
3617                 /* IP2_8_6 [3] */
3618                 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
3619                 /* IP2_5_3 [3] */
3620                 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
3621                 /* IP2_2_0 [3] */
3622                 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
3623         },
3624         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3625                              3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
3626                 /* IP3_31_29 [3] */
3627                 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
3628                 0, 0, 0,
3629                 /* IP3_28_26 [3] */
3630                 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
3631                 0, 0, 0, 0,
3632                 /* IP3_25_23 [3] */
3633                 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
3634                 /* IP3_22_20 [3] */
3635                 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
3636                 /* IP3_19_18 [2] */
3637                 FN_A16, FN_ATAWR1_N, 0, 0,
3638                 /* IP3_17_15 [3] */
3639                 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
3640                 0, 0, 0, 0,
3641                 /* IP3_14_12 [3] */
3642                 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
3643                 0, 0, 0, 0,
3644                 /* IP3_11_8 [4] */
3645                 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
3646                 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
3647                 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
3648                 /* IP3_7_4 [4] */
3649                 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
3650                 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
3651                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3652                 /* IP3_3_0 [4] */
3653                 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
3654                 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
3655                 0, 0, 0, 0, 0, 0, 0, 0, }
3656         },
3657         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3658                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3659                 /* IP4_31_30 [2] */
3660                 0, 0, 0, 0,
3661                 /* IP4_29_27 [3] */
3662                 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
3663                 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
3664                 /* IP4_26_24 [3] */
3665                 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
3666                 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
3667                 /* IP4_23_21 [3] */
3668                 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
3669                 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
3670                 /* IP4_20_18 [3] */
3671                 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
3672                 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
3673                 /* IP4_17_15 [3] */
3674                 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
3675                 0, 0, 0,
3676                 /* IP4_14_12 [3] */
3677                 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
3678                 FN_VI2_FIELD_B, 0, 0,
3679                 /* IP4_11_9 [3] */
3680                 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
3681                 FN_VI2_CLKENB_B, 0, 0,
3682                 /* IP4_8_6 [3] */
3683                 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
3684                 /* IP4_5_3 [3] */
3685                 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
3686                 /* IP4_2_0 [3] */
3687                 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
3688                 }
3689         },
3690         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3691                              2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
3692                 /* IP5_31_30 [2] */
3693                 0, 0, 0, 0,
3694                 /* IP5_29_27 [3] */
3695                 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
3696                 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
3697                 /* IP5_26_24 [3] */
3698                 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
3699                 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
3700                 FN_MSIOF0_SCK_B, 0,
3701                 /* IP5_23_21 [3] */
3702                 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
3703                 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
3704                 FN_IERX_C, 0,
3705                 /* IP5_20_18 [3] */
3706                 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
3707                 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
3708                 /* IP5_17_15 [3] */
3709                 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
3710                 FN_INTC_IRQ4_N, 0, 0,
3711                 /* IP5_14_13 [2] */
3712                 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
3713                 /* IP5_12_10 [3] */
3714                 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
3715                 0, 0,
3716                 /* IP5_9_6 [4] */
3717                 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
3718                 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
3719                 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
3720                 /* IP5_5_3 [3] */
3721                 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
3722                 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
3723                 FN_INTC_EN0_N, FN_I2C1_SCL,
3724                 /* IP5_2_0 [3] */
3725                 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
3726                 FN_VI2_R3, 0, 0, }
3727         },
3728         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3729                              3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
3730                 /* IP6_31_29 [3] */
3731                 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
3732                 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
3733                 /* IP6_28_26 [3] */
3734                 FN_ETH_LINK, 0, FN_HTX0_E,
3735                 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
3736                 /* IP6_25_23 [3] */
3737                 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
3738                 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
3739                 /* IP6_22_20 [3] */
3740                 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
3741                 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
3742                 /* IP6_19_17 [3] */
3743                 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
3744                 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
3745                 /* IP6_16_14 [3] */
3746                 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
3747                 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
3748                 FN_I2C2_SCL_E, 0,
3749                 /* IP6_13_11 [3] */
3750                 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
3751                 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
3752                 /* IP6_10_9 [2] */
3753                 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
3754                 /* IP6_8_6 [3] */
3755                 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
3756                 FN_SSI_SDATA8_C, 0, 0, 0,
3757                 /* IP6_5_3 [3] */
3758                 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
3759                 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
3760                 /* IP6_2_0 [3] */
3761                 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
3762                 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
3763         },
3764         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3765                              1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
3766                 /* IP7_31 [1] */
3767                 0, 0,
3768                 /* IP7_30_29 [2] */
3769                 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
3770                 /* IP7_28_27 [2] */
3771                 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
3772                 /* IP7_26_25 [2] */
3773                 FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
3774                 /* IP7_24_22 [3] */
3775                 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
3776                 0, 0, 0,
3777                 /* IP7_21_19 [3] */
3778                 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
3779                 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
3780                 /* IP7_18_16 [3] */
3781                 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
3782                 FN_GLO_SS_C, 0, 0, 0,
3783                 /* IP7_15_13 [3] */
3784                 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
3785                 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
3786                 /* IP7_12_10 [3] */
3787                 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
3788                 FN_GLO_SCLK_C, 0, 0, 0,
3789                 /* IP7_9_8 [2] */
3790                 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
3791                 /* IP7_7_6 [2] */
3792                 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
3793                 /* IP7_5_3 [3] */
3794                 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
3795                 /* IP7_2_0 [3] */
3796                 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
3797                 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
3798         },
3799         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3800                              1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
3801                              2, 2, 2, 2, 2, 2, 2) {
3802                 /* IP8_31 [1] */
3803                 0, 0,
3804                 /* IP8_30_29 [2] */
3805                 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
3806                 /* IP8_28 [1] */
3807                 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
3808                 /* IP8_27 [1] */
3809                 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
3810                 /* IP8_26 [1] */
3811                 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
3812                 /* IP8_25_24 [2] */
3813                 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
3814                 FN_AVB_MAGIC, 0,
3815                 /* IP8_23_22 [2] */
3816                 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
3817                 /* IP8_21_20 [2] */
3818                 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
3819                 /* IP8_19_18 [2] */
3820                 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
3821                 /* IP8_17_16 [2] */
3822                 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
3823                 /* IP8_15_14 [2] */
3824                 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
3825                 /* IP8_13_12 [2] */
3826                 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
3827                 /* IP8_11_10 [2] */
3828                 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
3829                 /* IP8_9_8 [2] */
3830                 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
3831                 /* IP8_7_6 [2] */
3832                 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
3833                 /* IP8_5_4 [2] */
3834                 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
3835                 /* IP8_3_2 [2] */
3836                 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
3837                 /* IP8_1_0 [2] */
3838                 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
3839         },
3840         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3841                              4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
3842                 /* IP9_31_28 [4] */
3843                 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
3844                 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
3845                 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
3846                 /* IP9_27_26 [2] */
3847                 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
3848                 /* IP9_25_24 [2] */
3849                 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
3850                 /* IP9_23_22 [2] */
3851                 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
3852                 /* IP9_21_20 [2] */
3853                 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
3854                 /* IP9_19_18 [2] */
3855                 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
3856                 /* IP9_17_16 [2] */
3857                 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
3858                 /* IP9_15_12 [4] */
3859                 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
3860                 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
3861                 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
3862                 /* IP9_11_8 [4] */
3863                 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
3864                 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
3865                 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
3866                 /* IP9_7_6 [2] */
3867                 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
3868                 /* IP9_5_4 [2] */
3869                 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
3870                 /* IP9_3_2 [2] */
3871                 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
3872                 /* IP9_1_0 [2] */
3873                 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
3874         },
3875         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3876                              2, 4, 3, 4, 4, 4, 4, 3, 4) {
3877                 /* IP10_31_30 [2] */
3878                 0, 0, 0, 0,
3879                 /* IP10_29_26 [4] */
3880                 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
3881                 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
3882                 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
3883                 /* IP10_25_23 [3] */
3884                 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
3885                 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
3886                 /* IP10_22_19 [4] */
3887                 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
3888                 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
3889                 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
3890                 /* IP10_18_15 [4] */
3891                 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
3892                 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
3893                 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
3894                 0, 0, 0, 0, 0, 0,
3895                 /* IP10_14_11 [4] */
3896                 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
3897                 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
3898                 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
3899                 0, 0, 0, 0, 0, 0, 0,
3900                 /* IP10_10_7 [4] */
3901                 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
3902                 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
3903                 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
3904                 0, 0, 0, 0, 0, 0, 0,
3905                 /* IP10_6_4 [3] */
3906                 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
3907                 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
3908                 FN_VI3_DATA0_B, 0,
3909                 /* IP10_3_0 [4] */
3910                 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
3911                 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
3912                 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
3913         },
3914         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
3915                              2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
3916                 /* IP11_31_30 [2] */
3917                 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
3918                 /* IP11_29_27 [3] */
3919                 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
3920                 0, 0, 0,
3921                 /* IP11_26_24 [3] */
3922                 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
3923                 0, 0, 0,
3924                 /* IP11_23_22 [2] */
3925                 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
3926                 /* IP11_21_18 [4] */
3927                 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
3928                 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
3929                 /* IP11_17_15 [3] */
3930                 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
3931                 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
3932                 /* IP11_14_13 [2] */
3933                 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
3934                 /* IP11_12_11 [2] */
3935                 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
3936                 /* IP11_10_9 [2] */
3937                 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
3938                 /* IP11_8_7 [2] */
3939                 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
3940                 /* IP11_6_5 [2] */
3941                 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
3942                 /* IP11_4 [1] */
3943                 FN_SD3_CLK, FN_MMC1_CLK,
3944                 /* IP11_3_0 [4] */
3945                 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
3946                 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
3947                 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
3948         },
3949         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
3950                              1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
3951                 /* IP12_31 [1] */
3952                 0, 0,
3953                 /* IP12_30_28 [3] */
3954                 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
3955                 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
3956                 FN_CAN_DEBUGOUT4, 0, 0,
3957                 /* IP12_27_25 [3] */
3958                 FN_SSI_SCK5, FN_SCIFB1_SCK,
3959                 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
3960                 FN_CAN_DEBUGOUT3, 0, 0,
3961                 /* IP12_24_23 [2] */
3962                 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
3963                 FN_CAN_DEBUGOUT2,
3964                 /* IP12_22_20 [3] */
3965                 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
3966                 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
3967                 /* IP12_19_17 [3] */
3968                 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
3969                 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
3970                 /* IP12_16_14 [3] */
3971                 FN_SSI_SDATA3, FN_STP_ISCLK_0,
3972                 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
3973                 /* IP12_13_11 [3] */
3974                 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
3975                 FN_CAN_STEP0, 0, 0, 0,
3976                 /* IP12_10_8 [3] */
3977                 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
3978                 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
3979                 /* IP12_7_6 [2] */
3980                 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
3981                 /* IP12_5_4 [2] */
3982                 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
3983                 /* IP12_3_2 [2] */
3984                 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
3985                 /* IP12_1_0 [2] */
3986                 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
3987         },
3988         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
3989                              1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
3990                 /* IP13_31 [1] */
3991                 0, 0,
3992                 /* IP13_30_29 [2] */
3993                 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
3994                 /* IP13_28_26 [3] */
3995                 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
3996                 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
3997                 /* IP13_25_23 [3] */
3998                 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
3999                 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
4000                 /* IP13_22_19 [4] */
4001                 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
4002                 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
4003                 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
4004                 /* IP13_18_16 [3] */
4005                 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
4006                 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
4007                 /* IP13_15_13 [3] */
4008                 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
4009                 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
4010                 /* IP13_12_10 [3] */
4011                 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
4012                 FN_CAN_DEBUGOUT8, 0, 0,
4013                 /* IP13_9_7 [3] */
4014                 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
4015                 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
4016                 /* IP13_6_3 [4] */
4017                 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
4018                 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
4019                 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
4020                 /* IP13_2_0 [3] */
4021                 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
4022                 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
4023         },
4024         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
4025                              1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
4026                 /* IP14_30 [1] */
4027                 0, 0,
4028                 /* IP14_30_28 [3] */
4029                 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
4030                 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
4031                 FN_HRTS0_N_C, 0,
4032                 /* IP14_27_25 [3] */
4033                 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
4034                 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
4035                 /* IP14_24_22 [3] */
4036                 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
4037                 FN_LCDOUT9, 0, 0, 0,
4038                 /* IP14_21_19 [3] */
4039                 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
4040                 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
4041                 /* IP14_18_16 [3] */
4042                 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
4043                 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
4044                 /* IP14_15_12 [4] */
4045                 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
4046                 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
4047                 0, 0, 0, 0, 0, 0, 0,
4048                 /* IP14_11_9 [3] */
4049                 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
4050                 0, 0, 0,
4051                 /* IP14_8_6 [3] */
4052                 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
4053                 0, 0, 0,
4054                 /* IP14_5_3 [3] */
4055                 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
4056                 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
4057                 /* IP14_2_0 [3] */
4058                 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
4059                 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
4060                 FN_REMOCON, 0, }
4061         },
4062         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
4063                              2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
4064                 /* IP15_31_30 [2] */
4065                 0, 0, 0, 0,
4066                 /* IP15_29_28 [2] */
4067                 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
4068                 /* IP15_27_26 [2] */
4069                 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
4070                 /* IP15_25_23 [3] */
4071                 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
4072                 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
4073                 /* IP15_22_20 [3] */
4074                 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
4075                 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
4076                 /* IP15_19_18 [2] */
4077                 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
4078                 /* IP15_17_16 [2] */
4079                 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
4080                 /* IP15_15_14 [2] */
4081                 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
4082                 /* IP15_13_12 [2] */
4083                 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
4084                 /* IP15_11_9 [3] */
4085                 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
4086                 0, 0, 0,
4087                 /* IP15_8_6 [3] */
4088                 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
4089                 FN_IIC2_SDA, FN_I2C2_SDA, 0,
4090                 /* IP15_5_3 [3] */
4091                 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
4092                 FN_IIC2_SCL, FN_I2C2_SCL, 0,
4093                 /* IP15_2_0 [3] */
4094                 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
4095                 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
4096         },
4097         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
4098                              4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
4099                 /* IP16_31_28 [4] */
4100                 0, 0, 0, 0, 0, 0, 0, 0,
4101                 0, 0, 0, 0, 0, 0, 0, 0,
4102                 /* IP16_27_24 [4] */
4103                 0, 0, 0, 0, 0, 0, 0, 0,
4104                 0, 0, 0, 0, 0, 0, 0, 0,
4105                 /* IP16_23_20 [4] */
4106                 0, 0, 0, 0, 0, 0, 0, 0,
4107                 0, 0, 0, 0, 0, 0, 0, 0,
4108                 /* IP16_19_16 [4] */
4109                 0, 0, 0, 0, 0, 0, 0, 0,
4110                 0, 0, 0, 0, 0, 0, 0, 0,
4111                 /* IP16_15_12 [4] */
4112                 0, 0, 0, 0, 0, 0, 0, 0,
4113                 0, 0, 0, 0, 0, 0, 0, 0,
4114                 /* IP16_11_8 [4] */
4115                 0, 0, 0, 0, 0, 0, 0, 0,
4116                 0, 0, 0, 0, 0, 0, 0, 0,
4117                 /* IP16_7 [1] */
4118                 FN_USB1_OVC, FN_TCLK1_B,
4119                 /* IP16_6 [1] */
4120                 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
4121                 /* IP16_5_3 [3] */
4122                 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
4123                 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
4124                 /* IP16_2_0 [3] */
4125                 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
4126                 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
4127         },
4128         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4129                              3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
4130                              2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
4131                 /* SEL_SCIF1 [3] */
4132                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
4133                 FN_SEL_SCIF1_4, 0, 0, 0,
4134                 /* SEL_SCIFB [2] */
4135                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
4136                 /* SEL_SCIFB2 [2] */
4137                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
4138                 /* SEL_SCIFB1 [3] */
4139                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
4140                 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
4141                 FN_SEL_SCIFB1_6, 0,
4142                 /* SEL_SCIFA1 [2] */
4143                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
4144                 FN_SEL_SCIFA1_3,
4145                 /* SEL_SCIF0 [1] */
4146                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
4147                 /* SEL_SCIFA [1] */
4148                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
4149                 /* SEL_SOF1 [1] */
4150                 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
4151                 /* SEL_SSI7 [2] */
4152                 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
4153                 /* SEL_SSI6 [1] */
4154                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
4155                 /* SEL_SSI5 [2] */
4156                 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
4157                 /* SEL_VI3 [1] */
4158                 FN_SEL_VI3_0, FN_SEL_VI3_1,
4159                 /* SEL_VI2 [1] */
4160                 FN_SEL_VI2_0, FN_SEL_VI2_1,
4161                 /* SEL_VI1 [1] */
4162                 FN_SEL_VI1_0, FN_SEL_VI1_1,
4163                 /* SEL_VI0 [1] */
4164                 FN_SEL_VI0_0, FN_SEL_VI0_1,
4165                 /* SEL_TSIF1 [2] */
4166                 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
4167                 /* RESERVED [1] */
4168                 0, 0,
4169                 /* SEL_LBS [1] */
4170                 FN_SEL_LBS_0, FN_SEL_LBS_1,
4171                 /* SEL_TSIF0 [2] */
4172                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4173                 /* SEL_SOF3 [1] */
4174                 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
4175                 /* SEL_SOF0 [1] */
4176                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
4177         },
4178         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4179                              3, 1, 1, 1, 2, 1, 2, 1, 2,
4180                              1, 1, 1, 3, 3, 2, 3, 2, 2) {
4181                 /* RESERVED [3] */
4182                 0, 0, 0, 0, 0, 0, 0, 0,
4183                 /* SEL_TMU1 [1] */
4184                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
4185                 /* SEL_HSCIF1 [1] */
4186                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
4187                 /* SEL_SCIFCLK [1] */
4188                 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
4189                 /* SEL_CAN0 [2] */
4190                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4191                 /* SEL_CANCLK [1] */
4192                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
4193                 /* SEL_SCIFA2 [2] */
4194                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
4195                 /* SEL_CAN1 [1] */
4196                 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
4197                 /* RESERVED [2] */
4198                 0, 0, 0, 0,
4199                 /* SEL_SCIF2 [1] */
4200                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
4201                 /* SEL_ADI [1] */
4202                 FN_SEL_ADI_0, FN_SEL_ADI_1,
4203                 /* SEL_SSP [1] */
4204                 FN_SEL_SSP_0, FN_SEL_SSP_1,
4205                 /* SEL_FM [3] */
4206                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
4207                 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
4208                 /* SEL_HSCIF0 [3] */
4209                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
4210                 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
4211                 /* SEL_GPS [2] */
4212                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
4213                 /* RESERVED [3] */
4214                 0, 0, 0, 0, 0, 0, 0, 0,
4215                 /* SEL_SIM [2] */
4216                 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
4217                 /* SEL_SSI8 [2] */
4218                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
4219         },
4220         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4221                              1, 1, 2, 4, 4, 2, 2,
4222                              4, 2, 3, 2, 3, 2) {
4223                 /* SEL_IICDVFS [1] */
4224                 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
4225                 /* SEL_IIC0 [1] */
4226                 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
4227                 /* RESERVED [2] */
4228                 0, 0, 0, 0,
4229                 /* RESERVED [4] */
4230                 0, 0, 0, 0, 0, 0, 0, 0,
4231                 0, 0, 0, 0, 0, 0, 0, 0,
4232                 /* RESERVED [4] */
4233                 0, 0, 0, 0, 0, 0, 0, 0,
4234                 0, 0, 0, 0, 0, 0, 0, 0,
4235                 /* RESERVED [2] */
4236                 0, 0, 0, 0,
4237                 /* SEL_IEB [2] */
4238                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
4239                 /* RESERVED [4] */
4240                 0, 0, 0, 0, 0, 0, 0, 0,
4241                 0, 0, 0, 0, 0, 0, 0, 0,
4242                 /* RESERVED [2] */
4243                 0, 0, 0, 0,
4244                 /* SEL_IIC2 [3] */
4245                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
4246                 FN_SEL_IIC2_4, 0, 0, 0,
4247                 /* SEL_IIC1 [2] */
4248                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
4249                 /* SEL_I2C2 [3] */
4250                 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
4251                 FN_SEL_I2C2_4, 0, 0, 0,
4252                 /* SEL_I2C1 [2] */
4253                 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
4254         },
4255         { },
4256 };
4257
4258 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
4259         .name = "r8a77900_pfc",
4260         .unlock_reg = 0xe6060000, /* PMMR */
4261
4262         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4263
4264         .pins = pinmux_pins,
4265         .nr_pins = ARRAY_SIZE(pinmux_pins),
4266         .groups = pinmux_groups,
4267         .nr_groups = ARRAY_SIZE(pinmux_groups),
4268         .functions = pinmux_functions,
4269         .nr_functions = ARRAY_SIZE(pinmux_functions),
4270
4271         .cfg_regs = pinmux_config_regs,
4272
4273         .gpio_data = pinmux_data,
4274         .gpio_data_size = ARRAY_SIZE(pinmux_data),
4275 };