2 * SuperH Pin Function Controller support.
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
12 #define DRV_NAME "sh-pfc"
14 #include <linux/bitops.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
29 static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev)
32 unsigned int num_windows = 0;
33 unsigned int num_irqs = 0;
34 struct sh_pfc_window *windows;
35 unsigned int *irqs = NULL;
39 /* Count the MEM and IRQ resources. */
40 for (i = 0; i < pdev->num_resources; ++i) {
41 switch (resource_type(&pdev->resource[i])) {
55 /* Allocate memory windows and IRQs arrays. */
56 windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
61 pfc->num_windows = num_windows;
62 pfc->windows = windows;
65 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
70 pfc->num_irqs = num_irqs;
75 for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) {
76 switch (resource_type(res)) {
78 windows->phys = res->start;
79 windows->size = resource_size(res);
80 windows->virt = devm_ioremap_resource(pfc->dev, res);
81 if (IS_ERR(windows->virt))
95 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
96 unsigned long address)
98 struct sh_pfc_window *window;
101 /* scan through physical windows and convert address */
102 for (i = 0; i < pfc->num_windows; i++) {
103 window = pfc->windows + i;
105 if (address < window->phys)
108 if (address >= (window->phys + window->size))
111 return window->virt + (address - window->phys);
118 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
123 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
124 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
126 if (pin <= range->end)
127 return pin >= range->start
128 ? offset + pin - range->start : -1;
130 offset += range->end - range->start + 1;
136 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
138 if (enum_id < r->begin)
141 if (enum_id > r->end)
147 unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
148 unsigned long reg_width)
152 return ioread8(mapped_reg);
154 return ioread16(mapped_reg);
156 return ioread32(mapped_reg);
163 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
168 iowrite8(data, mapped_reg);
171 iowrite16(data, mapped_reg);
174 iowrite32(data, mapped_reg);
181 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
182 const struct pinmux_cfg_reg *crp,
183 unsigned long in_pos,
184 void __iomem **mapped_regp,
185 unsigned long *maskp,
190 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
192 if (crp->field_width) {
193 *maskp = (1 << crp->field_width) - 1;
194 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
196 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
197 *posp = crp->reg_width;
198 for (k = 0; k <= in_pos; k++)
199 *posp -= crp->var_field_width[k];
203 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
204 const struct pinmux_cfg_reg *crp,
205 unsigned long field, unsigned long value)
207 void __iomem *mapped_reg;
208 unsigned long mask, pos, data;
210 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
212 dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
213 "r_width = %ld, f_width = %ld\n",
214 crp->reg, value, field, crp->reg_width, crp->field_width);
216 mask = ~(mask << pos);
217 value = value << pos;
219 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
223 if (pfc->info->unlock_reg)
224 sh_pfc_write_raw_reg(
225 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
228 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
231 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
232 const struct pinmux_cfg_reg **crp, int *fieldp,
235 const struct pinmux_cfg_reg *config_reg;
236 unsigned long r_width, f_width, curr_width, ncomb;
237 unsigned int k, m, n, pos, bit_pos;
241 config_reg = pfc->info->cfg_regs + k;
243 r_width = config_reg->reg_width;
244 f_width = config_reg->field_width;
251 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
253 curr_width = f_width;
255 curr_width = config_reg->var_field_width[m];
257 ncomb = 1 << curr_width;
258 for (n = 0; n < ncomb; n++) {
259 if (config_reg->enum_ids[pos + n] == enum_id) {
275 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
278 const u16 *data = pfc->info->gpio_data;
282 *enum_idp = data[pos + 1];
286 for (k = 0; k < pfc->info->gpio_data_size; k++) {
287 if (data[k] == mark) {
288 *enum_idp = data[k + 1];
293 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
298 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
300 const struct pinmux_cfg_reg *cr = NULL;
302 const struct pinmux_range *range;
303 int in_range, pos, field, value;
306 switch (pinmux_type) {
307 case PINMUX_TYPE_GPIO:
308 case PINMUX_TYPE_FUNCTION:
312 case PINMUX_TYPE_OUTPUT:
313 range = &pfc->info->output;
316 case PINMUX_TYPE_INPUT:
317 range = &pfc->info->input;
329 /* Iterate over all the configuration fields we need to update. */
331 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
338 /* Check if the configuration field selects a function. If it
339 * doesn't, skip the field if it's not applicable to the
340 * requested pinmux type.
342 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
344 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
345 /* Functions are allowed to modify all
349 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
350 /* Input/output types can only modify fields
351 * that correspond to their respective ranges.
353 in_range = sh_pfc_enum_in_range(enum_id, range);
356 * special case pass through for fixed
357 * input-only or output-only pins without
358 * function enum register association.
360 if (in_range && enum_id == range->force)
363 /* GPIOs are only allowed to modify function fields. */
369 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
373 sh_pfc_write_config_reg(pfc, cr, field, value);
379 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
381 struct sh_pfc_pin_range *range;
382 unsigned int nr_ranges;
385 if (pfc->info->pins[0].pin == (u16)-1) {
386 /* Pin number -1 denotes that the SoC doesn't report pin numbers
387 * in its pin arrays yet. Consider the pin numbers range as
388 * continuous and allocate a single range.
391 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
393 if (pfc->ranges == NULL)
396 pfc->ranges->start = 0;
397 pfc->ranges->end = pfc->info->nr_pins - 1;
398 pfc->nr_gpio_pins = pfc->info->nr_pins;
403 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
404 * be sorted by pin numbers, and pins without a GPIO port must come
407 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
408 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
412 pfc->nr_ranges = nr_ranges;
413 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
415 if (pfc->ranges == NULL)
419 range->start = pfc->info->pins[0].pin;
421 for (i = 1; i < pfc->info->nr_pins; ++i) {
422 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
425 range->end = pfc->info->pins[i-1].pin;
426 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
427 pfc->nr_gpio_pins = range->end + 1;
430 range->start = pfc->info->pins[i].pin;
433 range->end = pfc->info->pins[i-1].pin;
434 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
435 pfc->nr_gpio_pins = range->end + 1;
441 static const struct of_device_id sh_pfc_of_table[] = {
442 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
444 .compatible = "renesas,pfc-r8a73a4",
445 .data = &r8a73a4_pinmux_info,
448 #ifdef CONFIG_PINCTRL_PFC_R8A7740
450 .compatible = "renesas,pfc-r8a7740",
451 .data = &r8a7740_pinmux_info,
454 #ifdef CONFIG_PINCTRL_PFC_R8A7778
456 .compatible = "renesas,pfc-r8a7778",
457 .data = &r8a7778_pinmux_info,
460 #ifdef CONFIG_PINCTRL_PFC_R8A7779
462 .compatible = "renesas,pfc-r8a7779",
463 .data = &r8a7779_pinmux_info,
466 #ifdef CONFIG_PINCTRL_PFC_R8A7790
468 .compatible = "renesas,pfc-r8a7790",
469 .data = &r8a7790_pinmux_info,
472 #ifdef CONFIG_PINCTRL_PFC_R8A7791
474 .compatible = "renesas,pfc-r8a7791",
475 .data = &r8a7791_pinmux_info,
478 #ifdef CONFIG_PINCTRL_PFC_SH7372
480 .compatible = "renesas,pfc-sh7372",
481 .data = &sh7372_pinmux_info,
484 #ifdef CONFIG_PINCTRL_PFC_SH73A0
486 .compatible = "renesas,pfc-sh73a0",
487 .data = &sh73a0_pinmux_info,
492 MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
495 static int sh_pfc_probe(struct platform_device *pdev)
497 const struct platform_device_id *platid = platform_get_device_id(pdev);
499 struct device_node *np = pdev->dev.of_node;
501 const struct sh_pfc_soc_info *info;
507 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
510 info = platid ? (const void *)platid->driver_data : NULL;
515 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
520 pfc->dev = &pdev->dev;
522 ret = sh_pfc_map_resources(pfc, pdev);
523 if (unlikely(ret < 0))
526 spin_lock_init(&pfc->lock);
528 if (info->ops && info->ops->init) {
529 ret = info->ops->init(pfc);
534 pinctrl_provide_dummies();
536 ret = sh_pfc_init_ranges(pfc);
541 * Initialize pinctrl bindings first
543 ret = sh_pfc_register_pinctrl(pfc);
544 if (unlikely(ret != 0))
547 #ifdef CONFIG_GPIO_SH_PFC
551 ret = sh_pfc_register_gpiochip(pfc);
552 if (unlikely(ret != 0)) {
554 * If the GPIO chip fails to come up we still leave the
555 * PFC state as it is, given that there are already
556 * extant users of it that have succeeded by this point.
558 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
562 platform_set_drvdata(pdev, pfc);
564 dev_info(pfc->dev, "%s support registered\n", info->name);
569 if (info->ops && info->ops->exit)
570 info->ops->exit(pfc);
574 static int sh_pfc_remove(struct platform_device *pdev)
576 struct sh_pfc *pfc = platform_get_drvdata(pdev);
578 #ifdef CONFIG_GPIO_SH_PFC
579 sh_pfc_unregister_gpiochip(pfc);
581 sh_pfc_unregister_pinctrl(pfc);
583 if (pfc->info->ops && pfc->info->ops->exit)
584 pfc->info->ops->exit(pfc);
589 static const struct platform_device_id sh_pfc_id_table[] = {
590 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
591 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
593 #ifdef CONFIG_PINCTRL_PFC_R8A7740
594 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
596 #ifdef CONFIG_PINCTRL_PFC_R8A7778
597 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
599 #ifdef CONFIG_PINCTRL_PFC_R8A7779
600 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
602 #ifdef CONFIG_PINCTRL_PFC_R8A7790
603 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
605 #ifdef CONFIG_PINCTRL_PFC_R8A7791
606 { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info },
608 #ifdef CONFIG_PINCTRL_PFC_SH7203
609 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
611 #ifdef CONFIG_PINCTRL_PFC_SH7264
612 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
614 #ifdef CONFIG_PINCTRL_PFC_SH7269
615 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
617 #ifdef CONFIG_PINCTRL_PFC_SH7372
618 { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
620 #ifdef CONFIG_PINCTRL_PFC_SH73A0
621 { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
623 #ifdef CONFIG_PINCTRL_PFC_SH7720
624 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
626 #ifdef CONFIG_PINCTRL_PFC_SH7722
627 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
629 #ifdef CONFIG_PINCTRL_PFC_SH7723
630 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
632 #ifdef CONFIG_PINCTRL_PFC_SH7724
633 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
635 #ifdef CONFIG_PINCTRL_PFC_SH7734
636 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
638 #ifdef CONFIG_PINCTRL_PFC_SH7757
639 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
641 #ifdef CONFIG_PINCTRL_PFC_SH7785
642 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
644 #ifdef CONFIG_PINCTRL_PFC_SH7786
645 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
647 #ifdef CONFIG_PINCTRL_PFC_SHX3
648 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
653 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
655 static struct platform_driver sh_pfc_driver = {
656 .probe = sh_pfc_probe,
657 .remove = sh_pfc_remove,
658 .id_table = sh_pfc_id_table,
661 .owner = THIS_MODULE,
662 .of_match_table = of_match_ptr(sh_pfc_of_table),
666 static int __init sh_pfc_init(void)
668 return platform_driver_register(&sh_pfc_driver);
670 postcore_initcall(sh_pfc_init);
672 static void __exit sh_pfc_exit(void)
674 platform_driver_unregister(&sh_pfc_driver);
676 module_exit(sh_pfc_exit);
678 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
679 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
680 MODULE_LICENSE("GPL v2");