drivers/pinctrl/rockchip/pinctrl_rk3399.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/grf_rk3399.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/periph.h>
  15 #include <asm/arch/clock.h>
  16 #include <dm/pinctrl.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 struct rk3399_pinctrl_priv {
  21         struct rk3399_grf_regs *grf;
  22         struct rk3399_pmugrf_regs *pmugrf;
  23 };
  24
  25 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
  26                 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
  27 {
  28         switch (pwm_id) {
  29         case PERIPH_ID_PWM0:
  30                 rk_clrsetreg(&grf->gpio4c_iomux,
  31                              GRF_GPIO4C2_SEL_MASK,
  32                              GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
  33                 break;
  34         case PERIPH_ID_PWM1:
  35                 rk_clrsetreg(&grf->gpio4c_iomux,
  36                              GRF_GPIO4C6_SEL_MASK,
  37                              GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
  38                 break;
  39         case PERIPH_ID_PWM2:
  40                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
  41                              PMUGRF_GPIO1C3_SEL_MASK,
  42                              PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
  43                 break;
  44         case PERIPH_ID_PWM3:
  45                 if (readl(&pmugrf->soc_con0) & (1 << 5))
  46                         rk_clrsetreg(&pmugrf->gpio1b_iomux,
  47                                      PMUGRF_GPIO1B6_SEL_MASK,
  48                                      PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
  49                 else
  50                         rk_clrsetreg(&pmugrf->gpio0a_iomux,
  51                                      PMUGRF_GPIO0A6_SEL_MASK,
  52                                      PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
  53                 break;
  54         default:
  55                 debug("pwm id = %d iomux error!\n", pwm_id);
  56                 break;
  57         }
  58 }
  59
  60 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
  61                                       struct rk3399_pmugrf_regs *pmugrf,
  62                                       int i2c_id)
  63 {
  64         switch (i2c_id) {
  65         case PERIPH_ID_I2C0:
  66                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
  67                              PMUGRF_GPIO1B7_SEL_MASK,
  68                              PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
  69                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
  70                              PMUGRF_GPIO1C0_SEL_MASK,
  71                              PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
  72                 break;
  73         case PERIPH_ID_I2C1:
  74         case PERIPH_ID_I2C2:
  75         case PERIPH_ID_I2C3:
  76         case PERIPH_ID_I2C4:
  77         case PERIPH_ID_I2C5:
  78         default:
  79                 debug("i2c id = %d iomux error!\n", i2c_id);
  80                 break;
  81         }
  82 }
  83
  84 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
  85 {
  86         switch (lcd_id) {
  87         case PERIPH_ID_LCDC0:
  88                 break;
  89         default:
  90                 debug("lcdc id = %d iomux error!\n", lcd_id);
  91                 break;
  92         }
  93 }
  94
  95 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
  96                                      struct rk3399_pmugrf_regs *pmugrf,
  97                                      enum periph_id spi_id, int cs)
  98 {
  99         switch (spi_id) {
 100         case PERIPH_ID_SPI0:
 101                 switch (cs) {
 102                 case 0:
 103                         rk_clrsetreg(&grf->gpio3a_iomux,
 104                                      GRF_GPIO3A7_SEL_MASK,
 105                                      GRF_SPI0NORCODEC_CSN0
 106                                      << GRF_GPIO3A7_SEL_SHIFT);
 107                         break;
 108                 case 1:
 109                         rk_clrsetreg(&grf->gpio3b_iomux,
 110                                      GRF_GPIO3B0_SEL_MASK,
 111                                      GRF_SPI0NORCODEC_CSN1
 112                                      << GRF_GPIO3B0_SEL_SHIFT);
 113                         break;
 114                 default:
 115                         goto err;
 116                 }
 117                 rk_clrsetreg(&grf->gpio3a_iomux,
 118                              GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
 119                              | GRF_GPIO3A6_SEL_SHIFT,
 120                              GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
 121                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
 122                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
 123                 break;
 124         case PERIPH_ID_SPI1:
 125                 if (cs != 0)
 126                         goto err;
 127                 rk_clrsetreg(&pmugrf->gpio1a_iomux,
 128                              PMUGRF_GPIO1A7_SEL_MASK,
 129                              PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
 130                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 131                              PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
 132                              | PMUGRF_GPIO1B2_SEL_MASK,
 133                              PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
 134                              | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
 135                              | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
 136                 break;
 137         case PERIPH_ID_SPI2:
 138                 if (cs != 0)
 139                         goto err;
 140                 rk_clrsetreg(&grf->gpio2b_iomux,
 141                              GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
 142                              | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
 143                              GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
 144                              | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
 145                              | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
 146                              | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
 147                 break;
 148         case PERIPH_ID_SPI5:
 149                 if (cs != 0)
 150                         goto err;
 151                 rk_clrsetreg(&grf->gpio2c_iomux,
 152                              GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
 153                              | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
 154                              GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
 155                              | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
 156                              | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
 157                              | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
 158                 break;
 159         default:
 160                 printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
 161                 goto err;
 162         }
 163
 164         return 0;
 165 err:
 166         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 167         return -ENOENT;
 168 }
 169
 170 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
 171                                        struct rk3399_pmugrf_regs *pmugrf,
 172                                        int uart_id)
 173 {
 174         switch (uart_id) {
 175         case PERIPH_ID_UART2:
 176                 /* Using channel-C by default */
 177                 rk_clrsetreg(&grf->gpio4c_iomux,
 178                              GRF_GPIO4C3_SEL_MASK,
 179                              GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 180                 rk_clrsetreg(&grf->gpio4c_iomux,
 181                              GRF_GPIO4C4_SEL_MASK,
 182                              GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 183                 break;
 184         case PERIPH_ID_UART0:
 185         case PERIPH_ID_UART1:
 186         case PERIPH_ID_UART3:
 187         case PERIPH_ID_UART4:
 188         default:
 189                 debug("uart id = %d iomux error!\n", uart_id);
 190                 break;
 191         }
 192 }
 193
 194 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
 195 {
 196         switch (mmc_id) {
 197         case PERIPH_ID_EMMC:
 198                 break;
 199         case PERIPH_ID_SDCARD:
 200                 rk_clrsetreg(&grf->gpio4b_iomux,
 201                              GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
 202                              | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
 203                              | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
 204                              GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
 205                              | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
 206                              | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
 207                              | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
 208                              | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
 209                              | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
 210                 break;
 211         default:
 212                 debug("mmc id = %d iomux error!\n", mmc_id);
 213                 break;
 214         }
 215 }
 216
 217 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 218 static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
 219 {
 220         rk_clrsetreg(&grf->gpio3a_iomux,
 221                      GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
 222                      GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
 223                      GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
 224                      GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
 225                      GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
 226                      GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
 227                      GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
 228                      GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
 229                      GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
 230                      GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
 231                      GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
 232                      GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
 233         rk_clrsetreg(&grf->gpio3b_iomux,
 234                      GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
 235                                             GRF_GPIO3B3_SEL_MASK |
 236                      GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
 237                      GRF_GPIO3B6_SEL_MASK,
 238                      GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
 239                      GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
 240                      GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
 241                      GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
 242                      GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
 243                      GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
 244         rk_clrsetreg(&grf->gpio3c_iomux,
 245                      GRF_GPIO3C1_SEL_MASK,
 246                      GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
 247 }
 248 #endif
 249
 250 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 251 {
 252         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 253
 254         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 255         switch (func) {
 256         case PERIPH_ID_PWM0:
 257         case PERIPH_ID_PWM1:
 258         case PERIPH_ID_PWM2:
 259         case PERIPH_ID_PWM3:
 260         case PERIPH_ID_PWM4:
 261                 pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
 262                 break;
 263         case PERIPH_ID_I2C0:
 264         case PERIPH_ID_I2C1:
 265         case PERIPH_ID_I2C2:
 266         case PERIPH_ID_I2C3:
 267         case PERIPH_ID_I2C4:
 268         case PERIPH_ID_I2C5:
 269                 pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
 270                 break;
 271         case PERIPH_ID_SPI0:
 272         case PERIPH_ID_SPI1:
 273         case PERIPH_ID_SPI2:
 274         case PERIPH_ID_SPI3:
 275         case PERIPH_ID_SPI4:
 276         case PERIPH_ID_SPI5:
 277                 pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
 278                 break;
 279         case PERIPH_ID_UART0:
 280         case PERIPH_ID_UART1:
 281         case PERIPH_ID_UART2:
 282         case PERIPH_ID_UART3:
 283         case PERIPH_ID_UART4:
 284                 pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
 285                 break;
 286         case PERIPH_ID_LCDC0:
 287         case PERIPH_ID_LCDC1:
 288                 pinctrl_rk3399_lcdc_config(priv->grf, func);
 289                 break;
 290         case PERIPH_ID_SDMMC0:
 291         case PERIPH_ID_SDMMC1:
 292                 pinctrl_rk3399_sdmmc_config(priv->grf, func);
 293                 break;
 294 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 295         case PERIPH_ID_GMAC:
 296                 pinctrl_rk3399_gmac_config(priv->grf, func);
 297                 break;
 298 #endif
 299         default:
 300                 return -EINVAL;
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 307                                         struct udevice *periph)
 308 {
 309 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 310         u32 cell[3];
 311         int ret;
 312
 313         ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
 314                                    "interrupts", cell, ARRAY_SIZE(cell));
 315         if (ret < 0)
 316                 return -EINVAL;
 317
 318         switch (cell[1]) {
 319         case 68:
 320                 return PERIPH_ID_SPI0;
 321         case 53:
 322                 return PERIPH_ID_SPI1;
 323         case 52:
 324                 return PERIPH_ID_SPI2;
 325         case 132:
 326                 return PERIPH_ID_SPI5;
 327         case 57:
 328                 return PERIPH_ID_I2C0;
 329         case 59: /* Note strange order */
 330                 return PERIPH_ID_I2C1;
 331         case 35:
 332                 return PERIPH_ID_I2C2;
 333         case 34:
 334                 return PERIPH_ID_I2C3;
 335         case 56:
 336                 return PERIPH_ID_I2C4;
 337         case 38:
 338                 return PERIPH_ID_I2C5;
 339         case 65:
 340                 return PERIPH_ID_SDMMC1;
 341 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 342         case 12:
 343                 return PERIPH_ID_GMAC;
 344 #endif
 345         }
 346 #endif
 347         return -ENOENT;
 348 }
 349
 350 static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
 351                                            struct udevice *periph)
 352 {
 353         int func;
 354
 355         func = rk3399_pinctrl_get_periph_id(dev, periph);
 356         if (func < 0)
 357                 return func;
 358
 359         return rk3399_pinctrl_request(dev, func, 0);
 360 }
 361
 362 static struct pinctrl_ops rk3399_pinctrl_ops = {
 363         .set_state_simple       = rk3399_pinctrl_set_state_simple,
 364         .request        = rk3399_pinctrl_request,
 365         .get_periph_id  = rk3399_pinctrl_get_periph_id,
 366 };
 367
 368 static int rk3399_pinctrl_probe(struct udevice *dev)
 369 {
 370         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 371         int ret = 0;
 372
 373         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 374         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 375         debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
 376
 377         return ret;
 378 }
 379
 380 static const struct udevice_id rk3399_pinctrl_ids[] = {
 381         { .compatible = "rockchip,rk3399-pinctrl" },
 382         { }
 383 };
 384
 385 U_BOOT_DRIVER(pinctrl_rk3399) = {
 386         .name           = "rockchip_rk3399_pinctrl",
 387         .id             = UCLASS_PINCTRL,
 388         .of_match       = rk3399_pinctrl_ids,
 389         .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
 390         .ops            = &rk3399_pinctrl_ops,
 391 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 392         .bind           = dm_scan_fdt_dev,
 393 #endif
 394         .probe          = rk3399_pinctrl_probe,
 395 };