2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/grf_rk3368.h>
17 #include <asm/arch/periph.h>
18 #include <dm/pinctrl.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* PMUGRF_GPIO0B_IOMUX */
25 GPIO0B5_MASK = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT),
27 GPIO0B5_SPI2_CSN0 = (2 << GPIO0B5_SHIFT),
30 GPIO0B4_MASK = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT),
32 GPIO0B4_SPI2_CLK = (2 << GPIO0B4_SHIFT),
35 GPIO0B3_MASK = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT),
37 GPIO0B3_SPI2_TXD = (2 << GPIO0B3_SHIFT),
40 GPIO0B2_MASK = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT),
42 GPIO0B2_SPI2_RXD = (2 << GPIO0B2_SHIFT),
48 GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
50 GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
51 GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
52 GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
55 GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
57 GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
58 GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
59 GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
62 GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
64 GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
65 GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
66 GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
69 GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
71 GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
72 GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
73 GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
76 GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
78 GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
79 GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
80 GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
83 GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
85 GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
86 GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
87 GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
90 GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
92 GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
93 GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
94 GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
97 GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
99 GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
100 GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
101 GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
107 GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
109 GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
110 GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
111 GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
114 GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
116 GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
117 GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
118 GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
121 GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
123 GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
124 GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
125 GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
128 GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
130 GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
131 GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
132 GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
135 GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
137 GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
138 GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
139 GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
142 GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
144 GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
145 GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
146 GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
149 GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
151 GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
152 GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
153 GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
156 GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
158 GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
159 GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
160 GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
166 GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
168 GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
169 GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
172 GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
174 GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
175 GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
178 GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
180 GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
181 GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
184 GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
186 GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
187 GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
190 GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
192 GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
193 GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
196 GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
198 GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
201 GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
203 GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
206 GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
208 GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
214 GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
216 GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
219 GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
221 GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
224 GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
226 GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
229 GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
231 GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
234 GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
236 GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
239 GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
241 GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
244 GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
246 GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
249 GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
251 GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
254 /* GRF_GPIO1B_IOMUX */
257 GPIO1B7_MASK = GENMASK(GPIO1B7_SHIFT + 1, GPIO1B7_SHIFT),
259 GPIO1B7_SPI1_CSN0 = (2 << GPIO1B7_SHIFT),
262 GPIO1B6_MASK = GENMASK(GPIO1B6_SHIFT + 1, GPIO1B6_SHIFT),
264 GPIO1B6_SPI1_CLK = (2 << GPIO1B6_SHIFT),
267 /* GRF_GPIO1C_IOMUX */
270 GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
272 GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
273 GPIO1C7_SPI0_TXD = (3 << GPIO1C7_SHIFT),
276 GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
278 GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
279 GPIO1C6_SPI0_RXD = (3 << GPIO1C6_SHIFT),
282 GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
284 GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
287 GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
289 GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
292 GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
294 GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
297 GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
299 GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
302 GPIO1C1_MASK = GENMASK(GPIO1C1_SHIFT + 1, GPIO1C1_SHIFT),
304 GPIO1C1_SPI1_RXD = (2 << GPIO1C1_SHIFT),
307 GPIO1C0_MASK = GENMASK(GPIO1C0_SHIFT + 1, GPIO1C0_SHIFT),
309 GPIO1C0_SPI1_TXD = (2 << GPIO1C0_SHIFT),
312 /* GRF_GPIO1D_IOMUX*/
315 GPIO1D5_MASK = GENMASK(GPIO1D5_SHIFT + 1, GPIO1D5_SHIFT),
317 GPIO1D5_SPI0_CLK = (2 << GPIO1D5_SHIFT),
320 GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
322 GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
325 GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
327 GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
330 GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
332 GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
333 GPIO1D1_SPI0_CSN1 = (3 << GPIO1D1_SHIFT),
336 GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
338 GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
339 GPIO1D0_SPI0_CSN0 = (3 << GPIO1D0_SHIFT),
346 GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
348 GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
351 GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
353 GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
356 GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
358 GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
361 GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
363 GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
366 GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
368 GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
371 GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
373 GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
376 GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
378 GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
381 GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
383 GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
384 GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
390 GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
392 GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
395 GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
397 GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
400 GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
402 GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
405 GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
407 GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
410 GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
412 GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
415 GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
417 GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
420 GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
422 GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
428 GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
430 GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
431 GPIO3D4_SPI1_CNS1 = (2 << GPIO3D4_SHIFT),
434 GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
436 GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
439 GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
441 GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
444 struct rk3368_pinctrl_priv {
445 struct rk3368_grf *grf;
446 struct rk3368_pmu_grf *pmugrf;
449 static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
452 struct rk3368_grf *grf = priv->grf;
453 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
456 case PERIPH_ID_UART2:
457 rk_clrsetreg(&grf->gpio2a_iomux,
458 GPIO2A6_MASK | GPIO2A5_MASK,
459 GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
461 case PERIPH_ID_UART0:
463 case PERIPH_ID_UART1:
465 case PERIPH_ID_UART3:
467 case PERIPH_ID_UART4:
468 rk_clrsetreg(&pmugrf->gpio0d_iomux,
469 GPIO0D0_MASK | GPIO0D1_MASK |
470 GPIO0D2_MASK | GPIO0D3_MASK,
471 GPIO0D0_GPIO | GPIO0D1_GPIO |
472 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
475 debug("uart id = %d iomux error!\n", uart_id);
480 static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv,
483 struct rk3368_grf *grf = priv->grf;
484 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
489 * eMMC can only be connected with 4 bits, when SPI0 is used.
490 * This is all-or-nothing, so we assume that if someone asks us
491 * to configure SPI0, that their eMMC interface is unused or
492 * configured appropriately.
494 rk_clrsetreg(&grf->gpio1d_iomux,
495 GPIO1D0_MASK | GPIO1D1_MASK |
497 GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 |
499 rk_clrsetreg(&grf->gpio1c_iomux,
500 GPIO1C6_MASK | GPIO1C7_MASK,
501 GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD);
505 * We don't implement support for configuring SPI1_CSN#1, as it
506 * conflicts with the GMAC (MAC TX clk-out).
508 rk_clrsetreg(&grf->gpio1b_iomux,
509 GPIO1B6_MASK | GPIO1B7_MASK,
510 GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0);
511 rk_clrsetreg(&grf->gpio1c_iomux,
512 GPIO1C0_MASK | GPIO1C1_MASK,
513 GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD);
516 rk_clrsetreg(&pmugrf->gpio0b_iomux,
517 GPIO0B2_MASK | GPIO0B3_MASK |
518 GPIO0B4_MASK | GPIO0B5_MASK,
519 GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD |
520 GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0);
523 debug("%s: spi id = %d iomux error!\n", __func__, spi_id);
528 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
529 static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
531 rk_clrsetreg(&grf->gpio3b_iomux,
532 GPIO3B0_MASK | GPIO3B1_MASK |
533 GPIO3B2_MASK | GPIO3B5_MASK |
534 GPIO3B6_MASK | GPIO3B7_MASK,
535 GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
536 GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
537 GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
538 rk_clrsetreg(&grf->gpio3c_iomux,
539 GPIO3C0_MASK | GPIO3C1_MASK |
540 GPIO3C2_MASK | GPIO3C3_MASK |
541 GPIO3C4_MASK | GPIO3C5_MASK |
543 GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
544 GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
545 GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
547 rk_clrsetreg(&grf->gpio3d_iomux,
548 GPIO3D0_MASK | GPIO3D1_MASK |
550 GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
555 static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
559 debug("mmc id = %d setting registers!\n", mmc_id);
560 rk_clrsetreg(&grf->gpio1c_iomux,
561 GPIO1C2_MASK | GPIO1C3_MASK |
562 GPIO1C4_MASK | GPIO1C5_MASK |
563 GPIO1C6_MASK | GPIO1C7_MASK,
570 rk_clrsetreg(&grf->gpio1d_iomux,
571 GPIO1D0_MASK | GPIO1D1_MASK |
572 GPIO1D2_MASK | GPIO1D3_MASK,
577 rk_clrsetreg(&grf->gpio2a_iomux,
578 GPIO2A3_MASK | GPIO2A4_MASK,
579 GPIO2A3_EMMC_RSTNOUT |
580 GPIO2A4_EMMC_CLKOUT);
582 case PERIPH_ID_SDCARD:
584 * We assume that the BROM has already set this up
585 * correctly for us and that there's nothing to do
590 debug("mmc id = %d iomux error!\n", mmc_id);
595 static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
597 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
599 debug("%s: func=%d, flags=%x\n", __func__, func, flags);
601 case PERIPH_ID_UART0:
602 case PERIPH_ID_UART1:
603 case PERIPH_ID_UART2:
604 case PERIPH_ID_UART3:
605 case PERIPH_ID_UART4:
606 pinctrl_rk3368_uart_config(priv, func);
611 pinctrl_rk3368_spi_config(priv, func);
614 case PERIPH_ID_SDCARD:
615 pinctrl_rk3368_sdmmc_config(priv->grf, func);
617 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
619 pinctrl_rk3368_gmac_config(priv->grf, func);
629 static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
630 struct udevice *periph)
635 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
641 return PERIPH_ID_UART4;
643 return PERIPH_ID_UART3;
645 return PERIPH_ID_UART2;
647 return PERIPH_ID_UART1;
649 return PERIPH_ID_UART0;
651 return PERIPH_ID_SPI0;
653 return PERIPH_ID_SPI1;
655 return PERIPH_ID_SPI2;
657 return PERIPH_ID_EMMC;
659 return PERIPH_ID_SDCARD;
660 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
662 return PERIPH_ID_GMAC;
669 static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
670 struct udevice *periph)
674 func = rk3368_pinctrl_get_periph_id(dev, periph);
678 return rk3368_pinctrl_request(dev, func, 0);
681 static struct pinctrl_ops rk3368_pinctrl_ops = {
682 .set_state_simple = rk3368_pinctrl_set_state_simple,
683 .request = rk3368_pinctrl_request,
684 .get_periph_id = rk3368_pinctrl_get_periph_id,
687 static int rk3368_pinctrl_probe(struct udevice *dev)
689 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
692 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
693 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
695 debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
700 static const struct udevice_id rk3368_pinctrl_ids[] = {
701 { .compatible = "rockchip,rk3368-pinctrl" },
705 U_BOOT_DRIVER(pinctrl_rk3368) = {
706 .name = "rockchip_rk3368_pinctrl",
707 .id = UCLASS_PINCTRL,
708 .of_match = rk3368_pinctrl_ids,
709 .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
710 .ops = &rk3368_pinctrl_ops,
711 .bind = dm_scan_fdt_dev,
712 .probe = rk3368_pinctrl_probe,