2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/grf_rk3328.h>
14 #include <asm/arch/periph.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR;
22 GPIO0A5_SEL_SHIFT = 10,
23 GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
26 GPIO0A6_SEL_SHIFT = 12,
27 GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
30 GPIO0A7_SEL_SHIFT = 14,
31 GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
32 GPIO0A7_EMMC_DATA0 = 2,
35 GPIO0B0_SEL_SHIFT = 0,
36 GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT,
37 GPIO0B0_GAMC_CLKTXM0 = 1,
39 GPIO0B4_SEL_SHIFT = 8,
40 GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT,
41 GPIO0B4_GAMC_TXENM0 = 1,
44 GPIO0C0_SEL_SHIFT = 0,
45 GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT,
46 GPIO0C0_GAMC_TXD1M0 = 1,
48 GPIO0C1_SEL_SHIFT = 2,
49 GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT,
50 GPIO0C1_GAMC_TXD0M0 = 1,
52 GPIO0C6_SEL_SHIFT = 12,
53 GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT,
54 GPIO0C6_GAMC_TXD2M0 = 1,
56 GPIO0C7_SEL_SHIFT = 14,
57 GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT,
58 GPIO0C7_GAMC_TXD3M0 = 1,
61 GPIO0D0_SEL_SHIFT = 0,
62 GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT,
63 GPIO0D0_GMAC_CLKM0 = 1,
65 GPIO0D6_SEL_SHIFT = 12,
66 GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
68 GPIO0D6_SDMMC0_PWRENM1 = 3,
71 GPIO1A0_SEL_SHIFT = 0,
72 GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
73 GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
76 GPIO1B0_SEL_SHIFT = 0,
77 GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT,
78 GPIO1B0_GMAC_TXD1M1 = 2,
80 GPIO1B1_SEL_SHIFT = 2,
81 GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT,
82 GPIO1B1_GMAC_TXD0M1 = 2,
84 GPIO1B2_SEL_SHIFT = 4,
85 GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT,
86 GPIO1B2_GMAC_RXD1M1 = 2,
88 GPIO1B3_SEL_SHIFT = 6,
89 GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT,
90 GPIO1B3_GMAC_RXD0M1 = 2,
92 GPIO1B4_SEL_SHIFT = 8,
93 GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT,
94 GPIO1B4_GMAC_TXCLKM1 = 2,
96 GPIO1B5_SEL_SHIFT = 10,
97 GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT,
98 GPIO1B5_GMAC_RXCLKM1 = 2,
100 GPIO1B6_SEL_SHIFT = 12,
101 GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT,
102 GPIO1B6_GMAC_RXD3M1 = 2,
104 GPIO1B7_SEL_SHIFT = 14,
105 GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT,
106 GPIO1B7_GMAC_RXD2M1 = 2,
109 GPIO1C0_SEL_SHIFT = 0,
110 GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT,
111 GPIO1C0_GMAC_TXD3M1 = 2,
113 GPIO1C1_SEL_SHIFT = 2,
114 GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT,
115 GPIO1C1_GMAC_TXD2M1 = 2,
117 GPIO1C3_SEL_SHIFT = 6,
118 GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT,
119 GPIO1C3_GMAC_MDIOM1 = 2,
121 GPIO1C5_SEL_SHIFT = 10,
122 GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT,
123 GPIO1C5_GMAC_CLKM1 = 2,
125 GPIO1C6_SEL_SHIFT = 12,
126 GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT,
127 GPIO1C6_GMAC_RXDVM1 = 2,
129 GPIO1C7_SEL_SHIFT = 14,
130 GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT,
131 GPIO1C7_GMAC_MDCM1 = 2,
134 GPIO1D1_SEL_SHIFT = 2,
135 GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT,
136 GPIO1D1_GMAC_TXENM1 = 2,
139 GPIO2A0_SEL_SHIFT = 0,
140 GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
141 GPIO2A0_UART2_TX_M1 = 1,
143 GPIO2A1_SEL_SHIFT = 2,
144 GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
145 GPIO2A1_UART2_RX_M1 = 1,
147 GPIO2A2_SEL_SHIFT = 4,
148 GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
151 GPIO2A4_SEL_SHIFT = 8,
152 GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
156 GPIO2A5_SEL_SHIFT = 10,
157 GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
161 GPIO2A6_SEL_SHIFT = 12,
162 GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
165 GPIO2A7_SEL_SHIFT = 14,
166 GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
168 GPIO2A7_SDMMC0_PWRENM0,
171 GPIO2BL0_SEL_SHIFT = 0,
172 GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
173 GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
175 GPIO2BL3_SEL_SHIFT = 6,
176 GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
177 GPIO2BL3_SPI_CSN0_M0 = 1,
179 GPIO2BL4_SEL_SHIFT = 8,
180 GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
181 GPIO2BL4_SPI_CSN1_M0 = 1,
183 GPIO2BL5_SEL_SHIFT = 10,
184 GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
185 GPIO2BL5_I2C2_SDA = 1,
187 GPIO2BL6_SEL_SHIFT = 12,
188 GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
189 GPIO2BL6_I2C2_SCL = 1,
192 GPIO2D0_SEL_SHIFT = 0,
193 GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
194 GPIO2D0_I2C0_SCL = 1,
196 GPIO2D1_SEL_SHIFT = 2,
197 GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
198 GPIO2D1_I2C0_SDA = 1,
200 GPIO2D4_SEL_SHIFT = 8,
201 GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
202 GPIO2D4_EMMC_DATA1234 = 0xaa,
205 GPIO3C0_SEL_SHIFT = 0,
206 GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
207 GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
210 IOMUX_SEL_UART2_SHIFT = 0,
211 IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
212 IOMUX_SEL_UART2_M0 = 0,
215 IOMUX_SEL_GMAC_SHIFT = 2,
216 IOMUX_SEL_GMAC_MASK = 1 << IOMUX_SEL_GMAC_SHIFT,
217 IOMUX_SEL_GMAC_M0 = 0,
220 IOMUX_SEL_SPI_SHIFT = 4,
221 IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
222 IOMUX_SEL_SPI_M0 = 0,
226 IOMUX_SEL_SDMMC_SHIFT = 7,
227 IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
228 IOMUX_SEL_SDMMC_M0 = 0,
231 IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10,
232 IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = 1 << IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT,
233 IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0,
234 IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER,
237 GRF_GPIO1B0_E_SHIFT = 0,
238 GRF_GPIO1B0_E_MASK = 3 << GRF_GPIO1B0_E_SHIFT,
239 GRF_GPIO1B1_E_SHIFT = 2,
240 GRF_GPIO1B1_E_MASK = 3 << GRF_GPIO1B1_E_SHIFT,
241 GRF_GPIO1B2_E_SHIFT = 4,
242 GRF_GPIO1B2_E_MASK = 3 << GRF_GPIO1B2_E_SHIFT,
243 GRF_GPIO1B3_E_SHIFT = 6,
244 GRF_GPIO1B3_E_MASK = 3 << GRF_GPIO1B3_E_SHIFT,
245 GRF_GPIO1B4_E_SHIFT = 8,
246 GRF_GPIO1B4_E_MASK = 3 << GRF_GPIO1B4_E_SHIFT,
247 GRF_GPIO1B5_E_SHIFT = 10,
248 GRF_GPIO1B5_E_MASK = 3 << GRF_GPIO1B5_E_SHIFT,
249 GRF_GPIO1B6_E_SHIFT = 12,
250 GRF_GPIO1B6_E_MASK = 3 << GRF_GPIO1B6_E_SHIFT,
251 GRF_GPIO1B7_E_SHIFT = 14,
252 GRF_GPIO1B7_E_MASK = 3 << GRF_GPIO1B7_E_SHIFT,
255 GRF_GPIO1C0_E_SHIFT = 0,
256 GRF_GPIO1C0_E_MASK = 3 << GRF_GPIO1C0_E_SHIFT,
257 GRF_GPIO1C1_E_SHIFT = 2,
258 GRF_GPIO1C1_E_MASK = 3 << GRF_GPIO1C1_E_SHIFT,
259 GRF_GPIO1C3_E_SHIFT = 6,
260 GRF_GPIO1C3_E_MASK = 3 << GRF_GPIO1C3_E_SHIFT,
261 GRF_GPIO1C5_E_SHIFT = 10,
262 GRF_GPIO1C5_E_MASK = 3 << GRF_GPIO1C5_E_SHIFT,
263 GRF_GPIO1C6_E_SHIFT = 12,
264 GRF_GPIO1C6_E_MASK = 3 << GRF_GPIO1C6_E_SHIFT,
265 GRF_GPIO1C7_E_SHIFT = 14,
266 GRF_GPIO1C7_E_MASK = 3 << GRF_GPIO1C7_E_SHIFT,
269 GRF_GPIO1D1_E_SHIFT = 2,
270 GRF_GPIO1D1_E_MASK = 3 << GRF_GPIO1D1_E_SHIFT,
273 /* GPIO Bias drive strength settings */
281 struct rk3328_pinctrl_priv {
282 struct rk3328_grf_regs *grf;
285 static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
289 rk_clrsetreg(&grf->gpio2a_iomux,
291 GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT);
294 rk_clrsetreg(&grf->gpio2a_iomux,
296 GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT);
299 rk_clrsetreg(&grf->gpio2a_iomux,
301 GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT);
304 rk_clrsetreg(&grf->gpio2a_iomux,
306 GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT);
309 debug("pwm id = %d iomux error!\n", pwm_id);
314 static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
318 rk_clrsetreg(&grf->gpio2d_iomux,
319 GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK,
320 GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT |
321 GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT);
324 rk_clrsetreg(&grf->gpio2a_iomux,
325 GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK,
326 GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT |
327 GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT);
330 rk_clrsetreg(&grf->gpio2bl_iomux,
331 GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK,
332 GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT |
333 GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT);
336 rk_clrsetreg(&grf->gpio0a_iomux,
337 GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK,
338 GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT |
339 GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT);
342 debug("i2c id = %d iomux error!\n", i2c_id);
347 static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
350 case PERIPH_ID_LCDC0:
353 debug("lcdc id = %d iomux error!\n", lcd_id);
358 static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
359 enum periph_id spi_id, int cs)
361 u32 com_iomux = readl(&grf->com_iomux);
363 if ((com_iomux & IOMUX_SEL_SPI_MASK) !=
364 IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) {
365 debug("driver do not support iomux other than m0\n");
373 rk_clrsetreg(&grf->gpio2bl_iomux,
376 << GPIO2BL3_SEL_SHIFT);
379 rk_clrsetreg(&grf->gpio2bl_iomux,
382 << GPIO2BL4_SEL_SHIFT);
387 rk_clrsetreg(&grf->gpio2bl_iomux,
389 GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT);
397 debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
401 static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
403 u32 com_iomux = readl(&grf->com_iomux);
406 case PERIPH_ID_UART2:
408 if (com_iomux & IOMUX_SEL_UART2_MASK)
409 rk_clrsetreg(&grf->gpio2a_iomux,
410 GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
411 GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
412 GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
415 case PERIPH_ID_UART0:
416 case PERIPH_ID_UART1:
417 case PERIPH_ID_UART3:
418 case PERIPH_ID_UART4:
420 debug("uart id = %d iomux error!\n", uart_id);
425 static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
428 u32 com_iomux = readl(&grf->com_iomux);
432 rk_clrsetreg(&grf->gpio0a_iomux,
434 GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT);
435 rk_clrsetreg(&grf->gpio2d_iomux,
437 GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT);
438 rk_clrsetreg(&grf->gpio3c_iomux,
440 GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD
441 << GPIO3C0_SEL_SHIFT);
443 case PERIPH_ID_SDCARD:
444 /* SDMMC_PWREN use GPIO and init as regulator-fiexed */
445 if (com_iomux & IOMUX_SEL_SDMMC_MASK)
446 rk_clrsetreg(&grf->gpio0d_iomux,
448 GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
450 rk_clrsetreg(&grf->gpio2a_iomux,
452 GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
453 rk_clrsetreg(&grf->gpio1a_iomux,
455 GPIO1A0_CARD_DATA_CLK_CMD_DETN
456 << GPIO1A0_SEL_SHIFT);
459 debug("mmc id = %d iomux error!\n", mmc_id);
464 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
465 static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id)
469 /* set rgmii m1 pins mux */
470 rk_clrsetreg(&grf->gpio1b_iomux,
479 GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT |
480 GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT |
481 GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT |
482 GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT |
483 GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT |
484 GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT |
485 GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT |
486 GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT);
488 rk_clrsetreg(&grf->gpio1c_iomux,
495 GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT |
496 GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT |
497 GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT |
498 GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT |
499 GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT |
500 GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT);
502 rk_clrsetreg(&grf->gpio1d_iomux,
504 GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT);
506 /* set rgmii m0 tx pins mux */
507 rk_clrsetreg(&grf->gpio0b_iomux,
510 GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT |
511 GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT);
513 rk_clrsetreg(&grf->gpio0c_iomux,
518 GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT |
519 GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT |
520 GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT |
521 GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT);
523 rk_clrsetreg(&grf->gpio0d_iomux,
525 GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT);
528 rk_clrsetreg(&grf->com_iomux,
529 IOMUX_SEL_GMAC_MASK |
530 IOMUX_SEL_GMACM1_OPTIMIZATION_MASK,
531 IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT |
532 IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER <<
533 IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT);
536 * set rgmii m1 tx pins to 12ma drive-strength,
537 * and clean others to 2ma.
539 rk_clrsetreg(&grf->gpio1b_e,
548 GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT |
549 GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT |
550 GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT |
551 GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT |
552 GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT |
553 GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT |
554 GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT |
555 GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT);
557 rk_clrsetreg(&grf->gpio1c_e,
564 GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT |
565 GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT |
566 GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT |
567 GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT |
568 GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT |
569 GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT);
571 rk_clrsetreg(&grf->gpio1d_e,
573 GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT);
576 debug("gmac id = %d iomux error!\n", gmac_id);
582 static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
584 struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
586 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
592 pinctrl_rk3328_pwm_config(priv->grf, func);
598 pinctrl_rk3328_i2c_config(priv->grf, func);
601 pinctrl_rk3328_spi_config(priv->grf, func, flags);
603 case PERIPH_ID_UART0:
604 case PERIPH_ID_UART1:
605 case PERIPH_ID_UART2:
606 case PERIPH_ID_UART3:
607 case PERIPH_ID_UART4:
608 pinctrl_rk3328_uart_config(priv->grf, func);
610 case PERIPH_ID_LCDC0:
611 case PERIPH_ID_LCDC1:
612 pinctrl_rk3328_lcdc_config(priv->grf, func);
614 case PERIPH_ID_SDMMC0:
615 case PERIPH_ID_SDMMC1:
616 pinctrl_rk3328_sdmmc_config(priv->grf, func);
618 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
620 pinctrl_rk3328_gmac_config(priv->grf, func);
630 static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
631 struct udevice *periph)
636 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
642 return PERIPH_ID_SPI0;
644 return PERIPH_ID_PWM0;
646 return PERIPH_ID_I2C0;
647 case 37: /* Note strange order */
648 return PERIPH_ID_I2C1;
650 return PERIPH_ID_I2C2;
652 return PERIPH_ID_I2C3;
654 return PERIPH_ID_SDCARD;
656 return PERIPH_ID_EMMC;
657 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
659 return PERIPH_ID_GMAC;
666 static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
667 struct udevice *periph)
671 func = rk3328_pinctrl_get_periph_id(dev, periph);
675 return rk3328_pinctrl_request(dev, func, 0);
678 static struct pinctrl_ops rk3328_pinctrl_ops = {
679 .set_state_simple = rk3328_pinctrl_set_state_simple,
680 .request = rk3328_pinctrl_request,
681 .get_periph_id = rk3328_pinctrl_get_periph_id,
684 static int rk3328_pinctrl_probe(struct udevice *dev)
686 struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
689 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
690 debug("%s: grf=%p\n", __func__, priv->grf);
695 static const struct udevice_id rk3328_pinctrl_ids[] = {
696 { .compatible = "rockchip,rk3328-pinctrl" },
700 U_BOOT_DRIVER(pinctrl_rk3328) = {
701 .name = "rockchip_rk3328_pinctrl",
702 .id = UCLASS_PINCTRL,
703 .of_match = rk3328_pinctrl_ids,
704 .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
705 .ops = &rk3328_pinctrl_ops,
706 .bind = dm_scan_fdt_dev,
707 .probe = rk3328_pinctrl_probe,