2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/grf_rk3328.h>
14 #include <asm/arch/periph.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR;
22 GPIO0A5_SEL_SHIFT = 10,
23 GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
26 GPIO0A6_SEL_SHIFT = 12,
27 GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
30 GPIO0A7_SEL_SHIFT = 14,
31 GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
32 GPIO0A7_EMMC_DATA0 = 2,
34 GPIO0D6_SEL_SHIFT = 12,
35 GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
37 GPIO0D6_SDMMC0_PWRENM1 = 3,
40 GPIO1A0_SEL_SHIFT = 0,
41 GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
42 GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
45 GPIO2A0_SEL_SHIFT = 0,
46 GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
47 GPIO2A0_UART2_TX_M1 = 1,
49 GPIO2A1_SEL_SHIFT = 2,
50 GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
51 GPIO2A1_UART2_RX_M1 = 1,
53 GPIO2A2_SEL_SHIFT = 4,
54 GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
57 GPIO2A4_SEL_SHIFT = 8,
58 GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
62 GPIO2A5_SEL_SHIFT = 10,
63 GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
67 GPIO2A6_SEL_SHIFT = 12,
68 GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
71 GPIO2A7_SEL_SHIFT = 14,
72 GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
74 GPIO2A7_SDMMC0_PWRENM0,
77 GPIO2BL0_SEL_SHIFT = 0,
78 GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
79 GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
81 GPIO2BL3_SEL_SHIFT = 6,
82 GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
83 GPIO2BL3_SPI_CSN0_M0 = 1,
85 GPIO2BL4_SEL_SHIFT = 8,
86 GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
87 GPIO2BL4_SPI_CSN1_M0 = 1,
89 GPIO2BL5_SEL_SHIFT = 10,
90 GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
91 GPIO2BL5_I2C2_SDA = 1,
93 GPIO2BL6_SEL_SHIFT = 12,
94 GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
95 GPIO2BL6_I2C2_SCL = 1,
98 GPIO2D0_SEL_SHIFT = 0,
99 GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
100 GPIO2D0_I2C0_SCL = 1,
102 GPIO2D1_SEL_SHIFT = 2,
103 GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
104 GPIO2D1_I2C0_SDA = 1,
106 GPIO2D4_SEL_SHIFT = 8,
107 GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
108 GPIO2D4_EMMC_DATA1234 = 0xaa,
111 GPIO3C0_SEL_SHIFT = 0,
112 GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
113 GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
116 IOMUX_SEL_UART2_SHIFT = 0,
117 IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
118 IOMUX_SEL_UART2_M0 = 0,
121 IOMUX_SEL_SPI_SHIFT = 4,
122 IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
123 IOMUX_SEL_SPI_M0 = 0,
127 IOMUX_SEL_SDMMC_SHIFT = 7,
128 IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
129 IOMUX_SEL_SDMMC_M0 = 0,
133 struct rk3328_pinctrl_priv {
134 struct rk3328_grf_regs *grf;
137 static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
141 rk_clrsetreg(&grf->gpio2a_iomux,
143 GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT);
146 rk_clrsetreg(&grf->gpio2a_iomux,
148 GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT);
151 rk_clrsetreg(&grf->gpio2a_iomux,
153 GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT);
156 rk_clrsetreg(&grf->gpio2a_iomux,
158 GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT);
161 debug("pwm id = %d iomux error!\n", pwm_id);
166 static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
170 rk_clrsetreg(&grf->gpio2d_iomux,
171 GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK,
172 GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT |
173 GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT);
176 rk_clrsetreg(&grf->gpio2a_iomux,
177 GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK,
178 GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT |
179 GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT);
182 rk_clrsetreg(&grf->gpio2bl_iomux,
183 GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK,
184 GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT |
185 GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT);
188 rk_clrsetreg(&grf->gpio0a_iomux,
189 GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK,
190 GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT |
191 GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT);
194 debug("i2c id = %d iomux error!\n", i2c_id);
199 static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
202 case PERIPH_ID_LCDC0:
205 debug("lcdc id = %d iomux error!\n", lcd_id);
210 static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
211 enum periph_id spi_id, int cs)
213 u32 com_iomux = readl(&grf->com_iomux);
215 if ((com_iomux & IOMUX_SEL_SPI_MASK) !=
216 IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) {
217 debug("driver do not support iomux other than m0\n");
225 rk_clrsetreg(&grf->gpio2bl_iomux,
228 << GPIO2BL3_SEL_SHIFT);
231 rk_clrsetreg(&grf->gpio2bl_iomux,
234 << GPIO2BL4_SEL_SHIFT);
239 rk_clrsetreg(&grf->gpio2bl_iomux,
241 GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT);
249 debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
253 static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
255 u32 com_iomux = readl(&grf->com_iomux);
258 case PERIPH_ID_UART2:
260 if (com_iomux & IOMUX_SEL_UART2_MASK)
261 rk_clrsetreg(&grf->gpio2a_iomux,
262 GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
263 GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
264 GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
267 case PERIPH_ID_UART0:
268 case PERIPH_ID_UART1:
269 case PERIPH_ID_UART3:
270 case PERIPH_ID_UART4:
272 debug("uart id = %d iomux error!\n", uart_id);
277 static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
280 u32 com_iomux = readl(&grf->com_iomux);
284 rk_clrsetreg(&grf->gpio0a_iomux,
286 GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT);
287 rk_clrsetreg(&grf->gpio2d_iomux,
289 GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT);
290 rk_clrsetreg(&grf->gpio3c_iomux,
292 GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD
293 << GPIO3C0_SEL_SHIFT);
295 case PERIPH_ID_SDCARD:
296 /* SDMMC_PWREN use GPIO and init as regulator-fiexed */
297 if (com_iomux & IOMUX_SEL_SDMMC_MASK)
298 rk_clrsetreg(&grf->gpio0d_iomux,
300 GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
302 rk_clrsetreg(&grf->gpio2a_iomux,
304 GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
305 rk_clrsetreg(&grf->gpio1a_iomux,
307 GPIO1A0_CARD_DATA_CLK_CMD_DETN
308 << GPIO1A0_SEL_SHIFT);
311 debug("mmc id = %d iomux error!\n", mmc_id);
316 static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
318 struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
320 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
326 pinctrl_rk3328_pwm_config(priv->grf, func);
332 pinctrl_rk3328_i2c_config(priv->grf, func);
335 pinctrl_rk3328_spi_config(priv->grf, func, flags);
337 case PERIPH_ID_UART0:
338 case PERIPH_ID_UART1:
339 case PERIPH_ID_UART2:
340 case PERIPH_ID_UART3:
341 case PERIPH_ID_UART4:
342 pinctrl_rk3328_uart_config(priv->grf, func);
344 case PERIPH_ID_LCDC0:
345 case PERIPH_ID_LCDC1:
346 pinctrl_rk3328_lcdc_config(priv->grf, func);
348 case PERIPH_ID_SDMMC0:
349 case PERIPH_ID_SDMMC1:
350 pinctrl_rk3328_sdmmc_config(priv->grf, func);
359 static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
360 struct udevice *periph)
365 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
371 return PERIPH_ID_SPI0;
373 return PERIPH_ID_PWM0;
375 return PERIPH_ID_I2C0;
376 case 37: /* Note strange order */
377 return PERIPH_ID_I2C1;
379 return PERIPH_ID_I2C2;
381 return PERIPH_ID_I2C3;
383 return PERIPH_ID_SDCARD;
385 return PERIPH_ID_EMMC;
391 static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
392 struct udevice *periph)
396 func = rk3328_pinctrl_get_periph_id(dev, periph);
400 return rk3328_pinctrl_request(dev, func, 0);
403 static struct pinctrl_ops rk3328_pinctrl_ops = {
404 .set_state_simple = rk3328_pinctrl_set_state_simple,
405 .request = rk3328_pinctrl_request,
406 .get_periph_id = rk3328_pinctrl_get_periph_id,
409 static int rk3328_pinctrl_probe(struct udevice *dev)
411 struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
414 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
415 debug("%s: grf=%p\n", __func__, priv->grf);
420 static const struct udevice_id rk3328_pinctrl_ids[] = {
421 { .compatible = "rockchip,rk3328-pinctrl" },
425 U_BOOT_DRIVER(pinctrl_rk3328) = {
426 .name = "rockchip_rk3328_pinctrl",
427 .id = UCLASS_PINCTRL,
428 .of_match = rk3328_pinctrl_ids,
429 .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
430 .ops = &rk3328_pinctrl_ops,
431 .bind = dm_scan_fdt_dev,
432 .probe = rk3328_pinctrl_probe,