drivers/pinctrl/rockchip/pinctrl_rk3288.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  * Copyright (c) 2015 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/periph.h>
  18 #include <asm/arch/pmu_rk3288.h>
  19 #include <dm/pinctrl.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct rk3288_pinctrl_priv {
  24         struct rk3288_grf *grf;
  25         struct rk3288_pmu *pmu;
  26         int num_banks;
  27 };
  28
  29 /**
  30  * Encode variants of iomux registers into a type variable
  31  */
  32 #define IOMUX_GPIO_ONLY         BIT(0)
  33 #define IOMUX_WIDTH_4BIT        BIT(1)
  34 #define IOMUX_SOURCE_PMU        BIT(2)
  35 #define IOMUX_UNROUTED          BIT(3)
  36
  37 /**
  38  * @type: iomux variant using IOMUX_* constants
  39  * @offset: if initialized to -1 it will be autocalculated, by specifying
  40  *          an initial offset value the relevant source offset can be reset
  41  *          to a new value for autocalculating the following iomux registers.
  42  */
  43 struct rockchip_iomux {
  44         u8 type;
  45         s16 offset;
  46 };
  47
  48 /**
  49  * @reg: register offset of the gpio bank
  50  * @nr_pins: number of pins in this bank
  51  * @bank_num: number of the bank, to account for holes
  52  * @name: name of the bank
  53  * @iomux: array describing the 4 iomux sources of the bank
  54  */
  55 struct rockchip_pin_bank {
  56         u16 reg;
  57         u8 nr_pins;
  58         u8 bank_num;
  59         char *name;
  60         struct rockchip_iomux iomux[4];
  61 };
  62
  63 #define PIN_BANK(id, pins, label)                       \
  64         {                                               \
  65                 .bank_num       = id,                   \
  66                 .nr_pins        = pins,                 \
  67                 .name           = label,                \
  68                 .iomux          = {                     \
  69                         { .offset = -1 },               \
  70                         { .offset = -1 },               \
  71                         { .offset = -1 },               \
  72                         { .offset = -1 },               \
  73                 },                                      \
  74         }
  75
  76 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  77         {                                                               \
  78                 .bank_num       = id,                                   \
  79                 .nr_pins        = pins,                                 \
  80                 .name           = label,                                \
  81                 .iomux          = {                                     \
  82                         { .type = iom0, .offset = -1 },                 \
  83                         { .type = iom1, .offset = -1 },                 \
  84                         { .type = iom2, .offset = -1 },                 \
  85                         { .type = iom3, .offset = -1 },                 \
  86                 },                                                      \
  87         }
  88
  89 #ifndef CONFIG_SPL_BUILD
  90 static struct rockchip_pin_bank rk3288_pin_banks[] = {
  91         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
  92                                              IOMUX_SOURCE_PMU,
  93                                              IOMUX_SOURCE_PMU,
  94                                              IOMUX_UNROUTED
  95                             ),
  96         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
  97                                              IOMUX_UNROUTED,
  98                                              IOMUX_UNROUTED,
  99                                              0
 100                             ),
 101         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
 102         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
 103         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
 104                                              IOMUX_WIDTH_4BIT,
 105                                              0,
 106                                              0
 107                             ),
 108         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
 109                                              0,
 110                                              0,
 111                                              IOMUX_UNROUTED
 112                             ),
 113         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
 114         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
 115                                              0,
 116                                              IOMUX_WIDTH_4BIT,
 117                                              IOMUX_UNROUTED
 118                             ),
 119         PIN_BANK(8, 16, "gpio8"),
 120 };
 121 #endif
 122
 123 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
 124 {
 125         switch (pwm_id) {
 126         case PERIPH_ID_PWM0:
 127                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
 128                              GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
 129                 break;
 130         case PERIPH_ID_PWM1:
 131                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
 132                              GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
 133                 break;
 134         case PERIPH_ID_PWM2:
 135                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
 136                              GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
 137                 break;
 138         case PERIPH_ID_PWM3:
 139                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
 140                              GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
 141                 break;
 142         default:
 143                 debug("pwm id = %d iomux error!\n", pwm_id);
 144                 break;
 145         }
 146 }
 147
 148 static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
 149                                       struct rk3288_pmu *pmu, int i2c_id)
 150 {
 151         switch (i2c_id) {
 152         case PERIPH_ID_I2C0:
 153                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
 154                                 GPIO0_B7_MASK << GPIO0_B7_SHIFT,
 155                                 GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
 156                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
 157                                 GPIO0_C0_MASK << GPIO0_C0_SHIFT,
 158                                 GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
 159                 break;
 160 #ifndef CONFIG_SPL_BUILD
 161         case PERIPH_ID_I2C1:
 162                 rk_clrsetreg(&grf->gpio8a_iomux,
 163                              GPIO8A4_MASK << GPIO8A4_SHIFT |
 164                              GPIO8A5_MASK << GPIO8A5_SHIFT,
 165                              GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
 166                              GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
 167                 break;
 168         case PERIPH_ID_I2C2:
 169                 rk_clrsetreg(&grf->gpio6b_iomux,
 170                              GPIO6B1_MASK << GPIO6B1_SHIFT |
 171                              GPIO6B2_MASK << GPIO6B2_SHIFT,
 172                              GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
 173                              GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
 174                 break;
 175         case PERIPH_ID_I2C3:
 176                 rk_clrsetreg(&grf->gpio2c_iomux,
 177                              GPIO2C1_MASK << GPIO2C1_SHIFT |
 178                              GPIO2C0_MASK << GPIO2C0_SHIFT,
 179                              GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
 180                              GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
 181                 break;
 182         case PERIPH_ID_I2C4:
 183                 rk_clrsetreg(&grf->gpio7cl_iomux,
 184                              GPIO7C1_MASK << GPIO7C1_SHIFT |
 185                              GPIO7C2_MASK << GPIO7C2_SHIFT,
 186                              GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
 187                              GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
 188                 break;
 189         case PERIPH_ID_I2C5:
 190                 rk_clrsetreg(&grf->gpio7cl_iomux,
 191                              GPIO7C3_MASK << GPIO7C3_SHIFT,
 192                              GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
 193                 rk_clrsetreg(&grf->gpio7ch_iomux,
 194                              GPIO7C4_MASK << GPIO7C4_SHIFT,
 195                              GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
 196                 break;
 197 #endif
 198         default:
 199                 debug("i2c id = %d iomux error!\n", i2c_id);
 200                 break;
 201         }
 202 }
 203
 204 #ifndef CONFIG_SPL_BUILD
 205 static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
 206 {
 207         switch (lcd_id) {
 208         case PERIPH_ID_LCDC0:
 209                 rk_clrsetreg(&grf->gpio1d_iomux,
 210                              GPIO1D3_MASK << GPIO1D0_SHIFT |
 211                              GPIO1D2_MASK << GPIO1D2_SHIFT |
 212                              GPIO1D1_MASK << GPIO1D1_SHIFT |
 213                              GPIO1D0_MASK << GPIO1D0_SHIFT,
 214                              GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
 215                              GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
 216                              GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
 217                              GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
 218                 break;
 219         default:
 220                 debug("lcdc id = %d iomux error!\n", lcd_id);
 221                 break;
 222         }
 223 }
 224 #endif
 225
 226 static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
 227                                      enum periph_id spi_id, int cs)
 228 {
 229         switch (spi_id) {
 230 #ifndef CONFIG_SPL_BUILD
 231         case PERIPH_ID_SPI0:
 232                 switch (cs) {
 233                 case 0:
 234                         rk_clrsetreg(&grf->gpio5b_iomux,
 235                                      GPIO5B5_MASK << GPIO5B5_SHIFT,
 236                                      GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
 237                         break;
 238                 case 1:
 239                         rk_clrsetreg(&grf->gpio5c_iomux,
 240                                      GPIO5C0_MASK << GPIO5C0_SHIFT,
 241                                      GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
 242                         break;
 243                 default:
 244                         goto err;
 245                 }
 246                 rk_clrsetreg(&grf->gpio5b_iomux,
 247                              GPIO5B7_MASK << GPIO5B7_SHIFT |
 248                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 249                              GPIO5B4_MASK << GPIO5B4_SHIFT,
 250                              GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
 251                              GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
 252                              GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
 253                 break;
 254         case PERIPH_ID_SPI1:
 255                 if (cs != 0)
 256                         goto err;
 257                 rk_clrsetreg(&grf->gpio7b_iomux,
 258                              GPIO7B6_MASK << GPIO7B6_SHIFT |
 259                              GPIO7B7_MASK << GPIO7B7_SHIFT |
 260                              GPIO7B5_MASK << GPIO7B5_SHIFT |
 261                              GPIO7B4_MASK << GPIO7B4_SHIFT,
 262                              GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
 263                              GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
 264                              GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
 265                              GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
 266                 break;
 267 #endif
 268         case PERIPH_ID_SPI2:
 269                 switch (cs) {
 270                 case 0:
 271                         rk_clrsetreg(&grf->gpio8a_iomux,
 272                                      GPIO8A7_MASK << GPIO8A7_SHIFT,
 273                                      GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
 274                         break;
 275                 case 1:
 276                         rk_clrsetreg(&grf->gpio8a_iomux,
 277                                      GPIO8A3_MASK << GPIO8A3_SHIFT,
 278                                      GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
 279                         break;
 280                 default:
 281                         goto err;
 282                 }
 283                 rk_clrsetreg(&grf->gpio8b_iomux,
 284                              GPIO8B1_MASK << GPIO8B1_SHIFT |
 285                              GPIO8B0_MASK << GPIO8B0_SHIFT,
 286                              GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
 287                              GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
 288                 rk_clrsetreg(&grf->gpio8a_iomux,
 289                              GPIO8A6_MASK << GPIO8A6_SHIFT,
 290                              GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
 291                 break;
 292         default:
 293                 goto err;
 294         }
 295
 296         return 0;
 297 err:
 298         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 299         return -ENOENT;
 300 }
 301
 302 static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
 303 {
 304         switch (uart_id) {
 305 #ifndef CONFIG_SPL_BUILD
 306         case PERIPH_ID_UART_BT:
 307                 rk_clrsetreg(&grf->gpio4c_iomux,
 308                              GPIO4C3_MASK << GPIO4C3_SHIFT |
 309                              GPIO4C2_MASK << GPIO4C2_SHIFT |
 310                              GPIO4C1_MASK << GPIO4C1_SHIFT |
 311                              GPIO4C0_MASK << GPIO4C0_SHIFT,
 312                              GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
 313                              GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
 314                              GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
 315                              GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
 316                 break;
 317         case PERIPH_ID_UART_BB:
 318                 rk_clrsetreg(&grf->gpio5b_iomux,
 319                              GPIO5B3_MASK << GPIO5B3_SHIFT |
 320                              GPIO5B2_MASK << GPIO5B2_SHIFT |
 321                              GPIO5B1_MASK << GPIO5B1_SHIFT |
 322                              GPIO5B0_MASK << GPIO5B0_SHIFT,
 323                              GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
 324                              GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
 325                              GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
 326                              GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
 327                 break;
 328 #endif
 329         case PERIPH_ID_UART_DBG:
 330                 rk_clrsetreg(&grf->gpio7ch_iomux,
 331                              GPIO7C7_MASK << GPIO7C7_SHIFT |
 332                              GPIO7C6_MASK << GPIO7C6_SHIFT,
 333                              GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 334                              GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 335                 break;
 336 #ifndef CONFIG_SPL_BUILD
 337         case PERIPH_ID_UART_GPS:
 338                 rk_clrsetreg(&grf->gpio7b_iomux,
 339                              GPIO7B2_MASK << GPIO7B2_SHIFT |
 340                              GPIO7B1_MASK << GPIO7B1_SHIFT |
 341                              GPIO7B0_MASK << GPIO7B0_SHIFT,
 342                              GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
 343                              GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
 344                              GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
 345                 rk_clrsetreg(&grf->gpio7a_iomux,
 346                              GPIO7A7_MASK << GPIO7A7_SHIFT,
 347                              GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
 348                 break;
 349         case PERIPH_ID_UART_EXP:
 350                 rk_clrsetreg(&grf->gpio5b_iomux,
 351                              GPIO5B5_MASK << GPIO5B5_SHIFT |
 352                              GPIO5B4_MASK << GPIO5B4_SHIFT |
 353                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 354                              GPIO5B7_MASK << GPIO5B7_SHIFT,
 355                              GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
 356                              GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
 357                              GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
 358                              GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
 359                 break;
 360 #endif
 361         default:
 362                 debug("uart id = %d iomux error!\n", uart_id);
 363                 break;
 364         }
 365 }
 366
 367 static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
 368 {
 369         switch (mmc_id) {
 370         case PERIPH_ID_EMMC:
 371                 rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
 372                              GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
 373                              GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
 374                              GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
 375                              GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
 376                              GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
 377                              GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
 378                              GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
 379                              GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
 380                 rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
 381                              GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
 382                 rk_clrsetreg(&grf->gpio3c_iomux,
 383                              GPIO3C0_MASK << GPIO3C0_SHIFT,
 384                              GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
 385                 break;
 386         case PERIPH_ID_SDCARD:
 387                 rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
 388                              GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
 389                              GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
 390                              GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
 391                              GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
 392                              GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
 393                              GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
 394                              GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
 395
 396                 /* use sdmmc0 io, disable JTAG function */
 397                 rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
 398                 break;
 399         default:
 400                 debug("mmc id = %d iomux error!\n", mmc_id);
 401                 break;
 402         }
 403 }
 404
 405 #ifndef CONFIG_SPL_BUILD
 406 static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
 407 {
 408         switch (hdmi_id) {
 409         case PERIPH_ID_HDMI:
 410                 rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
 411                              GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
 412                 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
 413                              GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
 414                 break;
 415         default:
 416                 debug("hdmi id = %d iomux error!\n", hdmi_id);
 417                 break;
 418         }
 419 }
 420 #endif
 421
 422 static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
 423 {
 424         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 425
 426         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 427         switch (func) {
 428         case PERIPH_ID_PWM0:
 429         case PERIPH_ID_PWM1:
 430         case PERIPH_ID_PWM2:
 431         case PERIPH_ID_PWM3:
 432         case PERIPH_ID_PWM4:
 433                 pinctrl_rk3288_pwm_config(priv->grf, func);
 434                 break;
 435         case PERIPH_ID_I2C0:
 436         case PERIPH_ID_I2C1:
 437         case PERIPH_ID_I2C2:
 438         case PERIPH_ID_I2C3:
 439         case PERIPH_ID_I2C4:
 440         case PERIPH_ID_I2C5:
 441                 pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
 442                 break;
 443         case PERIPH_ID_SPI0:
 444         case PERIPH_ID_SPI1:
 445         case PERIPH_ID_SPI2:
 446                 pinctrl_rk3288_spi_config(priv->grf, func, flags);
 447                 break;
 448         case PERIPH_ID_UART0:
 449         case PERIPH_ID_UART1:
 450         case PERIPH_ID_UART2:
 451         case PERIPH_ID_UART3:
 452         case PERIPH_ID_UART4:
 453                 pinctrl_rk3288_uart_config(priv->grf, func);
 454                 break;
 455 #ifndef CONFIG_SPL_BUILD
 456         case PERIPH_ID_LCDC0:
 457         case PERIPH_ID_LCDC1:
 458                 pinctrl_rk3288_lcdc_config(priv->grf, func);
 459                 break;
 460         case PERIPH_ID_HDMI:
 461                 pinctrl_rk3288_hdmi_config(priv->grf, func);
 462                 break;
 463 #endif
 464         case PERIPH_ID_SDMMC0:
 465         case PERIPH_ID_SDMMC1:
 466                 pinctrl_rk3288_sdmmc_config(priv->grf, func);
 467                 break;
 468         default:
 469                 return -EINVAL;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 476                                         struct udevice *periph)
 477 {
 478 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 479         u32 cell[3];
 480         int ret;
 481
 482         ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
 483                                    "interrupts", cell, ARRAY_SIZE(cell));
 484         if (ret < 0)
 485                 return -EINVAL;
 486
 487         switch (cell[1]) {
 488         case 44:
 489                 return PERIPH_ID_SPI0;
 490         case 45:
 491                 return PERIPH_ID_SPI1;
 492         case 46:
 493                 return PERIPH_ID_SPI2;
 494         case 60:
 495                 return PERIPH_ID_I2C0;
 496         case 62: /* Note strange order */
 497                 return PERIPH_ID_I2C1;
 498         case 61:
 499                 return PERIPH_ID_I2C2;
 500         case 63:
 501                 return PERIPH_ID_I2C3;
 502         case 64:
 503                 return PERIPH_ID_I2C4;
 504         case 65:
 505                 return PERIPH_ID_I2C5;
 506         case 103:
 507                 return PERIPH_ID_HDMI;
 508         }
 509 #endif
 510
 511         return -ENOENT;
 512 }
 513
 514 static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
 515                                            struct udevice *periph)
 516 {
 517         int func;
 518
 519         func = rk3288_pinctrl_get_periph_id(dev, periph);
 520         if (func < 0)
 521                 return func;
 522         return rk3288_pinctrl_request(dev, func, 0);
 523 }
 524
 525 #ifndef CONFIG_SPL_BUILD
 526 int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv,
 527                                 int banknum, int ind, u32 **addrp, uint *shiftp,
 528                                 uint *maskp)
 529 {
 530         struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
 531         uint muxnum;
 532         u32 *addr;
 533
 534         for (muxnum = 0; muxnum < 4; muxnum++) {
 535                 struct rockchip_iomux *mux = &bank->iomux[muxnum];
 536
 537                 if (ind >= 8) {
 538                         ind -= 8;
 539                         continue;
 540                 }
 541
 542                 if (mux->type & IOMUX_SOURCE_PMU)
 543                         addr = priv->pmu->gpio0_iomux;
 544                 else
 545                         addr = (u32 *)priv->grf - 4;
 546                 addr += mux->offset;
 547                 *shiftp = ind & 7;
 548                 if (mux->type & IOMUX_WIDTH_4BIT) {
 549                         *maskp = 0xf;
 550                         *shiftp *= 4;
 551                         if (*shiftp >= 16) {
 552                                 *shiftp -= 16;
 553                                 addr++;
 554                         }
 555                 } else {
 556                         *maskp = 3;
 557                         *shiftp *= 2;
 558                 }
 559
 560                 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
 561                       *maskp, *shiftp);
 562                 *addrp = addr;
 563                 return 0;
 564         }
 565
 566         return -EINVAL;
 567 }
 568
 569 static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 570                                        int index)
 571 {
 572         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 573         uint shift;
 574         uint mask;
 575         u32 *addr;
 576         int ret;
 577
 578         ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 579                                           &mask);
 580         if (ret)
 581                 return ret;
 582         return (readl(addr) & mask) >> shift;
 583 }
 584
 585 static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 586                                    int muxval, int flags)
 587 {
 588         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 589         uint shift, ind = index;
 590         uint mask;
 591         uint value;
 592         u32 *addr;
 593         int ret;
 594
 595         debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
 596         ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 597                                           &mask);
 598         if (ret)
 599                 return ret;
 600
 601         /*
 602          * PMU_GPIO0 registers cannot be selectively written so we cannot use
 603          * rk_clrsetreg() here.  However, the upper 16 bits are reserved and
 604          * are ignored when written, so we can use the same code as for the
 605          * other GPIO banks providing that we preserve the value of the other
 606          * bits.
 607          */
 608         value = readl(addr);
 609         value &= ~(mask << shift);
 610         value |= (mask << (shift + 16)) | (muxval << shift);
 611         writel(value, addr);
 612
 613         /* Handle pullup/pulldown */
 614         if (flags) {
 615                 uint val = 0;
 616
 617                 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
 618                         val = 1;
 619                 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 620                         val = 2;
 621                 shift = (index & 7) * 2;
 622                 ind = index >> 3;
 623                 if (banknum == 0)
 624                         addr = &priv->pmu->gpio0pull[ind];
 625                 else
 626                         addr = &priv->grf->gpio1_p[banknum - 1][ind];
 627                 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 628                       shift);
 629
 630                 /* As above, rk_clrsetreg() cannot be used here. */
 631                 value = readl(addr);
 632                 value &= ~(mask << shift);
 633                 value |= (3 << (shift + 16)) | (val << shift);
 634                 writel(value, addr);
 635         }
 636
 637         return 0;
 638 }
 639
 640 static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 641 {
 642         const void *blob = gd->fdt_blob;
 643         int pcfg_node, ret, flags, count, i;
 644         u32 cell[60], *ptr;
 645
 646         debug("%s: %s %s\n", __func__, dev->name, config->name);
 647         ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
 648                                          "rockchip,pins", cell,
 649                                          ARRAY_SIZE(cell));
 650         if (ret < 0) {
 651                 debug("%s: bad array %d\n", __func__, ret);
 652                 return -EINVAL;
 653         }
 654         count = ret;
 655         for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
 656                 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
 657                 if (pcfg_node < 0)
 658                         return -EINVAL;
 659                 flags = pinctrl_decode_pin_config(blob, pcfg_node);
 660                 if (flags < 0)
 661                         return flags;
 662
 663                 ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
 664                                               flags);
 665                 if (ret)
 666                         return ret;
 667         }
 668
 669         return 0;
 670 }
 671 #endif
 672
 673 static struct pinctrl_ops rk3288_pinctrl_ops = {
 674 #ifndef CONFIG_SPL_BUILD
 675         .set_state      = rk3288_pinctrl_set_state,
 676         .get_gpio_mux   = rk3288_pinctrl_get_gpio_mux,
 677 #endif
 678         .set_state_simple       = rk3288_pinctrl_set_state_simple,
 679         .request        = rk3288_pinctrl_request,
 680         .get_periph_id  = rk3288_pinctrl_get_periph_id,
 681 };
 682
 683 #ifndef CONFIG_SPL_BUILD
 684 static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
 685                                        struct rockchip_pin_bank *banks,
 686                                        int count)
 687 {
 688         struct rockchip_pin_bank *bank;
 689         uint reg, muxnum, banknum;
 690
 691         reg = 0;
 692         for (banknum = 0; banknum < count; banknum++) {
 693                 bank = &banks[banknum];
 694                 bank->reg = reg;
 695                 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
 696                 for (muxnum = 0; muxnum < 4; muxnum++) {
 697                         struct rockchip_iomux *mux = &bank->iomux[muxnum];
 698
 699                         if (!(mux->type & IOMUX_UNROUTED))
 700                                 mux->offset = reg;
 701                         if (mux->type & IOMUX_WIDTH_4BIT)
 702                                 reg += 2;
 703                         else
 704                                 reg += 1;
 705                 }
 706         }
 707
 708         return 0;
 709 }
 710 #endif
 711
 712 static int rk3288_pinctrl_probe(struct udevice *dev)
 713 {
 714         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 715         int ret = 0;
 716
 717         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 718         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 719         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 720 #ifndef CONFIG_SPL_BUILD
 721         ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
 722                                           ARRAY_SIZE(rk3288_pin_banks));
 723 #endif
 724
 725         return ret;
 726 }
 727
 728 static const struct udevice_id rk3288_pinctrl_ids[] = {
 729         { .compatible = "rockchip,rk3288-pinctrl" },
 730         { }
 731 };
 732
 733 U_BOOT_DRIVER(pinctrl_rk3288) = {
 734         .name           = "rockchip_rk3288_pinctrl",
 735         .id             = UCLASS_PINCTRL,
 736         .of_match       = rk3288_pinctrl_ids,
 737         .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
 738         .ops            = &rk3288_pinctrl_ops,
 739 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 740         .bind           = dm_scan_fdt_dev,
 741 #endif
 742         .probe          = rk3288_pinctrl_probe,
 743 };