drivers/pinctrl/rockchip/pinctrl_rk3288.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  * Copyright (c) 2015 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/periph.h>
  18 #include <asm/arch/pmu_rk3288.h>
  19 #include <dm/pinctrl.h>
  20 #include <dm/root.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct rk3288_pinctrl_priv {
  25         struct rk3288_grf *grf;
  26         struct rk3288_pmu *pmu;
  27         int num_banks;
  28 };
  29
  30 /**
  31  * Encode variants of iomux registers into a type variable
  32  */
  33 #define IOMUX_GPIO_ONLY         BIT(0)
  34 #define IOMUX_WIDTH_4BIT        BIT(1)
  35 #define IOMUX_SOURCE_PMU        BIT(2)
  36 #define IOMUX_UNROUTED          BIT(3)
  37
  38 /**
  39  * @type: iomux variant using IOMUX_* constants
  40  * @offset: if initialized to -1 it will be autocalculated, by specifying
  41  *          an initial offset value the relevant source offset can be reset
  42  *          to a new value for autocalculating the following iomux registers.
  43  */
  44 struct rockchip_iomux {
  45         u8 type;
  46         s16 offset;
  47 };
  48
  49 /**
  50  * @reg: register offset of the gpio bank
  51  * @nr_pins: number of pins in this bank
  52  * @bank_num: number of the bank, to account for holes
  53  * @name: name of the bank
  54  * @iomux: array describing the 4 iomux sources of the bank
  55  */
  56 struct rockchip_pin_bank {
  57         u16 reg;
  58         u8 nr_pins;
  59         u8 bank_num;
  60         char *name;
  61         struct rockchip_iomux iomux[4];
  62 };
  63
  64 #define PIN_BANK(id, pins, label)                       \
  65         {                                               \
  66                 .bank_num       = id,                   \
  67                 .nr_pins        = pins,                 \
  68                 .name           = label,                \
  69                 .iomux          = {                     \
  70                         { .offset = -1 },               \
  71                         { .offset = -1 },               \
  72                         { .offset = -1 },               \
  73                         { .offset = -1 },               \
  74                 },                                      \
  75         }
  76
  77 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  78         {                                                               \
  79                 .bank_num       = id,                                   \
  80                 .nr_pins        = pins,                                 \
  81                 .name           = label,                                \
  82                 .iomux          = {                                     \
  83                         { .type = iom0, .offset = -1 },                 \
  84                         { .type = iom1, .offset = -1 },                 \
  85                         { .type = iom2, .offset = -1 },                 \
  86                         { .type = iom3, .offset = -1 },                 \
  87                 },                                                      \
  88         }
  89
  90 #ifndef CONFIG_SPL_BUILD
  91 static struct rockchip_pin_bank rk3288_pin_banks[] = {
  92         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
  93                                              IOMUX_SOURCE_PMU,
  94                                              IOMUX_SOURCE_PMU,
  95                                              IOMUX_UNROUTED
  96                             ),
  97         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
  98                                              IOMUX_UNROUTED,
  99                                              IOMUX_UNROUTED,
 100                                              0
 101                             ),
 102         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
 103         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
 104         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
 105                                              IOMUX_WIDTH_4BIT,
 106                                              0,
 107                                              0
 108                             ),
 109         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
 110                                              0,
 111                                              0,
 112                                              IOMUX_UNROUTED
 113                             ),
 114         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
 115         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
 116                                              0,
 117                                              IOMUX_WIDTH_4BIT,
 118                                              IOMUX_UNROUTED
 119                             ),
 120         PIN_BANK(8, 16, "gpio8"),
 121 };
 122 #endif
 123
 124 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
 125 {
 126         switch (pwm_id) {
 127         case PERIPH_ID_PWM0:
 128                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
 129                              GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
 130                 break;
 131         case PERIPH_ID_PWM1:
 132                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
 133                              GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
 134                 break;
 135         case PERIPH_ID_PWM2:
 136                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
 137                              GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
 138                 break;
 139         case PERIPH_ID_PWM3:
 140                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
 141                              GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
 142                 break;
 143         default:
 144                 debug("pwm id = %d iomux error!\n", pwm_id);
 145                 break;
 146         }
 147 }
 148
 149 static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
 150                                       struct rk3288_pmu *pmu, int i2c_id)
 151 {
 152         switch (i2c_id) {
 153         case PERIPH_ID_I2C0:
 154                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
 155                                 GPIO0_B7_MASK << GPIO0_B7_SHIFT,
 156                                 GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
 157                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
 158                                 GPIO0_C0_MASK << GPIO0_C0_SHIFT,
 159                                 GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
 160                 break;
 161 #ifndef CONFIG_SPL_BUILD
 162         case PERIPH_ID_I2C1:
 163                 rk_clrsetreg(&grf->gpio8a_iomux,
 164                              GPIO8A4_MASK << GPIO8A4_SHIFT |
 165                              GPIO8A5_MASK << GPIO8A5_SHIFT,
 166                              GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
 167                              GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
 168                 break;
 169         case PERIPH_ID_I2C2:
 170                 rk_clrsetreg(&grf->gpio6b_iomux,
 171                              GPIO6B1_MASK << GPIO6B1_SHIFT |
 172                              GPIO6B2_MASK << GPIO6B2_SHIFT,
 173                              GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
 174                              GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
 175                 break;
 176         case PERIPH_ID_I2C3:
 177                 rk_clrsetreg(&grf->gpio2c_iomux,
 178                              GPIO2C1_MASK << GPIO2C1_SHIFT |
 179                              GPIO2C0_MASK << GPIO2C0_SHIFT,
 180                              GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
 181                              GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
 182                 break;
 183         case PERIPH_ID_I2C4:
 184                 rk_clrsetreg(&grf->gpio7cl_iomux,
 185                              GPIO7C1_MASK << GPIO7C1_SHIFT |
 186                              GPIO7C2_MASK << GPIO7C2_SHIFT,
 187                              GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
 188                              GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
 189                 break;
 190         case PERIPH_ID_I2C5:
 191                 rk_clrsetreg(&grf->gpio7cl_iomux,
 192                              GPIO7C3_MASK << GPIO7C3_SHIFT,
 193                              GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
 194                 rk_clrsetreg(&grf->gpio7ch_iomux,
 195                              GPIO7C4_MASK << GPIO7C4_SHIFT,
 196                              GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
 197                 break;
 198 #endif
 199         default:
 200                 debug("i2c id = %d iomux error!\n", i2c_id);
 201                 break;
 202         }
 203 }
 204
 205 #ifndef CONFIG_SPL_BUILD
 206 static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
 207 {
 208         switch (lcd_id) {
 209         case PERIPH_ID_LCDC0:
 210                 rk_clrsetreg(&grf->gpio1d_iomux,
 211                              GPIO1D3_MASK << GPIO1D0_SHIFT |
 212                              GPIO1D2_MASK << GPIO1D2_SHIFT |
 213                              GPIO1D1_MASK << GPIO1D1_SHIFT |
 214                              GPIO1D0_MASK << GPIO1D0_SHIFT,
 215                              GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
 216                              GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
 217                              GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
 218                              GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
 219                 break;
 220         default:
 221                 debug("lcdc id = %d iomux error!\n", lcd_id);
 222                 break;
 223         }
 224 }
 225 #endif
 226
 227 static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
 228                                      enum periph_id spi_id, int cs)
 229 {
 230         switch (spi_id) {
 231 #ifndef CONFIG_SPL_BUILD
 232         case PERIPH_ID_SPI0:
 233                 switch (cs) {
 234                 case 0:
 235                         rk_clrsetreg(&grf->gpio5b_iomux,
 236                                      GPIO5B5_MASK << GPIO5B5_SHIFT,
 237                                      GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
 238                         break;
 239                 case 1:
 240                         rk_clrsetreg(&grf->gpio5c_iomux,
 241                                      GPIO5C0_MASK << GPIO5C0_SHIFT,
 242                                      GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
 243                         break;
 244                 default:
 245                         goto err;
 246                 }
 247                 rk_clrsetreg(&grf->gpio5b_iomux,
 248                              GPIO5B7_MASK << GPIO5B7_SHIFT |
 249                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 250                              GPIO5B4_MASK << GPIO5B4_SHIFT,
 251                              GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
 252                              GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
 253                              GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
 254                 break;
 255         case PERIPH_ID_SPI1:
 256                 if (cs != 0)
 257                         goto err;
 258                 rk_clrsetreg(&grf->gpio7b_iomux,
 259                              GPIO7B6_MASK << GPIO7B6_SHIFT |
 260                              GPIO7B7_MASK << GPIO7B7_SHIFT |
 261                              GPIO7B5_MASK << GPIO7B5_SHIFT |
 262                              GPIO7B4_MASK << GPIO7B4_SHIFT,
 263                              GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
 264                              GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
 265                              GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
 266                              GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
 267                 break;
 268 #endif
 269         case PERIPH_ID_SPI2:
 270                 switch (cs) {
 271                 case 0:
 272                         rk_clrsetreg(&grf->gpio8a_iomux,
 273                                      GPIO8A7_MASK << GPIO8A7_SHIFT,
 274                                      GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
 275                         break;
 276                 case 1:
 277                         rk_clrsetreg(&grf->gpio8a_iomux,
 278                                      GPIO8A3_MASK << GPIO8A3_SHIFT,
 279                                      GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
 280                         break;
 281                 default:
 282                         goto err;
 283                 }
 284                 rk_clrsetreg(&grf->gpio8b_iomux,
 285                              GPIO8B1_MASK << GPIO8B1_SHIFT |
 286                              GPIO8B0_MASK << GPIO8B0_SHIFT,
 287                              GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
 288                              GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
 289                 rk_clrsetreg(&grf->gpio8a_iomux,
 290                              GPIO8A6_MASK << GPIO8A6_SHIFT,
 291                              GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
 292                 break;
 293         default:
 294                 goto err;
 295         }
 296
 297         return 0;
 298 err:
 299         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 300         return -ENOENT;
 301 }
 302
 303 static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
 304 {
 305         switch (uart_id) {
 306 #ifndef CONFIG_SPL_BUILD
 307         case PERIPH_ID_UART_BT:
 308                 rk_clrsetreg(&grf->gpio4c_iomux,
 309                              GPIO4C3_MASK << GPIO4C3_SHIFT |
 310                              GPIO4C2_MASK << GPIO4C2_SHIFT |
 311                              GPIO4C1_MASK << GPIO4C1_SHIFT |
 312                              GPIO4C0_MASK << GPIO4C0_SHIFT,
 313                              GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
 314                              GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
 315                              GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
 316                              GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
 317                 break;
 318         case PERIPH_ID_UART_BB:
 319                 rk_clrsetreg(&grf->gpio5b_iomux,
 320                              GPIO5B3_MASK << GPIO5B3_SHIFT |
 321                              GPIO5B2_MASK << GPIO5B2_SHIFT |
 322                              GPIO5B1_MASK << GPIO5B1_SHIFT |
 323                              GPIO5B0_MASK << GPIO5B0_SHIFT,
 324                              GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
 325                              GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
 326                              GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
 327                              GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
 328                 break;
 329 #endif
 330         case PERIPH_ID_UART_DBG:
 331                 rk_clrsetreg(&grf->gpio7ch_iomux,
 332                              GPIO7C7_MASK << GPIO7C7_SHIFT |
 333                              GPIO7C6_MASK << GPIO7C6_SHIFT,
 334                              GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 335                              GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 336                 break;
 337 #ifndef CONFIG_SPL_BUILD
 338         case PERIPH_ID_UART_GPS:
 339                 rk_clrsetreg(&grf->gpio7b_iomux,
 340                              GPIO7B2_MASK << GPIO7B2_SHIFT |
 341                              GPIO7B1_MASK << GPIO7B1_SHIFT |
 342                              GPIO7B0_MASK << GPIO7B0_SHIFT,
 343                              GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
 344                              GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
 345                              GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
 346                 rk_clrsetreg(&grf->gpio7a_iomux,
 347                              GPIO7A7_MASK << GPIO7A7_SHIFT,
 348                              GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
 349                 break;
 350         case PERIPH_ID_UART_EXP:
 351                 rk_clrsetreg(&grf->gpio5b_iomux,
 352                              GPIO5B5_MASK << GPIO5B5_SHIFT |
 353                              GPIO5B4_MASK << GPIO5B4_SHIFT |
 354                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 355                              GPIO5B7_MASK << GPIO5B7_SHIFT,
 356                              GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
 357                              GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
 358                              GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
 359                              GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
 360                 break;
 361 #endif
 362         default:
 363                 debug("uart id = %d iomux error!\n", uart_id);
 364                 break;
 365         }
 366 }
 367
 368 static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
 369 {
 370         switch (mmc_id) {
 371         case PERIPH_ID_EMMC:
 372                 rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
 373                              GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
 374                              GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
 375                              GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
 376                              GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
 377                              GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
 378                              GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
 379                              GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
 380                              GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
 381                 rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
 382                              GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
 383                 rk_clrsetreg(&grf->gpio3c_iomux,
 384                              GPIO3C0_MASK << GPIO3C0_SHIFT,
 385                              GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
 386                 break;
 387         case PERIPH_ID_SDCARD:
 388                 rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
 389                              GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
 390                              GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
 391                              GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
 392                              GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
 393                              GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
 394                              GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
 395                              GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
 396
 397                 /* use sdmmc0 io, disable JTAG function */
 398                 rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
 399                 break;
 400         default:
 401                 debug("mmc id = %d iomux error!\n", mmc_id);
 402                 break;
 403         }
 404 }
 405
 406 #ifndef CONFIG_SPL_BUILD
 407 static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
 408 {
 409         switch (hdmi_id) {
 410         case PERIPH_ID_HDMI:
 411                 rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
 412                              GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
 413                 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
 414                              GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
 415                 break;
 416         default:
 417                 debug("hdmi id = %d iomux error!\n", hdmi_id);
 418                 break;
 419         }
 420 }
 421 #endif
 422
 423 static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
 424 {
 425         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 426
 427         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 428         switch (func) {
 429         case PERIPH_ID_PWM0:
 430         case PERIPH_ID_PWM1:
 431         case PERIPH_ID_PWM2:
 432         case PERIPH_ID_PWM3:
 433         case PERIPH_ID_PWM4:
 434                 pinctrl_rk3288_pwm_config(priv->grf, func);
 435                 break;
 436         case PERIPH_ID_I2C0:
 437         case PERIPH_ID_I2C1:
 438         case PERIPH_ID_I2C2:
 439         case PERIPH_ID_I2C3:
 440         case PERIPH_ID_I2C4:
 441         case PERIPH_ID_I2C5:
 442                 pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
 443                 break;
 444         case PERIPH_ID_SPI0:
 445         case PERIPH_ID_SPI1:
 446         case PERIPH_ID_SPI2:
 447                 pinctrl_rk3288_spi_config(priv->grf, func, flags);
 448                 break;
 449         case PERIPH_ID_UART0:
 450         case PERIPH_ID_UART1:
 451         case PERIPH_ID_UART2:
 452         case PERIPH_ID_UART3:
 453         case PERIPH_ID_UART4:
 454                 pinctrl_rk3288_uart_config(priv->grf, func);
 455                 break;
 456 #ifndef CONFIG_SPL_BUILD
 457         case PERIPH_ID_LCDC0:
 458         case PERIPH_ID_LCDC1:
 459                 pinctrl_rk3288_lcdc_config(priv->grf, func);
 460                 break;
 461         case PERIPH_ID_HDMI:
 462                 pinctrl_rk3288_hdmi_config(priv->grf, func);
 463                 break;
 464 #endif
 465         case PERIPH_ID_SDMMC0:
 466         case PERIPH_ID_SDMMC1:
 467                 pinctrl_rk3288_sdmmc_config(priv->grf, func);
 468                 break;
 469         default:
 470                 return -EINVAL;
 471         }
 472
 473         return 0;
 474 }
 475
 476 static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 477                                         struct udevice *periph)
 478 {
 479 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 480         u32 cell[3];
 481         int ret;
 482
 483         ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
 484                                    "interrupts", cell, ARRAY_SIZE(cell));
 485         if (ret < 0)
 486                 return -EINVAL;
 487
 488         switch (cell[1]) {
 489         case 44:
 490                 return PERIPH_ID_SPI0;
 491         case 45:
 492                 return PERIPH_ID_SPI1;
 493         case 46:
 494                 return PERIPH_ID_SPI2;
 495         case 60:
 496                 return PERIPH_ID_I2C0;
 497         case 62: /* Note strange order */
 498                 return PERIPH_ID_I2C1;
 499         case 61:
 500                 return PERIPH_ID_I2C2;
 501         case 63:
 502                 return PERIPH_ID_I2C3;
 503         case 64:
 504                 return PERIPH_ID_I2C4;
 505         case 65:
 506                 return PERIPH_ID_I2C5;
 507         case 103:
 508                 return PERIPH_ID_HDMI;
 509         }
 510 #endif
 511
 512         return -ENOENT;
 513 }
 514
 515 static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
 516                                            struct udevice *periph)
 517 {
 518         int func;
 519
 520         func = rk3288_pinctrl_get_periph_id(dev, periph);
 521         if (func < 0)
 522                 return func;
 523         return rk3288_pinctrl_request(dev, func, 0);
 524 }
 525
 526 #ifndef CONFIG_SPL_BUILD
 527 int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv,
 528                                 int banknum, int ind, u32 **addrp, uint *shiftp,
 529                                 uint *maskp)
 530 {
 531         struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
 532         uint muxnum;
 533         u32 *addr;
 534
 535         for (muxnum = 0; muxnum < 4; muxnum++) {
 536                 struct rockchip_iomux *mux = &bank->iomux[muxnum];
 537
 538                 if (ind >= 8) {
 539                         ind -= 8;
 540                         continue;
 541                 }
 542
 543                 if (mux->type & IOMUX_SOURCE_PMU)
 544                         addr = priv->pmu->gpio0_iomux;
 545                 else
 546                         addr = (u32 *)priv->grf - 4;
 547                 addr += mux->offset;
 548                 *shiftp = ind & 7;
 549                 if (mux->type & IOMUX_WIDTH_4BIT) {
 550                         *maskp = 0xf;
 551                         *shiftp *= 4;
 552                         if (*shiftp >= 16) {
 553                                 *shiftp -= 16;
 554                                 addr++;
 555                         }
 556                 } else {
 557                         *maskp = 3;
 558                         *shiftp *= 2;
 559                 }
 560
 561                 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
 562                       *maskp, *shiftp);
 563                 *addrp = addr;
 564                 return 0;
 565         }
 566
 567         return -EINVAL;
 568 }
 569
 570 static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 571                                        int index)
 572 {
 573         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 574         uint shift;
 575         uint mask;
 576         u32 *addr;
 577         int ret;
 578
 579         ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 580                                           &mask);
 581         if (ret)
 582                 return ret;
 583         return (readl(addr) & mask) >> shift;
 584 }
 585
 586 static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 587                                    int muxval, int flags)
 588 {
 589         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 590         uint shift, ind = index;
 591         uint mask;
 592         u32 *addr;
 593         int ret;
 594
 595         debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
 596         ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 597                                           &mask);
 598         if (ret)
 599                 return ret;
 600         rk_clrsetreg(addr, mask << shift, muxval << shift);
 601
 602         /* Handle pullup/pulldown */
 603         if (flags) {
 604                 uint val = 0;
 605
 606                 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
 607                         val = 1;
 608                 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 609                         val = 2;
 610                 shift = (index & 7) * 2;
 611                 ind = index >> 3;
 612                 if (banknum == 0)
 613                         addr = &priv->pmu->gpio0pull[ind];
 614                 else
 615                         addr = &priv->grf->gpio1_p[banknum - 1][ind];
 616                 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 617                       shift);
 618                 rk_clrsetreg(addr, 3 << shift, val << shift);
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 625 {
 626         const void *blob = gd->fdt_blob;
 627         int pcfg_node, ret, flags, count, i;
 628         u32 cell[60], *ptr;
 629
 630         debug("%s: %s %s\n", __func__, dev->name, config->name);
 631         ret = fdtdec_get_int_array_count(blob, config->of_offset,
 632                                          "rockchip,pins", cell,
 633                                          ARRAY_SIZE(cell));
 634         if (ret < 0) {
 635                 debug("%s: bad array %d\n", __func__, ret);
 636                 return -EINVAL;
 637         }
 638         count = ret;
 639         for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
 640                 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
 641                 if (pcfg_node < 0)
 642                         return -EINVAL;
 643                 flags = pinctrl_decode_pin_config(blob, pcfg_node);
 644                 if (flags < 0)
 645                         return flags;
 646
 647                 ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
 648                                               flags);
 649                 if (ret)
 650                         return ret;
 651         }
 652
 653         return 0;
 654 }
 655 #endif
 656
 657 static struct pinctrl_ops rk3288_pinctrl_ops = {
 658 #ifndef CONFIG_SPL_BUILD
 659         .set_state      = rk3288_pinctrl_set_state,
 660         .get_gpio_mux   = rk3288_pinctrl_get_gpio_mux,
 661 #endif
 662         .set_state_simple       = rk3288_pinctrl_set_state_simple,
 663         .request        = rk3288_pinctrl_request,
 664         .get_periph_id  = rk3288_pinctrl_get_periph_id,
 665 };
 666
 667 static int rk3288_pinctrl_bind(struct udevice *dev)
 668 {
 669 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 670         return 0;
 671 #else
 672         /* scan child GPIO banks */
 673         return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
 674 #endif
 675 }
 676
 677 #ifndef CONFIG_SPL_BUILD
 678 static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
 679                                        struct rockchip_pin_bank *banks,
 680                                        int count)
 681 {
 682         struct rockchip_pin_bank *bank;
 683         uint reg, muxnum, banknum;
 684
 685         reg = 0;
 686         for (banknum = 0; banknum < count; banknum++) {
 687                 bank = &banks[banknum];
 688                 bank->reg = reg;
 689                 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
 690                 for (muxnum = 0; muxnum < 4; muxnum++) {
 691                         struct rockchip_iomux *mux = &bank->iomux[muxnum];
 692
 693                         if (!(mux->type & IOMUX_UNROUTED))
 694                                 mux->offset = reg;
 695                         if (mux->type & IOMUX_WIDTH_4BIT)
 696                                 reg += 2;
 697                         else
 698                                 reg += 1;
 699                 }
 700         }
 701
 702         return 0;
 703 }
 704 #endif
 705
 706 static int rk3288_pinctrl_probe(struct udevice *dev)
 707 {
 708         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 709         int ret = 0;
 710
 711         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 712         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 713         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 714 #ifndef CONFIG_SPL_BUILD
 715         ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
 716                                           ARRAY_SIZE(rk3288_pin_banks));
 717 #endif
 718
 719         return ret;
 720 }
 721
 722 static const struct udevice_id rk3288_pinctrl_ids[] = {
 723         { .compatible = "rockchip,rk3288-pinctrl" },
 724         { }
 725 };
 726
 727 U_BOOT_DRIVER(pinctrl_rk3288) = {
 728         .name           = "rockchip_rk3288_pinctrl",
 729         .id             = UCLASS_PINCTRL,
 730         .of_match       = rk3288_pinctrl_ids,
 731         .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
 732         .ops            = &rk3288_pinctrl_ops,
 733         .bind           = rk3288_pinctrl_bind,
 734         .probe          = rk3288_pinctrl_probe,
 735 };