drivers/pinctrl/rockchip/pinctrl_rk3288.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  * Copyright (c) 2015 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/periph.h>
  18 #include <asm/arch/pmu_rk3288.h>
  19 #include <dm/pinctrl.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct rk3288_pinctrl_priv {
  24         struct rk3288_grf *grf;
  25         struct rk3288_pmu *pmu;
  26         int num_banks;
  27 };
  28
  29 /**
  30  * Encode variants of iomux registers into a type variable
  31  */
  32 #define IOMUX_GPIO_ONLY         BIT(0)
  33 #define IOMUX_WIDTH_4BIT        BIT(1)
  34 #define IOMUX_SOURCE_PMU        BIT(2)
  35 #define IOMUX_UNROUTED          BIT(3)
  36
  37 /**
  38  * @type: iomux variant using IOMUX_* constants
  39  * @offset: if initialized to -1 it will be autocalculated, by specifying
  40  *          an initial offset value the relevant source offset can be reset
  41  *          to a new value for autocalculating the following iomux registers.
  42  */
  43 struct rockchip_iomux {
  44         u8 type;
  45         s16 offset;
  46 };
  47
  48 /**
  49  * @reg: register offset of the gpio bank
  50  * @nr_pins: number of pins in this bank
  51  * @bank_num: number of the bank, to account for holes
  52  * @name: name of the bank
  53  * @iomux: array describing the 4 iomux sources of the bank
  54  */
  55 struct rockchip_pin_bank {
  56         u16 reg;
  57         u8 nr_pins;
  58         u8 bank_num;
  59         char *name;
  60         struct rockchip_iomux iomux[4];
  61 };
  62
  63 #define PIN_BANK(id, pins, label)                       \
  64         {                                               \
  65                 .bank_num       = id,                   \
  66                 .nr_pins        = pins,                 \
  67                 .name           = label,                \
  68                 .iomux          = {                     \
  69                         { .offset = -1 },               \
  70                         { .offset = -1 },               \
  71                         { .offset = -1 },               \
  72                         { .offset = -1 },               \
  73                 },                                      \
  74         }
  75
  76 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  77         {                                                               \
  78                 .bank_num       = id,                                   \
  79                 .nr_pins        = pins,                                 \
  80                 .name           = label,                                \
  81                 .iomux          = {                                     \
  82                         { .type = iom0, .offset = -1 },                 \
  83                         { .type = iom1, .offset = -1 },                 \
  84                         { .type = iom2, .offset = -1 },                 \
  85                         { .type = iom3, .offset = -1 },                 \
  86                 },                                                      \
  87         }
  88
  89 #ifndef CONFIG_SPL_BUILD
  90 static struct rockchip_pin_bank rk3288_pin_banks[] = {
  91         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
  92                                              IOMUX_SOURCE_PMU,
  93                                              IOMUX_SOURCE_PMU,
  94                                              IOMUX_UNROUTED
  95                             ),
  96         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
  97                                              IOMUX_UNROUTED,
  98                                              IOMUX_UNROUTED,
  99                                              0
 100                             ),
 101         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
 102         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
 103         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
 104                                              IOMUX_WIDTH_4BIT,
 105                                              0,
 106                                              0
 107                             ),
 108         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
 109                                              0,
 110                                              0,
 111                                              IOMUX_UNROUTED
 112                             ),
 113         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
 114         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
 115                                              0,
 116                                              IOMUX_WIDTH_4BIT,
 117                                              IOMUX_UNROUTED
 118                             ),
 119         PIN_BANK(8, 16, "gpio8"),
 120 };
 121 #endif
 122
 123 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
 124 {
 125         switch (pwm_id) {
 126         case PERIPH_ID_PWM0:
 127                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
 128                              GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
 129                 break;
 130         case PERIPH_ID_PWM1:
 131                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
 132                              GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
 133                 break;
 134         case PERIPH_ID_PWM2:
 135                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
 136                              GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
 137                 break;
 138         case PERIPH_ID_PWM3:
 139                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
 140                              GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
 141                 break;
 142         default:
 143                 debug("pwm id = %d iomux error!\n", pwm_id);
 144                 break;
 145         }
 146 }
 147
 148 static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
 149                                       struct rk3288_pmu *pmu, int i2c_id)
 150 {
 151         switch (i2c_id) {
 152         case PERIPH_ID_I2C0:
 153                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
 154                                 GPIO0_B7_MASK << GPIO0_B7_SHIFT,
 155                                 GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
 156                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
 157                                 GPIO0_C0_MASK << GPIO0_C0_SHIFT,
 158                                 GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
 159                 break;
 160 #ifndef CONFIG_SPL_BUILD
 161         case PERIPH_ID_I2C1:
 162                 rk_clrsetreg(&grf->gpio8a_iomux,
 163                              GPIO8A4_MASK << GPIO8A4_SHIFT |
 164                              GPIO8A5_MASK << GPIO8A5_SHIFT,
 165                              GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
 166                              GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
 167                 break;
 168         case PERIPH_ID_I2C2:
 169                 rk_clrsetreg(&grf->gpio6b_iomux,
 170                              GPIO6B1_MASK << GPIO6B1_SHIFT |
 171                              GPIO6B2_MASK << GPIO6B2_SHIFT,
 172                              GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
 173                              GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
 174                 break;
 175         case PERIPH_ID_I2C3:
 176                 rk_clrsetreg(&grf->gpio2c_iomux,
 177                              GPIO2C1_MASK << GPIO2C1_SHIFT |
 178                              GPIO2C0_MASK << GPIO2C0_SHIFT,
 179                              GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
 180                              GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
 181                 break;
 182         case PERIPH_ID_I2C4:
 183                 rk_clrsetreg(&grf->gpio7cl_iomux,
 184                              GPIO7C1_MASK << GPIO7C1_SHIFT |
 185                              GPIO7C2_MASK << GPIO7C2_SHIFT,
 186                              GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
 187                              GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
 188                 break;
 189         case PERIPH_ID_I2C5:
 190                 rk_clrsetreg(&grf->gpio7cl_iomux,
 191                              GPIO7C3_MASK << GPIO7C3_SHIFT,
 192                              GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
 193                 rk_clrsetreg(&grf->gpio7ch_iomux,
 194                              GPIO7C4_MASK << GPIO7C4_SHIFT,
 195                              GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
 196                 break;
 197 #endif
 198         default:
 199                 debug("i2c id = %d iomux error!\n", i2c_id);
 200                 break;
 201         }
 202 }
 203
 204 #ifndef CONFIG_SPL_BUILD
 205 static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
 206 {
 207         switch (lcd_id) {
 208         case PERIPH_ID_LCDC0:
 209                 rk_clrsetreg(&grf->gpio1d_iomux,
 210                              GPIO1D3_MASK << GPIO1D0_SHIFT |
 211                              GPIO1D2_MASK << GPIO1D2_SHIFT |
 212                              GPIO1D1_MASK << GPIO1D1_SHIFT |
 213                              GPIO1D0_MASK << GPIO1D0_SHIFT,
 214                              GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
 215                              GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
 216                              GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
 217                              GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
 218                 break;
 219         default:
 220                 debug("lcdc id = %d iomux error!\n", lcd_id);
 221                 break;
 222         }
 223 }
 224 #endif
 225
 226 static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
 227                                      enum periph_id spi_id, int cs)
 228 {
 229         switch (spi_id) {
 230 #ifndef CONFIG_SPL_BUILD
 231         case PERIPH_ID_SPI0:
 232                 switch (cs) {
 233                 case 0:
 234                         rk_clrsetreg(&grf->gpio5b_iomux,
 235                                      GPIO5B5_MASK << GPIO5B5_SHIFT,
 236                                      GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
 237                         break;
 238                 case 1:
 239                         rk_clrsetreg(&grf->gpio5c_iomux,
 240                                      GPIO5C0_MASK << GPIO5C0_SHIFT,
 241                                      GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
 242                         break;
 243                 default:
 244                         goto err;
 245                 }
 246                 rk_clrsetreg(&grf->gpio5b_iomux,
 247                              GPIO5B7_MASK << GPIO5B7_SHIFT |
 248                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 249                              GPIO5B4_MASK << GPIO5B4_SHIFT,
 250                              GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
 251                              GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
 252                              GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
 253                 break;
 254         case PERIPH_ID_SPI1:
 255                 if (cs != 0)
 256                         goto err;
 257                 rk_clrsetreg(&grf->gpio7b_iomux,
 258                              GPIO7B6_MASK << GPIO7B6_SHIFT |
 259                              GPIO7B7_MASK << GPIO7B7_SHIFT |
 260                              GPIO7B5_MASK << GPIO7B5_SHIFT |
 261                              GPIO7B4_MASK << GPIO7B4_SHIFT,
 262                              GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
 263                              GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
 264                              GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
 265                              GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
 266                 break;
 267 #endif
 268         case PERIPH_ID_SPI2:
 269                 switch (cs) {
 270                 case 0:
 271                         rk_clrsetreg(&grf->gpio8a_iomux,
 272                                      GPIO8A7_MASK << GPIO8A7_SHIFT,
 273                                      GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
 274                         break;
 275                 case 1:
 276                         rk_clrsetreg(&grf->gpio8a_iomux,
 277                                      GPIO8A3_MASK << GPIO8A3_SHIFT,
 278                                      GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
 279                         break;
 280                 default:
 281                         goto err;
 282                 }
 283                 rk_clrsetreg(&grf->gpio8b_iomux,
 284                              GPIO8B1_MASK << GPIO8B1_SHIFT |
 285                              GPIO8B0_MASK << GPIO8B0_SHIFT,
 286                              GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
 287                              GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
 288                 rk_clrsetreg(&grf->gpio8a_iomux,
 289                              GPIO8A6_MASK << GPIO8A6_SHIFT,
 290                              GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
 291                 break;
 292         default:
 293                 goto err;
 294         }
 295
 296         return 0;
 297 err:
 298         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 299         return -ENOENT;
 300 }
 301
 302 static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
 303 {
 304         switch (uart_id) {
 305 #ifndef CONFIG_SPL_BUILD
 306         case PERIPH_ID_UART_BT:
 307                 rk_clrsetreg(&grf->gpio4c_iomux,
 308                              GPIO4C3_MASK << GPIO4C3_SHIFT |
 309                              GPIO4C2_MASK << GPIO4C2_SHIFT |
 310                              GPIO4C1_MASK << GPIO4C1_SHIFT |
 311                              GPIO4C0_MASK << GPIO4C0_SHIFT,
 312                              GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
 313                              GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
 314                              GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
 315                              GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
 316                 break;
 317         case PERIPH_ID_UART_BB:
 318                 rk_clrsetreg(&grf->gpio5b_iomux,
 319                              GPIO5B3_MASK << GPIO5B3_SHIFT |
 320                              GPIO5B2_MASK << GPIO5B2_SHIFT |
 321                              GPIO5B1_MASK << GPIO5B1_SHIFT |
 322                              GPIO5B0_MASK << GPIO5B0_SHIFT,
 323                              GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
 324                              GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
 325                              GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
 326                              GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
 327                 break;
 328 #endif
 329         case PERIPH_ID_UART_DBG:
 330                 rk_clrsetreg(&grf->gpio7ch_iomux,
 331                              GPIO7C7_MASK << GPIO7C7_SHIFT |
 332                              GPIO7C6_MASK << GPIO7C6_SHIFT,
 333                              GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 334                              GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 335                 break;
 336 #ifndef CONFIG_SPL_BUILD
 337         case PERIPH_ID_UART_GPS:
 338                 rk_clrsetreg(&grf->gpio7b_iomux,
 339                              GPIO7B2_MASK << GPIO7B2_SHIFT |
 340                              GPIO7B1_MASK << GPIO7B1_SHIFT |
 341                              GPIO7B0_MASK << GPIO7B0_SHIFT,
 342                              GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
 343                              GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
 344                              GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
 345                 rk_clrsetreg(&grf->gpio7a_iomux,
 346                              GPIO7A7_MASK << GPIO7A7_SHIFT,
 347                              GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
 348                 break;
 349         case PERIPH_ID_UART_EXP:
 350                 rk_clrsetreg(&grf->gpio5b_iomux,
 351                              GPIO5B5_MASK << GPIO5B5_SHIFT |
 352                              GPIO5B4_MASK << GPIO5B4_SHIFT |
 353                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 354                              GPIO5B7_MASK << GPIO5B7_SHIFT,
 355                              GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
 356                              GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
 357                              GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
 358                              GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
 359                 break;
 360 #endif
 361         default:
 362                 debug("uart id = %d iomux error!\n", uart_id);
 363                 break;
 364         }
 365 }
 366
 367 static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
 368 {
 369         switch (mmc_id) {
 370         case PERIPH_ID_EMMC:
 371                 rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
 372                              GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
 373                              GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
 374                              GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
 375                              GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
 376                              GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
 377                              GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
 378                              GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
 379                              GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
 380                 rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
 381                              GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
 382                 rk_clrsetreg(&grf->gpio3c_iomux,
 383                              GPIO3C0_MASK << GPIO3C0_SHIFT,
 384                              GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
 385                 break;
 386         case PERIPH_ID_SDCARD:
 387                 rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
 388                              GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
 389                              GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
 390                              GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
 391                              GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
 392                              GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
 393                              GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
 394                              GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
 395
 396                 /* use sdmmc0 io, disable JTAG function */
 397                 rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
 398                 break;
 399         default:
 400                 debug("mmc id = %d iomux error!\n", mmc_id);
 401                 break;
 402         }
 403 }
 404
 405 static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id)
 406 {
 407         switch (gmac_id) {
 408         case PERIPH_ID_GMAC:
 409                 rk_clrsetreg(&grf->gpio3dl_iomux,
 410                              GPIO3D3_MASK << GPIO3D3_SHIFT |
 411                              GPIO3D2_MASK << GPIO3D2_SHIFT |
 412                              GPIO3D2_MASK << GPIO3D1_SHIFT |
 413                              GPIO3D0_MASK << GPIO3D0_SHIFT,
 414                              GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT |
 415                              GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT |
 416                              GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT |
 417                              GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT);
 418
 419                 rk_clrsetreg(&grf->gpio3dh_iomux,
 420                              GPIO3D7_MASK << GPIO3D7_SHIFT |
 421                              GPIO3D6_MASK << GPIO3D6_SHIFT |
 422                              GPIO3D5_MASK << GPIO3D5_SHIFT |
 423                              GPIO3D4_MASK << GPIO3D4_SHIFT,
 424                              GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT |
 425                              GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT |
 426                              GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT |
 427                              GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT);
 428
 429                 /* switch the Tx pins to 12ma drive-strength */
 430                 rk_clrsetreg(&grf->gpio1_e[2][3],
 431                              GPIO_BIAS_MASK |
 432                              (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) |
 433                              (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) |
 434                              (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)),
 435                              (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) |
 436                              (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) |
 437                              (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) |
 438                              (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5)));
 439
 440                 /* Set normal pull for all GPIO3D pins */
 441                 rk_clrsetreg(&grf->gpio1_p[2][3],
 442                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
 443                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
 444                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
 445                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
 446                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
 447                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
 448                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
 449                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
 450                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
 451                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
 452                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
 453                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
 454                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
 455                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
 456                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
 457                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
 458
 459                 rk_clrsetreg(&grf->gpio4al_iomux,
 460                              GPIO4A3_MASK << GPIO4A3_SHIFT |
 461                              GPIO4A1_MASK << GPIO4A1_SHIFT |
 462                              GPIO4A0_MASK << GPIO4A0_SHIFT,
 463                              GPIO4A3_MAC_CLK << GPIO4A3_SHIFT |
 464                              GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT |
 465                              GPIO4A0_MAC_MDC << GPIO4A0_SHIFT);
 466
 467                 rk_clrsetreg(&grf->gpio4ah_iomux,
 468                              GPIO4A6_MASK << GPIO4A6_SHIFT |
 469                              GPIO4A5_MASK << GPIO4A5_SHIFT |
 470                              GPIO4A4_MASK << GPIO4A4_SHIFT,
 471                              GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT |
 472                              GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT |
 473                              GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT);
 474
 475                 /* switch GPIO4A4 to 12ma drive-strength */
 476                 rk_clrsetreg(&grf->gpio1_e[3][0],
 477                              GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4),
 478                              GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4));
 479
 480                 /* Set normal pull for all GPIO4A pins */
 481                 rk_clrsetreg(&grf->gpio1_p[3][0],
 482                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
 483                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
 484                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
 485                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
 486                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
 487                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
 488                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
 489                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
 490                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
 491                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
 492                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
 493                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
 494                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
 495                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
 496                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
 497                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
 498
 499                 rk_clrsetreg(&grf->gpio4bl_iomux,
 500                             GPIO4B1_MASK << GPIO4B1_SHIFT,
 501                             GPIO4B1_MAC_TXCLK << GPIO4B1_SHIFT);
 502
 503                 /* switch GPIO4B1 to 12ma drive-strength */
 504                 rk_clrsetreg(&grf->gpio1_e[3][1],
 505                              GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1),
 506                              GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1));
 507
 508                 /* Set pull normal for GPIO4B1 */
 509                 rk_clrsetreg(&grf->gpio1_p[3][1],
 510                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)),
 511                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)));
 512
 513                 break;
 514         default:
 515                 printf("gmac id = %d iomux error!\n", gmac_id);
 516                 break;
 517         }
 518 }
 519
 520 #ifndef CONFIG_SPL_BUILD
 521 static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
 522 {
 523         switch (hdmi_id) {
 524         case PERIPH_ID_HDMI:
 525                 rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
 526                              GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
 527                 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
 528                              GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
 529                 break;
 530         default:
 531                 debug("hdmi id = %d iomux error!\n", hdmi_id);
 532                 break;
 533         }
 534 }
 535 #endif
 536
 537 static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
 538 {
 539         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 540
 541         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 542         switch (func) {
 543         case PERIPH_ID_PWM0:
 544         case PERIPH_ID_PWM1:
 545         case PERIPH_ID_PWM2:
 546         case PERIPH_ID_PWM3:
 547         case PERIPH_ID_PWM4:
 548                 pinctrl_rk3288_pwm_config(priv->grf, func);
 549                 break;
 550         case PERIPH_ID_I2C0:
 551         case PERIPH_ID_I2C1:
 552         case PERIPH_ID_I2C2:
 553         case PERIPH_ID_I2C3:
 554         case PERIPH_ID_I2C4:
 555         case PERIPH_ID_I2C5:
 556                 pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
 557                 break;
 558         case PERIPH_ID_SPI0:
 559         case PERIPH_ID_SPI1:
 560         case PERIPH_ID_SPI2:
 561                 pinctrl_rk3288_spi_config(priv->grf, func, flags);
 562                 break;
 563         case PERIPH_ID_UART0:
 564         case PERIPH_ID_UART1:
 565         case PERIPH_ID_UART2:
 566         case PERIPH_ID_UART3:
 567         case PERIPH_ID_UART4:
 568                 pinctrl_rk3288_uart_config(priv->grf, func);
 569                 break;
 570 #ifndef CONFIG_SPL_BUILD
 571         case PERIPH_ID_LCDC0:
 572         case PERIPH_ID_LCDC1:
 573                 pinctrl_rk3288_lcdc_config(priv->grf, func);
 574                 break;
 575         case PERIPH_ID_HDMI:
 576                 pinctrl_rk3288_hdmi_config(priv->grf, func);
 577                 break;
 578 #endif
 579         case PERIPH_ID_SDMMC0:
 580         case PERIPH_ID_SDMMC1:
 581                 pinctrl_rk3288_sdmmc_config(priv->grf, func);
 582                 break;
 583         case PERIPH_ID_GMAC:
 584                 pinctrl_rk3288_gmac_config(priv->grf, func);
 585                 break;
 586         default:
 587                 return -EINVAL;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 594                                         struct udevice *periph)
 595 {
 596 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 597         u32 cell[3];
 598         int ret;
 599
 600         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 601         if (ret < 0)
 602                 return -EINVAL;
 603
 604         switch (cell[1]) {
 605         case 27:
 606                 return PERIPH_ID_GMAC;
 607         case 44:
 608                 return PERIPH_ID_SPI0;
 609         case 45:
 610                 return PERIPH_ID_SPI1;
 611         case 46:
 612                 return PERIPH_ID_SPI2;
 613         case 60:
 614                 return PERIPH_ID_I2C0;
 615         case 62: /* Note strange order */
 616                 return PERIPH_ID_I2C1;
 617         case 61:
 618                 return PERIPH_ID_I2C2;
 619         case 63:
 620                 return PERIPH_ID_I2C3;
 621         case 64:
 622                 return PERIPH_ID_I2C4;
 623         case 65:
 624                 return PERIPH_ID_I2C5;
 625         case 103:
 626                 return PERIPH_ID_HDMI;
 627         }
 628 #endif
 629
 630         return -ENOENT;
 631 }
 632
 633 static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
 634                                            struct udevice *periph)
 635 {
 636         int func;
 637
 638         func = rk3288_pinctrl_get_periph_id(dev, periph);
 639         if (func < 0)
 640                 return func;
 641         return rk3288_pinctrl_request(dev, func, 0);
 642 }
 643
 644 #ifndef CONFIG_SPL_BUILD
 645 int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv,
 646                                 int banknum, int ind, u32 **addrp, uint *shiftp,
 647                                 uint *maskp)
 648 {
 649         struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
 650         uint muxnum;
 651         u32 *addr;
 652
 653         for (muxnum = 0; muxnum < 4; muxnum++) {
 654                 struct rockchip_iomux *mux = &bank->iomux[muxnum];
 655
 656                 if (ind >= 8) {
 657                         ind -= 8;
 658                         continue;
 659                 }
 660
 661                 if (mux->type & IOMUX_SOURCE_PMU)
 662                         addr = priv->pmu->gpio0_iomux;
 663                 else
 664                         addr = (u32 *)priv->grf - 4;
 665                 addr += mux->offset;
 666                 *shiftp = ind & 7;
 667                 if (mux->type & IOMUX_WIDTH_4BIT) {
 668                         *maskp = 0xf;
 669                         *shiftp *= 4;
 670                         if (*shiftp >= 16) {
 671                                 *shiftp -= 16;
 672                                 addr++;
 673                         }
 674                 } else {
 675                         *maskp = 3;
 676                         *shiftp *= 2;
 677                 }
 678
 679                 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
 680                       *maskp, *shiftp);
 681                 *addrp = addr;
 682                 return 0;
 683         }
 684
 685         return -EINVAL;
 686 }
 687
 688 static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 689                                        int index)
 690 {
 691         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 692         uint shift;
 693         uint mask;
 694         u32 *addr;
 695         int ret;
 696
 697         ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 698                                           &mask);
 699         if (ret)
 700                 return ret;
 701         return (readl(addr) & mask) >> shift;
 702 }
 703
 704 static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 705                                    int muxval, int flags)
 706 {
 707         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 708         uint shift, ind = index;
 709         uint mask;
 710         uint value;
 711         u32 *addr;
 712         int ret;
 713
 714         debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
 715         ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 716                                           &mask);
 717         if (ret)
 718                 return ret;
 719
 720         /*
 721          * PMU_GPIO0 registers cannot be selectively written so we cannot use
 722          * rk_clrsetreg() here.  However, the upper 16 bits are reserved and
 723          * are ignored when written, so we can use the same code as for the
 724          * other GPIO banks providing that we preserve the value of the other
 725          * bits.
 726          */
 727         value = readl(addr);
 728         value &= ~(mask << shift);
 729         value |= (mask << (shift + 16)) | (muxval << shift);
 730         writel(value, addr);
 731
 732         /* Handle pullup/pulldown/drive-strength */
 733         if (flags) {
 734                 uint val = 0;
 735
 736                 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
 737                         val = 1;
 738                 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 739                         val = 2;
 740                 else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
 741                         val = 3;
 742
 743                 shift = (index & 7) * 2;
 744                 ind = index >> 3;
 745                 if (banknum == 0)
 746                         addr = &priv->pmu->gpio0pull[ind];
 747                 else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
 748                         addr = &priv->grf->gpio1_e[banknum - 1][ind];
 749                 else
 750                         addr = &priv->grf->gpio1_p[banknum - 1][ind];
 751                 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 752                       shift);
 753
 754                 /* As above, rk_clrsetreg() cannot be used here. */
 755                 value = readl(addr);
 756                 value &= ~(mask << shift);
 757                 value |= (3 << (shift + 16)) | (val << shift);
 758                 writel(value, addr);
 759         }
 760
 761         return 0;
 762 }
 763
 764 static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 765 {
 766         const void *blob = gd->fdt_blob;
 767         int pcfg_node, ret, flags, count, i;
 768         u32 cell[60], *ptr;
 769
 770         debug("%s: %s %s\n", __func__, dev->name, config->name);
 771         ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
 772                                          "rockchip,pins", cell,
 773                                          ARRAY_SIZE(cell));
 774         if (ret < 0) {
 775                 debug("%s: bad array %d\n", __func__, ret);
 776                 return -EINVAL;
 777         }
 778         count = ret;
 779         for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
 780                 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
 781                 if (pcfg_node < 0)
 782                         return -EINVAL;
 783                 flags = pinctrl_decode_pin_config(blob, pcfg_node);
 784                 if (flags < 0)
 785                         return flags;
 786
 787                 if (fdtdec_get_int(blob, pcfg_node, "drive-strength", 0) == 12)
 788                         flags |= 1 << PIN_CONFIG_DRIVE_STRENGTH;
 789
 790                 ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
 791                                               flags);
 792                 if (ret)
 793                         return ret;
 794         }
 795
 796         return 0;
 797 }
 798 #endif
 799
 800 static struct pinctrl_ops rk3288_pinctrl_ops = {
 801 #ifndef CONFIG_SPL_BUILD
 802         .set_state      = rk3288_pinctrl_set_state,
 803         .get_gpio_mux   = rk3288_pinctrl_get_gpio_mux,
 804 #endif
 805         .set_state_simple       = rk3288_pinctrl_set_state_simple,
 806         .request        = rk3288_pinctrl_request,
 807         .get_periph_id  = rk3288_pinctrl_get_periph_id,
 808 };
 809
 810 #ifndef CONFIG_SPL_BUILD
 811 static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
 812                                        struct rockchip_pin_bank *banks,
 813                                        int count)
 814 {
 815         struct rockchip_pin_bank *bank;
 816         uint reg, muxnum, banknum;
 817
 818         reg = 0;
 819         for (banknum = 0; banknum < count; banknum++) {
 820                 bank = &banks[banknum];
 821                 bank->reg = reg;
 822                 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
 823                 for (muxnum = 0; muxnum < 4; muxnum++) {
 824                         struct rockchip_iomux *mux = &bank->iomux[muxnum];
 825
 826                         if (!(mux->type & IOMUX_UNROUTED))
 827                                 mux->offset = reg;
 828                         if (mux->type & IOMUX_WIDTH_4BIT)
 829                                 reg += 2;
 830                         else
 831                                 reg += 1;
 832                 }
 833         }
 834
 835         return 0;
 836 }
 837 #endif
 838
 839 static int rk3288_pinctrl_probe(struct udevice *dev)
 840 {
 841         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 842         int ret = 0;
 843
 844         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 845         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 846         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 847 #ifndef CONFIG_SPL_BUILD
 848         ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
 849                                           ARRAY_SIZE(rk3288_pin_banks));
 850 #endif
 851
 852         return ret;
 853 }
 854
 855 static const struct udevice_id rk3288_pinctrl_ids[] = {
 856         { .compatible = "rockchip,rk3288-pinctrl" },
 857         { }
 858 };
 859
 860 U_BOOT_DRIVER(pinctrl_rk3288) = {
 861         .name           = "rockchip_rk3288_pinctrl",
 862         .id             = UCLASS_PINCTRL,
 863         .of_match       = rk3288_pinctrl_ids,
 864         .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
 865         .ops            = &rk3288_pinctrl_ops,
 866 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 867         .bind           = dm_scan_fdt_dev,
 868 #endif
 869         .probe          = rk3288_pinctrl_probe,
 870 };