drivers/pinctrl/rockchip/pinctrl_rk3288.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  * Copyright (c) 2015 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/periph.h>
  18 #include <asm/arch/pmu_rk3288.h>
  19 #include <dm/pinctrl.h>
  20 #include <dm/root.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct rk3288_pinctrl_priv {
  25         struct rk3288_grf *grf;
  26         struct rk3288_pmu *pmu;
  27         int num_banks;
  28 };
  29
  30 /**
  31  * Encode variants of iomux registers into a type variable
  32  */
  33 #define IOMUX_GPIO_ONLY         BIT(0)
  34 #define IOMUX_WIDTH_4BIT        BIT(1)
  35 #define IOMUX_SOURCE_PMU        BIT(2)
  36 #define IOMUX_UNROUTED          BIT(3)
  37
  38 /**
  39  * @type: iomux variant using IOMUX_* constants
  40  * @offset: if initialized to -1 it will be autocalculated, by specifying
  41  *          an initial offset value the relevant source offset can be reset
  42  *          to a new value for autocalculating the following iomux registers.
  43  */
  44 struct rockchip_iomux {
  45         u8 type;
  46         s16 offset;
  47 };
  48
  49 /**
  50  * @reg: register offset of the gpio bank
  51  * @nr_pins: number of pins in this bank
  52  * @bank_num: number of the bank, to account for holes
  53  * @name: name of the bank
  54  * @iomux: array describing the 4 iomux sources of the bank
  55  */
  56 struct rockchip_pin_bank {
  57         u16 reg;
  58         u8 nr_pins;
  59         u8 bank_num;
  60         char *name;
  61         struct rockchip_iomux iomux[4];
  62 };
  63
  64 #define PIN_BANK(id, pins, label)                       \
  65         {                                               \
  66                 .bank_num       = id,                   \
  67                 .nr_pins        = pins,                 \
  68                 .name           = label,                \
  69                 .iomux          = {                     \
  70                         { .offset = -1 },               \
  71                         { .offset = -1 },               \
  72                         { .offset = -1 },               \
  73                         { .offset = -1 },               \
  74                 },                                      \
  75         }
  76
  77 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  78         {                                                               \
  79                 .bank_num       = id,                                   \
  80                 .nr_pins        = pins,                                 \
  81                 .name           = label,                                \
  82                 .iomux          = {                                     \
  83                         { .type = iom0, .offset = -1 },                 \
  84                         { .type = iom1, .offset = -1 },                 \
  85                         { .type = iom2, .offset = -1 },                 \
  86                         { .type = iom3, .offset = -1 },                 \
  87                 },                                                      \
  88         }
  89
  90 #ifndef CONFIG_SPL_BUILD
  91 static struct rockchip_pin_bank rk3288_pin_banks[] = {
  92         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
  93                                              IOMUX_SOURCE_PMU,
  94                                              IOMUX_SOURCE_PMU,
  95                                              IOMUX_UNROUTED
  96                             ),
  97         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
  98                                              IOMUX_UNROUTED,
  99                                              IOMUX_UNROUTED,
 100                                              0
 101                             ),
 102         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
 103         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
 104         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
 105                                              IOMUX_WIDTH_4BIT,
 106                                              0,
 107                                              0
 108                             ),
 109         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
 110                                              0,
 111                                              0,
 112                                              IOMUX_UNROUTED
 113                             ),
 114         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
 115         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
 116                                              0,
 117                                              IOMUX_WIDTH_4BIT,
 118                                              IOMUX_UNROUTED
 119                             ),
 120         PIN_BANK(8, 16, "gpio8"),
 121 };
 122 #endif
 123
 124 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
 125 {
 126         switch (pwm_id) {
 127         case PERIPH_ID_PWM0:
 128                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
 129                              GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
 130                 break;
 131         case PERIPH_ID_PWM1:
 132                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
 133                              GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
 134                 break;
 135         case PERIPH_ID_PWM2:
 136                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
 137                              GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
 138                 break;
 139         case PERIPH_ID_PWM3:
 140                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
 141                              GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
 142                 break;
 143         default:
 144                 debug("pwm id = %d iomux error!\n", pwm_id);
 145                 break;
 146         }
 147 }
 148
 149 static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
 150                                       struct rk3288_pmu *pmu, int i2c_id)
 151 {
 152         switch (i2c_id) {
 153         case PERIPH_ID_I2C0:
 154                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
 155                                 GPIO0_B7_MASK << GPIO0_B7_SHIFT,
 156                                 GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
 157                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
 158                                 GPIO0_C0_MASK << GPIO0_C0_SHIFT,
 159                                 GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
 160                 break;
 161         case PERIPH_ID_I2C1:
 162                 rk_clrsetreg(&grf->gpio8a_iomux,
 163                              GPIO8A4_MASK << GPIO8A4_SHIFT |
 164                              GPIO8A5_MASK << GPIO8A5_SHIFT,
 165                              GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
 166                              GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
 167                 break;
 168         case PERIPH_ID_I2C2:
 169                 rk_clrsetreg(&grf->gpio6b_iomux,
 170                              GPIO6B1_MASK << GPIO6B1_SHIFT |
 171                              GPIO6B2_MASK << GPIO6B2_SHIFT,
 172                              GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
 173                              GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
 174                 break;
 175         case PERIPH_ID_I2C3:
 176                 rk_clrsetreg(&grf->gpio2c_iomux,
 177                              GPIO2C1_MASK << GPIO2C1_SHIFT |
 178                              GPIO2C0_MASK << GPIO2C0_SHIFT,
 179                              GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
 180                              GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
 181                 break;
 182         case PERIPH_ID_I2C4:
 183                 rk_clrsetreg(&grf->gpio7cl_iomux,
 184                              GPIO7C1_MASK << GPIO7C1_SHIFT |
 185                              GPIO7C2_MASK << GPIO7C2_SHIFT,
 186                              GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
 187                              GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
 188                 break;
 189         case PERIPH_ID_I2C5:
 190                 rk_clrsetreg(&grf->gpio7cl_iomux,
 191                              GPIO7C3_MASK << GPIO7C3_SHIFT,
 192                              GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
 193                 rk_clrsetreg(&grf->gpio7ch_iomux,
 194                              GPIO7C4_MASK << GPIO7C4_SHIFT,
 195                              GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
 196                 break;
 197         default:
 198                 debug("i2c id = %d iomux error!\n", i2c_id);
 199                 break;
 200         }
 201 }
 202
 203 static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
 204 {
 205         switch (lcd_id) {
 206         case PERIPH_ID_LCDC0:
 207                 rk_clrsetreg(&grf->gpio1d_iomux,
 208                              GPIO1D3_MASK << GPIO1D0_SHIFT |
 209                              GPIO1D2_MASK << GPIO1D2_SHIFT |
 210                              GPIO1D1_MASK << GPIO1D1_SHIFT |
 211                              GPIO1D0_MASK << GPIO1D0_SHIFT,
 212                              GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
 213                              GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
 214                              GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
 215                              GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
 216                 break;
 217         default:
 218                 debug("lcdc id = %d iomux error!\n", lcd_id);
 219                 break;
 220         }
 221 }
 222
 223 static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
 224                                      enum periph_id spi_id, int cs)
 225 {
 226         switch (spi_id) {
 227         case PERIPH_ID_SPI0:
 228                 switch (cs) {
 229                 case 0:
 230                         rk_clrsetreg(&grf->gpio5b_iomux,
 231                                      GPIO5B5_MASK << GPIO5B5_SHIFT,
 232                                      GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
 233                         break;
 234                 case 1:
 235                         rk_clrsetreg(&grf->gpio5c_iomux,
 236                                      GPIO5C0_MASK << GPIO5C0_SHIFT,
 237                                      GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
 238                         break;
 239                 default:
 240                         goto err;
 241                 }
 242                 rk_clrsetreg(&grf->gpio5b_iomux,
 243                              GPIO5B7_MASK << GPIO5B7_SHIFT |
 244                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 245                              GPIO5B4_MASK << GPIO5B4_SHIFT,
 246                              GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
 247                              GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
 248                              GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
 249                 break;
 250         case PERIPH_ID_SPI1:
 251                 if (cs != 0)
 252                         goto err;
 253                 rk_clrsetreg(&grf->gpio7b_iomux,
 254                              GPIO7B6_MASK << GPIO7B6_SHIFT |
 255                              GPIO7B7_MASK << GPIO7B7_SHIFT |
 256                              GPIO7B5_MASK << GPIO7B5_SHIFT |
 257                              GPIO7B4_MASK << GPIO7B4_SHIFT,
 258                              GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
 259                              GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
 260                              GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
 261                              GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
 262                 break;
 263         case PERIPH_ID_SPI2:
 264                 switch (cs) {
 265                 case 0:
 266                         rk_clrsetreg(&grf->gpio8a_iomux,
 267                                      GPIO8A7_MASK << GPIO8A7_SHIFT,
 268                                      GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
 269                         break;
 270                 case 1:
 271                         rk_clrsetreg(&grf->gpio8a_iomux,
 272                                      GPIO8A3_MASK << GPIO8A3_SHIFT,
 273                                      GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
 274                         break;
 275                 default:
 276                         goto err;
 277                 }
 278                 rk_clrsetreg(&grf->gpio8b_iomux,
 279                              GPIO8B1_MASK << GPIO8B1_SHIFT |
 280                              GPIO8B0_MASK << GPIO8B0_SHIFT,
 281                              GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
 282                              GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
 283                 rk_clrsetreg(&grf->gpio8a_iomux,
 284                              GPIO8A6_MASK << GPIO8A6_SHIFT,
 285                              GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
 286                 break;
 287         default:
 288                 goto err;
 289         }
 290
 291         return 0;
 292 err:
 293         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 294         return -ENOENT;
 295 }
 296
 297 static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
 298 {
 299         switch (uart_id) {
 300         case PERIPH_ID_UART_BT:
 301                 rk_clrsetreg(&grf->gpio4c_iomux,
 302                              GPIO4C3_MASK << GPIO4C3_SHIFT |
 303                              GPIO4C2_MASK << GPIO4C2_SHIFT |
 304                              GPIO4C1_MASK << GPIO4C1_SHIFT |
 305                              GPIO4C0_MASK << GPIO4C0_SHIFT,
 306                              GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
 307                              GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
 308                              GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
 309                              GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
 310                 break;
 311         case PERIPH_ID_UART_BB:
 312                 rk_clrsetreg(&grf->gpio5b_iomux,
 313                              GPIO5B3_MASK << GPIO5B3_SHIFT |
 314                              GPIO5B2_MASK << GPIO5B2_SHIFT |
 315                              GPIO5B1_MASK << GPIO5B1_SHIFT |
 316                              GPIO5B0_MASK << GPIO5B0_SHIFT,
 317                              GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
 318                              GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
 319                              GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
 320                              GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
 321                 break;
 322         case PERIPH_ID_UART_DBG:
 323                 rk_clrsetreg(&grf->gpio7ch_iomux,
 324                              GPIO7C7_MASK << GPIO7C7_SHIFT |
 325                              GPIO7C6_MASK << GPIO7C6_SHIFT,
 326                              GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 327                              GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 328                 break;
 329         case PERIPH_ID_UART_GPS:
 330                 rk_clrsetreg(&grf->gpio7b_iomux,
 331                              GPIO7B2_MASK << GPIO7B2_SHIFT |
 332                              GPIO7B1_MASK << GPIO7B1_SHIFT |
 333                              GPIO7B0_MASK << GPIO7B0_SHIFT,
 334                              GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
 335                              GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
 336                              GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
 337                 rk_clrsetreg(&grf->gpio7a_iomux,
 338                              GPIO7A7_MASK << GPIO7A7_SHIFT,
 339                              GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
 340                 break;
 341         case PERIPH_ID_UART_EXP:
 342                 rk_clrsetreg(&grf->gpio5b_iomux,
 343                              GPIO5B5_MASK << GPIO5B5_SHIFT |
 344                              GPIO5B4_MASK << GPIO5B4_SHIFT |
 345                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 346                              GPIO5B7_MASK << GPIO5B7_SHIFT,
 347                              GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
 348                              GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
 349                              GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
 350                              GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
 351                 break;
 352         default:
 353                 debug("uart id = %d iomux error!\n", uart_id);
 354                 break;
 355         }
 356 }
 357
 358 static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
 359 {
 360         switch (mmc_id) {
 361         case PERIPH_ID_EMMC:
 362                 rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
 363                              GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
 364                              GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
 365                              GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
 366                              GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
 367                              GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
 368                              GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
 369                              GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
 370                              GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
 371                 rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
 372                              GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
 373                 rk_clrsetreg(&grf->gpio3c_iomux,
 374                              GPIO3C0_MASK << GPIO3C0_SHIFT,
 375                              GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
 376                 break;
 377         case PERIPH_ID_SDCARD:
 378                 rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
 379                              GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
 380                              GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
 381                              GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
 382                              GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
 383                              GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
 384                              GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
 385                              GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
 386
 387                 /* use sdmmc0 io, disable JTAG function */
 388                 rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
 389                 break;
 390         default:
 391                 debug("mmc id = %d iomux error!\n", mmc_id);
 392                 break;
 393         }
 394 }
 395
 396 static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
 397 {
 398         switch (hdmi_id) {
 399         case PERIPH_ID_HDMI:
 400                 rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
 401                              GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
 402                 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
 403                              GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
 404                 break;
 405         default:
 406                 debug("hdmi id = %d iomux error!\n", hdmi_id);
 407                 break;
 408         }
 409 }
 410
 411 static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
 412 {
 413         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 414
 415         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 416         switch (func) {
 417         case PERIPH_ID_PWM0:
 418         case PERIPH_ID_PWM1:
 419         case PERIPH_ID_PWM2:
 420         case PERIPH_ID_PWM3:
 421         case PERIPH_ID_PWM4:
 422                 pinctrl_rk3288_pwm_config(priv->grf, func);
 423                 break;
 424         case PERIPH_ID_I2C0:
 425         case PERIPH_ID_I2C1:
 426         case PERIPH_ID_I2C2:
 427         case PERIPH_ID_I2C3:
 428         case PERIPH_ID_I2C4:
 429         case PERIPH_ID_I2C5:
 430                 pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
 431                 break;
 432         case PERIPH_ID_SPI0:
 433         case PERIPH_ID_SPI1:
 434         case PERIPH_ID_SPI2:
 435                 pinctrl_rk3288_spi_config(priv->grf, func, flags);
 436                 break;
 437         case PERIPH_ID_UART0:
 438         case PERIPH_ID_UART1:
 439         case PERIPH_ID_UART2:
 440         case PERIPH_ID_UART3:
 441         case PERIPH_ID_UART4:
 442                 pinctrl_rk3288_uart_config(priv->grf, func);
 443                 break;
 444         case PERIPH_ID_LCDC0:
 445         case PERIPH_ID_LCDC1:
 446                 pinctrl_rk3288_lcdc_config(priv->grf, func);
 447                 break;
 448         case PERIPH_ID_SDMMC0:
 449         case PERIPH_ID_SDMMC1:
 450                 pinctrl_rk3288_sdmmc_config(priv->grf, func);
 451                 break;
 452         case PERIPH_ID_HDMI:
 453                 pinctrl_rk3288_hdmi_config(priv->grf, func);
 454                 break;
 455         default:
 456                 return -EINVAL;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 463                                         struct udevice *periph)
 464 {
 465         u32 cell[3];
 466         int ret;
 467
 468         ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
 469                                    "interrupts", cell, ARRAY_SIZE(cell));
 470         if (ret < 0)
 471                 return -EINVAL;
 472
 473         switch (cell[1]) {
 474         case 44:
 475                 return PERIPH_ID_SPI0;
 476         case 45:
 477                 return PERIPH_ID_SPI1;
 478         case 46:
 479                 return PERIPH_ID_SPI2;
 480         case 60:
 481                 return PERIPH_ID_I2C0;
 482         case 62: /* Note strange order */
 483                 return PERIPH_ID_I2C1;
 484         case 61:
 485                 return PERIPH_ID_I2C2;
 486         case 63:
 487                 return PERIPH_ID_I2C3;
 488         case 64:
 489                 return PERIPH_ID_I2C4;
 490         case 65:
 491                 return PERIPH_ID_I2C5;
 492         }
 493
 494         return -ENOENT;
 495 }
 496
 497 static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
 498                                            struct udevice *periph)
 499 {
 500         int func;
 501
 502         func = rk3288_pinctrl_get_periph_id(dev, periph);
 503         if (func < 0)
 504                 return func;
 505         return rk3288_pinctrl_request(dev, func, 0);
 506 }
 507
 508 #ifndef CONFIG_SPL_BUILD
 509 static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 510                                    int muxval, int flags)
 511 {
 512         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 513         struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
 514         uint shift, muxnum, ind = index;
 515         u32 *addr;
 516
 517         debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
 518         for (muxnum = 0; muxnum < 4; muxnum++) {
 519                 struct rockchip_iomux *mux = &bank->iomux[muxnum];
 520                 uint mask;
 521
 522                 if (ind >= 8) {
 523                         ind -= 8;
 524                         continue;
 525                 }
 526
 527                 if (mux->type & IOMUX_SOURCE_PMU)
 528                         addr = priv->pmu->gpio0_iomux;
 529                 else
 530                         addr = (u32 *)priv->grf - 4;
 531                 addr += mux->offset;
 532                 shift = ind & 7;
 533                 if (mux->type & IOMUX_WIDTH_4BIT) {
 534                         mask = 0xf;
 535                         shift *= 4;
 536                         if (shift >= 16) {
 537                                 shift -= 16;
 538                                 addr++;
 539                         }
 540                 } else {
 541                         mask = 3;
 542                         shift *= 2;
 543                 }
 544
 545                 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
 546                       mask, shift);
 547                 rk_clrsetreg(addr, mask << shift, muxval << shift);
 548                 break;
 549         }
 550         if (flags) {
 551                 uint val = 0;
 552
 553                 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
 554                         val = 1;
 555                 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 556                         val = 2;
 557                 shift = (index & 7) * 2;
 558                 ind = index >> 3;
 559                 if (banknum == 0)
 560                         addr = &priv->pmu->gpio0pull[ind];
 561                 else
 562                         addr = &priv->grf->gpio1_p[banknum - 1][ind];
 563                 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 564                       shift);
 565                 rk_clrsetreg(addr, 3 << shift, val << shift);
 566         }
 567
 568         return 0;
 569 }
 570
 571 static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 572 {
 573         const void *blob = gd->fdt_blob;
 574         int pcfg_node, ret, flags, count, i;
 575         u32 cell[40], *ptr;
 576
 577         debug("%s: %s %s\n", __func__, dev->name, config->name);
 578         ret = fdtdec_get_int_array_count(blob, config->of_offset,
 579                                          "rockchip,pins", cell,
 580                                          ARRAY_SIZE(cell));
 581         if (ret < 0) {
 582                 debug("%s: bad array %d\n", __func__, ret);
 583                 return -EINVAL;
 584         }
 585         count = ret;
 586         for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
 587                 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
 588                 if (pcfg_node < 0)
 589                         return -EINVAL;
 590                 flags = pinctrl_decode_pin_config(blob, pcfg_node);
 591                 if (flags < 0)
 592                         return flags;
 593
 594                 ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
 595                                               flags);
 596                 if (ret)
 597                         return ret;
 598         }
 599
 600         return 0;
 601 }
 602 #endif
 603
 604 static struct pinctrl_ops rk3288_pinctrl_ops = {
 605 #ifndef CONFIG_SPL_BUILD
 606         .set_state      = rk3288_pinctrl_set_state,
 607 #endif
 608         .set_state_simple       = rk3288_pinctrl_set_state_simple,
 609         .request        = rk3288_pinctrl_request,
 610         .get_periph_id  = rk3288_pinctrl_get_periph_id,
 611 };
 612
 613 static int rk3288_pinctrl_bind(struct udevice *dev)
 614 {
 615         /* scan child GPIO banks */
 616         return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
 617 }
 618
 619 #ifndef CONFIG_SPL_BUILD
 620 static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
 621                                        struct rockchip_pin_bank *banks,
 622                                        int count)
 623 {
 624         struct rockchip_pin_bank *bank;
 625         uint reg, muxnum, banknum;
 626
 627         reg = 0;
 628         for (banknum = 0; banknum < count; banknum++) {
 629                 bank = &banks[banknum];
 630                 bank->reg = reg;
 631                 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
 632                 for (muxnum = 0; muxnum < 4; muxnum++) {
 633                         struct rockchip_iomux *mux = &bank->iomux[muxnum];
 634
 635                         if (!(mux->type & IOMUX_UNROUTED))
 636                                 mux->offset = reg;
 637                         if (mux->type & IOMUX_WIDTH_4BIT)
 638                                 reg += 2;
 639                         else
 640                                 reg += 1;
 641                 }
 642         }
 643
 644         return 0;
 645 }
 646 #endif
 647
 648 static int rk3288_pinctrl_probe(struct udevice *dev)
 649 {
 650         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 651         int ret = 0;
 652
 653         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 654         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 655         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 656 #ifndef CONFIG_SPL_BUILD
 657         ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
 658                                           ARRAY_SIZE(rk3288_pin_banks));
 659 #endif
 660
 661         return ret;
 662 }
 663
 664 static const struct udevice_id rk3288_pinctrl_ids[] = {
 665         { .compatible = "rockchip,rk3288-pinctrl" },
 666         { }
 667 };
 668
 669 U_BOOT_DRIVER(pinctrl_rk3288) = {
 670         .name           = "pinctrl_rk3288",
 671         .id             = UCLASS_PINCTRL,
 672         .of_match       = rk3288_pinctrl_ids,
 673         .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
 674         .ops            = &rk3288_pinctrl_ops,
 675         .bind           = rk3288_pinctrl_bind,
 676         .probe          = rk3288_pinctrl_probe,
 677 };