1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
9 #include <dm/pinctrl.h>
12 #include <linux/bitops.h>
14 #include "pinctrl-rockchip.h"
16 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
80 static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
82 struct rockchip_pinctrl_priv *priv = bank->priv;
83 int iomux_num = (pin / 8);
84 struct regmap *regmap;
85 int reg, ret, mask, mux_type;
89 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
90 ? priv->regmap_pmu : priv->regmap_base;
92 /* get basic quadrupel of mux registers and the correct reg inside */
93 mux_type = bank->iomux[iomux_num].type;
94 reg = bank->iomux[iomux_num].offset;
95 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
97 if (bank->recalced_mask & BIT(pin))
98 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
100 data = (mask << (bit + 16));
101 data |= (mux & mask) << bit;
102 ret = regmap_write(regmap, reg, data);
107 #define RV1108_PULL_PMU_OFFSET 0x10
108 #define RV1108_PULL_OFFSET 0x110
110 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
111 int pin_num, struct regmap **regmap,
114 struct rockchip_pinctrl_priv *priv = bank->priv;
116 /* The first 24 pins of the first bank are located in PMU */
117 if (bank->bank_num == 0) {
118 *regmap = priv->regmap_pmu;
119 *reg = RV1108_PULL_PMU_OFFSET;
121 *reg = RV1108_PULL_OFFSET;
122 *regmap = priv->regmap_base;
123 /* correct the offset, as we're starting with the 2nd bank */
125 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
128 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
129 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
130 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
133 static int rv1108_set_pull(struct rockchip_pin_bank *bank,
134 int pin_num, int pull)
136 struct regmap *regmap;
141 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
144 rv1108_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
145 type = bank->pull_type[pin_num / 8];
146 ret = rockchip_translate_pull_value(type, pull);
148 debug("unsupported pull setting %d\n", pull);
152 /* enable the write to the equivalent lower bits */
153 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
155 data |= (ret << bit);
156 ret = regmap_write(regmap, reg, data);
161 #define RV1108_DRV_PMU_OFFSET 0x20
162 #define RV1108_DRV_GRF_OFFSET 0x210
164 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
165 int pin_num, struct regmap **regmap,
168 struct rockchip_pinctrl_priv *priv = bank->priv;
170 /* The first 24 pins of the first bank are located in PMU */
171 if (bank->bank_num == 0) {
172 *regmap = priv->regmap_pmu;
173 *reg = RV1108_DRV_PMU_OFFSET;
175 *regmap = priv->regmap_base;
176 *reg = RV1108_DRV_GRF_OFFSET;
178 /* correct the offset, as we're starting with the 2nd bank */
180 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
183 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
184 *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
185 *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
188 static int rv1108_set_drive(struct rockchip_pin_bank *bank,
189 int pin_num, int strength)
191 struct regmap *regmap;
195 int type = bank->drv[pin_num / 8].drv_type;
197 rv1108_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
198 ret = rockchip_translate_drive_value(type, strength);
200 debug("unsupported driver strength %d\n", strength);
204 /* enable the write to the equivalent lower bits */
205 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
207 data |= (ret << bit);
208 ret = regmap_write(regmap, reg, data);
212 #define RV1108_SCHMITT_PMU_OFFSET 0x30
213 #define RV1108_SCHMITT_GRF_OFFSET 0x388
214 #define RV1108_SCHMITT_BANK_STRIDE 8
215 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
216 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
218 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
220 struct regmap **regmap,
223 struct rockchip_pinctrl_priv *priv = bank->priv;
226 if (bank->bank_num == 0) {
227 *regmap = priv->regmap_pmu;
228 *reg = RV1108_SCHMITT_PMU_OFFSET;
229 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
231 *regmap = priv->regmap_base;
232 *reg = RV1108_SCHMITT_GRF_OFFSET;
233 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
234 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
236 *reg += ((pin_num / pins_per_reg) * 4);
237 *bit = pin_num % pins_per_reg;
242 static int rv1108_set_schmitt(struct rockchip_pin_bank *bank,
243 int pin_num, int enable)
245 struct regmap *regmap;
250 rv1108_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
251 /* enable the write to the equivalent lower bits */
252 data = BIT(bit + 16) | (enable << bit);
254 return regmap_write(regmap, reg, data);
257 static struct rockchip_pin_bank rv1108_pin_banks[] = {
258 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
262 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
263 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
264 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
267 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
268 .pin_banks = rv1108_pin_banks,
269 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
270 .grf_mux_offset = 0x10,
271 .pmu_mux_offset = 0x0,
272 .iomux_recalced = rv1108_mux_recalced_data,
273 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
274 .set_mux = rv1108_set_mux,
275 .set_pull = rv1108_set_pull,
276 .set_drive = rv1108_set_drive,
277 .set_schmitt = rv1108_set_schmitt,
280 static const struct udevice_id rv1108_pinctrl_ids[] = {
282 .compatible = "rockchip,rv1108-pinctrl",
283 .data = (ulong)&rv1108_pin_ctrl
288 U_BOOT_DRIVER(pinctrl_rv1108) = {
289 .name = "pinctrl_rv1108",
290 .id = UCLASS_PINCTRL,
291 .of_match = rv1108_pinctrl_ids,
292 .priv_auto = sizeof(struct rockchip_pinctrl_priv),
293 .ops = &rockchip_pinctrl_ops,
294 #if CONFIG_IS_ENABLED(OF_REAL)
295 .bind = dm_scan_fdt_dev,
297 .probe = rockchip_pinctrl_probe,