1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
6 #ifndef __DRIVERS_PINCTRL_ROCKCHIP_H
7 #define __DRIVERS_PINCTRL_ROCKCHIP_H
9 #include <linux/types.h>
11 enum rockchip_pinctrl_type {
22 * Encode variants of iomux registers into a type variable
24 #define IOMUX_GPIO_ONLY BIT(0)
25 #define IOMUX_WIDTH_4BIT BIT(1)
26 #define IOMUX_SOURCE_PMU BIT(2)
27 #define IOMUX_UNROUTED BIT(3)
28 #define IOMUX_WIDTH_3BIT BIT(4)
29 #define IOMUX_WRITABLE_32BIT BIT(5)
32 * Defined some common pins constants
34 #define ROCKCHIP_PULL_BITS_PER_PIN 2
35 #define ROCKCHIP_PULL_PINS_PER_REG 8
36 #define ROCKCHIP_PULL_BANK_STRIDE 16
37 #define ROCKCHIP_DRV_BITS_PER_PIN 2
38 #define ROCKCHIP_DRV_PINS_PER_REG 8
39 #define ROCKCHIP_DRV_BANK_STRIDE 16
40 #define ROCKCHIP_DRV_3BITS_PER_PIN 3
43 * @type: iomux variant using IOMUX_* constants
44 * @offset: if initialized to -1 it will be autocalculated, by specifying
45 * an initial offset value the relevant source offset can be reset
46 * to a new value for autocalculating the following iomux registers.
48 struct rockchip_iomux {
53 #define DRV_TYPE_IO_MASK GENMASK(31, 16)
54 #define DRV_TYPE_WRITABLE_32BIT BIT(31)
57 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
59 enum rockchip_pin_drv_type {
60 DRV_TYPE_IO_DEFAULT = 0,
61 DRV_TYPE_IO_1V8_OR_3V0,
63 DRV_TYPE_IO_1V8_3V0_AUTO,
68 #define PULL_TYPE_IO_MASK GENMASK(31, 16)
69 #define PULL_TYPE_WRITABLE_32BIT BIT(31)
72 * enum type index corresponding to rockchip_pull_list arrays index.
74 enum rockchip_pin_pull_type {
75 PULL_TYPE_IO_DEFAULT = 0,
76 PULL_TYPE_IO_1V8_ONLY,
81 * @drv_type: drive strength variant using rockchip_perpin_drv_type
82 * @offset: if initialized to -1 it will be autocalculated, by specifying
83 * an initial offset value the relevant source offset can be reset
84 * to a new value for autocalculating the following drive strength
85 * registers. if used chips own cal_drv func instead to calculate
86 * registers offset, the variant could be ignored.
89 enum rockchip_pin_drv_type drv_type;
94 * @priv: common pinctrl private basedata
95 * @pin_base: first pin number
96 * @nr_pins: number of pins in this bank
97 * @name: name of the bank
98 * @bank_num: number of the bank, to account for holes
99 * @iomux: array describing the 4 iomux sources of the bank
100 * @drv: array describing the 4 drive strength sources of the bank
101 * @pull_type: array describing the 4 pull type sources of the bank
102 * @recalced_mask: bits describing the mux recalced pins of per bank
103 * @route_mask: bits describing the routing pins of per bank
105 struct rockchip_pin_bank {
106 struct rockchip_pinctrl_priv *priv;
111 struct rockchip_iomux iomux[4];
112 struct rockchip_drv drv[4];
113 enum rockchip_pin_pull_type pull_type[4];
118 #define PIN_BANK(id, pins, label) \
131 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
137 { .type = iom0, .offset = -1 }, \
138 { .type = iom1, .offset = -1 }, \
139 { .type = iom2, .offset = -1 }, \
140 { .type = iom3, .offset = -1 }, \
144 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
156 { .drv_type = type0, .offset = -1 }, \
157 { .drv_type = type1, .offset = -1 }, \
158 { .drv_type = type2, .offset = -1 }, \
159 { .drv_type = type3, .offset = -1 }, \
163 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
164 drv2, drv3, pull0, pull1, \
177 { .drv_type = drv0, .offset = -1 }, \
178 { .drv_type = drv1, .offset = -1 }, \
179 { .drv_type = drv2, .offset = -1 }, \
180 { .drv_type = drv3, .offset = -1 }, \
182 .pull_type[0] = pull0, \
183 .pull_type[1] = pull1, \
184 .pull_type[2] = pull2, \
185 .pull_type[3] = pull3, \
188 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
189 iom2, iom3, drv0, drv1, drv2, \
190 drv3, offset0, offset1, \
197 { .type = iom0, .offset = -1 }, \
198 { .type = iom1, .offset = -1 }, \
199 { .type = iom2, .offset = -1 }, \
200 { .type = iom3, .offset = -1 }, \
203 { .drv_type = drv0, .offset = offset0 }, \
204 { .drv_type = drv1, .offset = offset1 }, \
205 { .drv_type = drv2, .offset = offset2 }, \
206 { .drv_type = drv3, .offset = offset3 }, \
210 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
211 iom2, iom3, drv0, drv1, drv2, \
212 drv3, pull0, pull1, pull2, \
219 { .type = iom0, .offset = -1 }, \
220 { .type = iom1, .offset = -1 }, \
221 { .type = iom2, .offset = -1 }, \
222 { .type = iom3, .offset = -1 }, \
225 { .drv_type = drv0, .offset = -1 }, \
226 { .drv_type = drv1, .offset = -1 }, \
227 { .drv_type = drv2, .offset = -1 }, \
228 { .drv_type = drv3, .offset = -1 }, \
230 .pull_type[0] = pull0, \
231 .pull_type[1] = pull1, \
232 .pull_type[2] = pull2, \
233 .pull_type[3] = pull3, \
236 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
237 label, iom0, iom1, iom2, \
238 iom3, drv0, drv1, drv2, \
239 drv3, offset0, offset1, \
240 offset2, offset3, pull0, \
241 pull1, pull2, pull3) \
247 { .type = iom0, .offset = -1 }, \
248 { .type = iom1, .offset = -1 }, \
249 { .type = iom2, .offset = -1 }, \
250 { .type = iom3, .offset = -1 }, \
253 { .drv_type = drv0, .offset = offset0 }, \
254 { .drv_type = drv1, .offset = offset1 }, \
255 { .drv_type = drv2, .offset = offset2 }, \
256 { .drv_type = drv3, .offset = offset3 }, \
258 .pull_type[0] = pull0, \
259 .pull_type[1] = pull1, \
260 .pull_type[2] = pull2, \
261 .pull_type[3] = pull3, \
265 * struct rockchip_mux_recalced_data: recalculate a pin iomux data.
268 * @reg: register offset.
269 * @bit: index at register.
272 struct rockchip_mux_recalced_data {
281 * struct rockchip_mux_route_data: route a pin iomux data.
282 * @bank_num: bank number.
283 * @pin: index at register or used to calc index.
284 * @func: the min pin.
285 * @route_offset: the max pin.
286 * @route_val: the register offset.
288 struct rockchip_mux_route_data {
298 struct rockchip_pin_ctrl {
299 struct rockchip_pin_bank *pin_banks;
303 enum rockchip_pinctrl_type type;
308 struct rockchip_mux_recalced_data *iomux_recalced;
310 struct rockchip_mux_route_data *iomux_routes;
313 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
314 int pin_num, struct regmap **regmap,
316 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
317 int pin_num, struct regmap **regmap,
319 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
320 int pin_num, struct regmap **regmap,
326 struct rockchip_pinctrl_priv {
327 struct rockchip_pin_ctrl *ctrl;
328 struct regmap *regmap_base;
329 struct regmap *regmap_pmu;
332 extern const struct pinctrl_ops rockchip_pinctrl_ops;
333 int rockchip_pinctrl_probe(struct udevice *dev);
335 #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */