drivers/pinctrl/rockchip/pinctrl-rockchip-core.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <log.h>
   9 #include <dm/pinctrl.h>
  10 #include <regmap.h>
  11 #include <syscon.h>
  12 #include <fdtdec.h>
  13 #include <linux/libfdt.h>
  14
  15 #include "pinctrl-rockchip.h"
  16
  17 #define MAX_ROCKCHIP_PINS_ENTRIES       30
  18 #define MAX_ROCKCHIP_GPIO_PER_BANK      32
  19 #define RK_FUNC_GPIO                    0
  20
  21 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
  22 {
  23         struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
  24         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  25
  26         if (bank >= ctrl->nr_banks) {
  27                 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
  28                 return -EINVAL;
  29         }
  30
  31         if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
  32                 debug("pin conf pin %d >= %d\n", pin,
  33                       MAX_ROCKCHIP_GPIO_PER_BANK);
  34                 return -EINVAL;
  35         }
  36
  37         return 0;
  38 }
  39
  40 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
  41                                int *reg, u8 *bit, int *mask)
  42 {
  43         struct rockchip_pinctrl_priv *priv = bank->priv;
  44         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  45         struct rockchip_mux_recalced_data *data;
  46         int i;
  47
  48         for (i = 0; i < ctrl->niomux_recalced; i++) {
  49                 data = &ctrl->iomux_recalced[i];
  50                 if (data->num == bank->bank_num &&
  51                     data->pin == pin)
  52                         break;
  53         }
  54
  55         if (i >= ctrl->niomux_recalced)
  56                 return;
  57
  58         *reg = data->reg;
  59         *mask = data->mask;
  60         *bit = data->bit;
  61 }
  62
  63 bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
  64                             int mux, u32 *reg, u32 *value)
  65 {
  66         struct rockchip_pinctrl_priv *priv = bank->priv;
  67         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  68         struct rockchip_mux_route_data *data;
  69         int i;
  70
  71         for (i = 0; i < ctrl->niomux_routes; i++) {
  72                 data = &ctrl->iomux_routes[i];
  73                 if (data->bank_num == bank->bank_num &&
  74                     data->pin == pin && data->func == mux)
  75                         break;
  76         }
  77
  78         if (i >= ctrl->niomux_routes)
  79                 return false;
  80
  81         *reg = data->route_offset;
  82         *value = data->route_val;
  83
  84         return true;
  85 }
  86
  87 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
  88 {
  89         int offset = 0;
  90
  91         if (mux_type & IOMUX_WIDTH_4BIT) {
  92                 if ((pin % 8) >= 4)
  93                         offset = 0x4;
  94                 *bit = (pin % 4) * 4;
  95                 *mask = 0xf;
  96         } else if (mux_type & IOMUX_WIDTH_3BIT) {
  97                 /*
  98                  * pin0 ~ pin4 are at first register, and
  99                  * pin5 ~ pin7 are at second register.
 100                  */
 101                 if ((pin % 8) >= 5)
 102                         offset = 0x4;
 103                 *bit = (pin % 8 % 5) * 3;
 104                 *mask = 0x7;
 105         } else {
 106                 *bit = (pin % 8) * 2;
 107                 *mask = 0x3;
 108         }
 109
 110         return offset;
 111 }
 112
 113 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 114 {
 115         struct rockchip_pinctrl_priv *priv = bank->priv;
 116         int iomux_num = (pin / 8);
 117         struct regmap *regmap;
 118         unsigned int val;
 119         int reg, ret, mask, mux_type;
 120         u8 bit;
 121
 122         if (iomux_num > 3)
 123                 return -EINVAL;
 124
 125         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 126                 debug("pin %d is unrouted\n", pin);
 127                 return -EINVAL;
 128         }
 129
 130         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 131                 return RK_FUNC_GPIO;
 132
 133         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 134                                 ? priv->regmap_pmu : priv->regmap_base;
 135
 136         /* get basic quadrupel of mux registers and the correct reg inside */
 137         mux_type = bank->iomux[iomux_num].type;
 138         reg = bank->iomux[iomux_num].offset;
 139         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
 140
 141         if (bank->recalced_mask & BIT(pin))
 142                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 143
 144         ret = regmap_read(regmap, reg, &val);
 145         if (ret)
 146                 return ret;
 147
 148         return ((val >> bit) & mask);
 149 }
 150
 151 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 152                                          int index)
 153 {       struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 154         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 155
 156         return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
 157 }
 158
 159 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
 160                                int pin, int mux)
 161 {
 162         int iomux_num = (pin / 8);
 163
 164         if (iomux_num > 3)
 165                 return -EINVAL;
 166
 167         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 168                 debug("pin %d is unrouted\n", pin);
 169                 return -EINVAL;
 170         }
 171
 172         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 173                 if (mux != IOMUX_GPIO_ONLY) {
 174                         debug("pin %d only supports a gpio mux\n", pin);
 175                         return -ENOTSUPP;
 176                 }
 177         }
 178
 179         return 0;
 180 }
 181
 182 /*
 183  * Set a new mux function for a pin.
 184  *
 185  * The register is divided into the upper and lower 16 bit. When changing
 186  * a value, the previous register value is not read and changed. Instead
 187  * it seems the changed bits are marked in the upper 16 bit, while the
 188  * changed value gets set in the same offset in the lower 16 bit.
 189  * All pin settings seem to be 2 bit wide in both the upper and lower
 190  * parts.
 191  * @bank: pin bank to change
 192  * @pin: pin to change
 193  * @mux: new mux function to set
 194  */
 195 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 196 {
 197         struct rockchip_pinctrl_priv *priv = bank->priv;
 198         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 199         int iomux_num = (pin / 8);
 200         int ret;
 201
 202         ret = rockchip_verify_mux(bank, pin, mux);
 203         if (ret < 0)
 204                 return ret;
 205
 206         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 207                 return 0;
 208
 209         debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
 210
 211         if (!ctrl->set_mux)
 212                 return -ENOTSUPP;
 213
 214         ret = ctrl->set_mux(bank, pin, mux);
 215
 216         return ret;
 217 }
 218
 219 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
 220         { 2, 4, 8, 12, -1, -1, -1, -1 },
 221         { 3, 6, 9, 12, -1, -1, -1, -1 },
 222         { 5, 10, 15, 20, -1, -1, -1, -1 },
 223         { 4, 6, 8, 10, 12, 14, 16, 18 },
 224         { 4, 7, 10, 13, 16, 19, 22, 26 }
 225 };
 226
 227 int rockchip_translate_drive_value(int type, int strength)
 228 {
 229         int i, ret;
 230
 231         ret = -EINVAL;
 232         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
 233                 if (rockchip_perpin_drv_list[type][i] == strength) {
 234                         ret = i;
 235                         break;
 236                 } else if (rockchip_perpin_drv_list[type][i] < 0) {
 237                         ret = rockchip_perpin_drv_list[type][i];
 238                         break;
 239                 }
 240         }
 241
 242         return ret;
 243 }
 244
 245 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 246                                      int pin_num, int strength)
 247 {
 248         struct rockchip_pinctrl_priv *priv = bank->priv;
 249         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 250
 251         debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
 252               pin_num, strength);
 253
 254         if (!ctrl->set_drive)
 255                 return -ENOTSUPP;
 256
 257         return ctrl->set_drive(bank, pin_num, strength);
 258 }
 259
 260 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
 261         {
 262                 PIN_CONFIG_BIAS_DISABLE,
 263                 PIN_CONFIG_BIAS_PULL_UP,
 264                 PIN_CONFIG_BIAS_PULL_DOWN,
 265                 PIN_CONFIG_BIAS_BUS_HOLD
 266         },
 267         {
 268                 PIN_CONFIG_BIAS_DISABLE,
 269                 PIN_CONFIG_BIAS_PULL_DOWN,
 270                 PIN_CONFIG_BIAS_DISABLE,
 271                 PIN_CONFIG_BIAS_PULL_UP
 272         },
 273 };
 274
 275 int rockchip_translate_pull_value(int type, int pull)
 276 {
 277         int i, ret;
 278
 279         ret = -EINVAL;
 280         for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
 281                 i++) {
 282                 if (rockchip_pull_list[type][i] == pull) {
 283                         ret = i;
 284                         break;
 285                 }
 286         }
 287
 288         return ret;
 289 }
 290
 291 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 292                              int pin_num, int pull)
 293 {
 294         struct rockchip_pinctrl_priv *priv = bank->priv;
 295         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 296
 297         debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
 298               pin_num, pull);
 299
 300         if (!ctrl->set_pull)
 301                 return -ENOTSUPP;
 302
 303         return ctrl->set_pull(bank, pin_num, pull);
 304 }
 305
 306 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
 307                                 int pin_num, int enable)
 308 {
 309         struct rockchip_pinctrl_priv *priv = bank->priv;
 310         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 311
 312         debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
 313               pin_num, enable);
 314
 315         if (!ctrl->set_schmitt)
 316                 return -ENOTSUPP;
 317
 318         return ctrl->set_schmitt(bank, pin_num, enable);
 319 }
 320
 321 /* set the pin config settings for a specified pin */
 322 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
 323                                 u32 pin, u32 param, u32 arg)
 324 {
 325         int rc;
 326
 327         switch (param) {
 328         case PIN_CONFIG_BIAS_DISABLE:
 329         case PIN_CONFIG_BIAS_PULL_UP:
 330         case PIN_CONFIG_BIAS_PULL_DOWN:
 331         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 332         case PIN_CONFIG_BIAS_BUS_HOLD:
 333                 rc = rockchip_set_pull(bank, pin, param);
 334                 if (rc)
 335                         return rc;
 336                 break;
 337
 338         case PIN_CONFIG_DRIVE_STRENGTH:
 339                 rc = rockchip_set_drive_perpin(bank, pin, arg);
 340                 if (rc < 0)
 341                         return rc;
 342                 break;
 343
 344         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 345                 rc = rockchip_set_schmitt(bank, pin, arg);
 346                 if (rc < 0)
 347                         return rc;
 348                 break;
 349
 350         default:
 351                 break;
 352         }
 353
 354         return 0;
 355 }
 356
 357 static const struct pinconf_param rockchip_conf_params[] = {
 358         { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
 359         { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
 360         { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
 361         { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
 362         { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
 363         { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
 364         { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
 365         { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
 366 };
 367
 368 static int rockchip_pinconf_prop_name_to_param(const char *property,
 369                                                u32 *default_value)
 370 {
 371         const struct pinconf_param *p, *end;
 372
 373         p = rockchip_conf_params;
 374         end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
 375
 376         /* See if this pctldev supports this parameter */
 377         for (; p < end; p++) {
 378                 if (!strcmp(property, p->property)) {
 379                         *default_value = p->default_value;
 380                         return p->param;
 381                 }
 382         }
 383
 384         *default_value = 0;
 385         return -EPERM;
 386 }
 387
 388 static int rockchip_pinctrl_set_state(struct udevice *dev,
 389                                       struct udevice *config)
 390 {
 391         struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 392         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 393         u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
 394         u32 bank, pin, mux, conf, arg, default_val;
 395         int ret, count, i;
 396         const char *prop_name;
 397         const void *value;
 398         int prop_len, param;
 399         const u32 *data;
 400         ofnode node;
 401 #ifdef CONFIG_OF_LIVE
 402         const struct device_node *np;
 403         struct property *pp;
 404 #else
 405         int property_offset, pcfg_node;
 406         const void *blob = gd->fdt_blob;
 407 #endif
 408         data = dev_read_prop(config, "rockchip,pins", &count);
 409         if (count < 0) {
 410                 debug("%s: bad array size %d\n", __func__, count);
 411                 return -EINVAL;
 412         }
 413
 414         count /= sizeof(u32);
 415         if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
 416                 debug("%s: unsupported pins array count %d\n",
 417                       __func__, count);
 418                 return -EINVAL;
 419         }
 420
 421         for (i = 0; i < count; i++)
 422                 cells[i] = fdt32_to_cpu(data[i]);
 423
 424         for (i = 0; i < (count >> 2); i++) {
 425                 bank = cells[4 * i + 0];
 426                 pin = cells[4 * i + 1];
 427                 mux = cells[4 * i + 2];
 428                 conf = cells[4 * i + 3];
 429
 430                 ret = rockchip_verify_config(dev, bank, pin);
 431                 if (ret)
 432                         return ret;
 433
 434                 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
 435                 if (ret)
 436                         return ret;
 437
 438                 node = ofnode_get_by_phandle(conf);
 439                 if (!ofnode_valid(node))
 440                         return -ENODEV;
 441 #ifdef CONFIG_OF_LIVE
 442                 np = ofnode_to_np(node);
 443                 for (pp = np->properties; pp; pp = pp->next) {
 444                         prop_name = pp->name;
 445                         prop_len = pp->length;
 446                         value = pp->value;
 447 #else
 448                 pcfg_node = ofnode_to_offset(node);
 449                 fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
 450                         value = fdt_getprop_by_offset(blob, property_offset,
 451                                                       &prop_name, &prop_len);
 452                         if (!value)
 453                                 return -ENOENT;
 454 #endif
 455                         param = rockchip_pinconf_prop_name_to_param(prop_name,
 456                                                                     &default_val);
 457                         if (param < 0)
 458                                 break;
 459
 460                         if (prop_len >= sizeof(fdt32_t))
 461                                 arg = fdt32_to_cpu(*(fdt32_t *)value);
 462                         else
 463                                 arg = default_val;
 464
 465                         ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
 466                                                    param, arg);
 467                         if (ret) {
 468                                 debug("%s: rockchip_pinconf_set fail: %d\n",
 469                                       __func__, ret);
 470                                 return ret;
 471                         }
 472                 }
 473         }
 474
 475         return 0;
 476 }
 477
 478 const struct pinctrl_ops rockchip_pinctrl_ops = {
 479         .set_state                      = rockchip_pinctrl_set_state,
 480         .get_gpio_mux                   = rockchip_pinctrl_get_gpio_mux,
 481 };
 482
 483 /* retrieve the soc specific data */
 484 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
 485 {
 486         struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 487         struct rockchip_pin_ctrl *ctrl =
 488                         (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
 489         struct rockchip_pin_bank *bank;
 490         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
 491
 492         grf_offs = ctrl->grf_mux_offset;
 493         pmu_offs = ctrl->pmu_mux_offset;
 494         drv_pmu_offs = ctrl->pmu_drv_offset;
 495         drv_grf_offs = ctrl->grf_drv_offset;
 496         bank = ctrl->pin_banks;
 497
 498         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
 499                 int bank_pins = 0;
 500
 501                 bank->priv = priv;
 502                 bank->pin_base = ctrl->nr_pins;
 503                 ctrl->nr_pins += bank->nr_pins;
 504
 505                 /* calculate iomux and drv offsets */
 506                 for (j = 0; j < 4; j++) {
 507                         struct rockchip_iomux *iom = &bank->iomux[j];
 508                         struct rockchip_drv *drv = &bank->drv[j];
 509                         int inc;
 510
 511                         if (bank_pins >= bank->nr_pins)
 512                                 break;
 513
 514                         /* preset iomux offset value, set new start value */
 515                         if (iom->offset >= 0) {
 516                                 if (iom->type & IOMUX_SOURCE_PMU)
 517                                         pmu_offs = iom->offset;
 518                                 else
 519                                         grf_offs = iom->offset;
 520                         } else { /* set current iomux offset */
 521                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
 522                                                         pmu_offs : grf_offs;
 523                         }
 524
 525                         /* preset drv offset value, set new start value */
 526                         if (drv->offset >= 0) {
 527                                 if (iom->type & IOMUX_SOURCE_PMU)
 528                                         drv_pmu_offs = drv->offset;
 529                                 else
 530                                         drv_grf_offs = drv->offset;
 531                         } else { /* set current drv offset */
 532                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
 533                                                 drv_pmu_offs : drv_grf_offs;
 534                         }
 535
 536                         debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
 537                               i, j, iom->offset, drv->offset);
 538
 539                         /*
 540                          * Increase offset according to iomux width.
 541                          * 4bit iomux'es are spread over two registers.
 542                          */
 543                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
 544                                             IOMUX_WIDTH_3BIT |
 545                                             IOMUX_8WIDTH_2BIT)) ? 8 : 4;
 546                         if (iom->type & IOMUX_SOURCE_PMU)
 547                                 pmu_offs += inc;
 548                         else
 549                                 grf_offs += inc;
 550
 551                         /*
 552                          * Increase offset according to drv width.
 553                          * 3bit drive-strenth'es are spread over two registers.
 554                          */
 555                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
 556                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
 557                                 inc = 8;
 558                         else
 559                                 inc = 4;
 560
 561                         if (iom->type & IOMUX_SOURCE_PMU)
 562                                 drv_pmu_offs += inc;
 563                         else
 564                                 drv_grf_offs += inc;
 565
 566                         bank_pins += 8;
 567                 }
 568
 569                 /* calculate the per-bank recalced_mask */
 570                 for (j = 0; j < ctrl->niomux_recalced; j++) {
 571                         int pin = 0;
 572
 573                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
 574                                 pin = ctrl->iomux_recalced[j].pin;
 575                                 bank->recalced_mask |= BIT(pin);
 576                         }
 577                 }
 578
 579                 /* calculate the per-bank route_mask */
 580                 for (j = 0; j < ctrl->niomux_routes; j++) {
 581                         int pin = 0;
 582
 583                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
 584                                 pin = ctrl->iomux_routes[j].pin;
 585                                 bank->route_mask |= BIT(pin);
 586                         }
 587                 }
 588         }
 589
 590         return ctrl;
 591 }
 592
 593 int rockchip_pinctrl_probe(struct udevice *dev)
 594 {
 595         struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 596         struct rockchip_pin_ctrl *ctrl;
 597         struct udevice *syscon;
 598         struct regmap *regmap;
 599         int ret = 0;
 600
 601         /* get rockchip grf syscon phandle */
 602         ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
 603                                            &syscon);
 604         if (ret) {
 605                 debug("unable to find rockchip,grf syscon device (%d)\n", ret);
 606                 return ret;
 607         }
 608
 609         /* get grf-reg base address */
 610         regmap = syscon_get_regmap(syscon);
 611         if (!regmap) {
 612                 debug("unable to find rockchip grf regmap\n");
 613                 return -ENODEV;
 614         }
 615         priv->regmap_base = regmap;
 616
 617         /* option: get pmu-reg base address */
 618         ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
 619                                            &syscon);
 620         if (!ret) {
 621                 /* get pmugrf-reg base address */
 622                 regmap = syscon_get_regmap(syscon);
 623                 if (!regmap) {
 624                         debug("unable to find rockchip pmu regmap\n");
 625                         return -ENODEV;
 626                 }
 627                 priv->regmap_pmu = regmap;
 628         }
 629
 630         ctrl = rockchip_pinctrl_get_soc_data(dev);
 631         if (!ctrl) {
 632                 debug("driver data not available\n");
 633                 return -EINVAL;
 634         }
 635
 636         priv->ctrl = ctrl;
 637         return 0;
 638 }