1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
9 #include <dm/pinctrl.h>
12 #include <linux/bitops.h>
14 #include "pinctrl-rockchip.h"
16 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
38 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
45 .route_val = BIT(16) | BIT(16 + 1),
52 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
59 .route_val = BIT(16 + 2) | BIT(2),
61 /* gmac-m1-optimized_rxd3 */
66 .route_val = BIT(16 + 10) | BIT(10),
73 .route_val = BIT(16 + 3),
80 .route_val = BIT(16 + 3) | BIT(3),
87 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
94 .route_val = BIT(16 + 6),
100 .route_offset = 0x50,
101 .route_val = BIT(16 + 6) | BIT(6),
107 .route_offset = 0x50,
108 .route_val = BIT(16 + 7) | BIT(7),
114 .route_offset = 0x50,
115 .route_val = BIT(16 + 8) | BIT(8),
121 .route_offset = 0x50,
122 .route_val = BIT(16 + 9) | BIT(9),
126 static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
128 struct rockchip_pinctrl_priv *priv = bank->priv;
129 int iomux_num = (pin / 8);
130 struct regmap *regmap;
131 int reg, ret, mask, mux_type;
133 u32 data, route_reg, route_val;
135 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
136 ? priv->regmap_pmu : priv->regmap_base;
138 /* get basic quadrupel of mux registers and the correct reg inside */
139 mux_type = bank->iomux[iomux_num].type;
140 reg = bank->iomux[iomux_num].offset;
141 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
143 if (bank->recalced_mask & BIT(pin))
144 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
146 if (bank->route_mask & BIT(pin)) {
147 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
149 ret = regmap_write(regmap, route_reg, route_val);
155 data = (mask << (bit + 16));
156 data |= (mux & mask) << bit;
157 ret = regmap_write(regmap, reg, data);
162 #define RK3328_PULL_OFFSET 0x100
164 static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
165 int pin_num, struct regmap **regmap,
168 struct rockchip_pinctrl_priv *priv = bank->priv;
170 *regmap = priv->regmap_base;
171 *reg = RK3328_PULL_OFFSET;
172 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
173 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
175 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
176 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
179 static int rk3328_set_pull(struct rockchip_pin_bank *bank,
180 int pin_num, int pull)
182 struct regmap *regmap;
187 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
190 rk3328_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
191 type = bank->pull_type[pin_num / 8];
192 ret = rockchip_translate_pull_value(type, pull);
194 debug("unsupported pull setting %d\n", pull);
198 /* enable the write to the equivalent lower bits */
199 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
200 data |= (ret << bit);
201 ret = regmap_write(regmap, reg, data);
206 #define RK3328_DRV_GRF_OFFSET 0x200
208 static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
209 int pin_num, struct regmap **regmap,
212 struct rockchip_pinctrl_priv *priv = bank->priv;
214 *regmap = priv->regmap_base;
215 *reg = RK3328_DRV_GRF_OFFSET;
216 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
217 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
219 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
220 *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
223 static int rk3328_set_drive(struct rockchip_pin_bank *bank,
224 int pin_num, int strength)
226 struct regmap *regmap;
230 int type = bank->drv[pin_num / 8].drv_type;
232 rk3328_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
233 ret = rockchip_translate_drive_value(type, strength);
235 debug("unsupported driver strength %d\n", strength);
239 /* enable the write to the equivalent lower bits */
240 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
241 data |= (ret << bit);
242 ret = regmap_write(regmap, reg, data);
247 #define RK3328_SCHMITT_BITS_PER_PIN 1
248 #define RK3328_SCHMITT_PINS_PER_REG 16
249 #define RK3328_SCHMITT_BANK_STRIDE 8
250 #define RK3328_SCHMITT_GRF_OFFSET 0x380
252 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
254 struct regmap **regmap,
257 struct rockchip_pinctrl_priv *priv = bank->priv;
259 *regmap = priv->regmap_base;
260 *reg = RK3328_SCHMITT_GRF_OFFSET;
262 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
263 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
264 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
269 static int rk3328_set_schmitt(struct rockchip_pin_bank *bank,
270 int pin_num, int enable)
272 struct regmap *regmap;
277 rk3328_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
278 /* enable the write to the equivalent lower bits */
279 data = BIT(bit + 16) | (enable << bit);
281 return regmap_write(regmap, reg, data);
284 static struct rockchip_pin_bank rk3328_pin_banks[] = {
285 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
286 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
287 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
291 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
298 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
299 .pin_banks = rk3328_pin_banks,
300 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
301 .grf_mux_offset = 0x0,
302 .iomux_recalced = rk3328_mux_recalced_data,
303 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
304 .iomux_routes = rk3328_mux_route_data,
305 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
306 .set_mux = rk3328_set_mux,
307 .set_pull = rk3328_set_pull,
308 .set_drive = rk3328_set_drive,
309 .set_schmitt = rk3328_set_schmitt,
312 static const struct udevice_id rk3328_pinctrl_ids[] = {
314 .compatible = "rockchip,rk3328-pinctrl",
315 .data = (ulong)&rk3328_pin_ctrl
320 U_BOOT_DRIVER(rockchip_rk3328_pinctrl) = {
321 .name = "rockchip_rk3328_pinctrl",
322 .id = UCLASS_PINCTRL,
323 .of_match = rk3328_pinctrl_ids,
324 .priv_auto = sizeof(struct rockchip_pinctrl_priv),
325 .ops = &rockchip_pinctrl_ops,
326 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
327 .bind = dm_scan_fdt_dev,
329 .probe = rockchip_pinctrl_probe,