drivers/pinctrl/rockchip/pinctrl-rk322x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <log.h>
   9 #include <dm/pinctrl.h>
  10 #include <regmap.h>
  11 #include <syscon.h>
  12 #include <linux/bitops.h>
  13
  14 #include "pinctrl-rockchip.h"
  15
  16 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
  17         {
  18                 /* pwm0-0 */
  19                 .bank_num = 0,
  20                 .pin = 26,
  21                 .func = 1,
  22                 .route_offset = 0x50,
  23                 .route_val = BIT(16),
  24         }, {
  25                 /* pwm0-1 */
  26                 .bank_num = 3,
  27                 .pin = 21,
  28                 .func = 1,
  29                 .route_offset = 0x50,
  30                 .route_val = BIT(16) | BIT(0),
  31         }, {
  32                 /* pwm1-0 */
  33                 .bank_num = 0,
  34                 .pin = 27,
  35                 .func = 1,
  36                 .route_offset = 0x50,
  37                 .route_val = BIT(16 + 1),
  38         }, {
  39                 /* pwm1-1 */
  40                 .bank_num = 0,
  41                 .pin = 30,
  42                 .func = 2,
  43                 .route_offset = 0x50,
  44                 .route_val = BIT(16 + 1) | BIT(1),
  45         }, {
  46                 /* pwm2-0 */
  47                 .bank_num = 0,
  48                 .pin = 28,
  49                 .func = 1,
  50                 .route_offset = 0x50,
  51                 .route_val = BIT(16 + 2),
  52         }, {
  53                 /* pwm2-1 */
  54                 .bank_num = 1,
  55                 .pin = 12,
  56                 .func = 2,
  57                 .route_offset = 0x50,
  58                 .route_val = BIT(16 + 2) | BIT(2),
  59         }, {
  60                 /* pwm3-0 */
  61                 .bank_num = 3,
  62                 .pin = 26,
  63                 .func = 1,
  64                 .route_offset = 0x50,
  65                 .route_val = BIT(16 + 3),
  66         }, {
  67                 /* pwm3-1 */
  68                 .bank_num = 1,
  69                 .pin = 11,
  70                 .func = 2,
  71                 .route_offset = 0x50,
  72                 .route_val = BIT(16 + 3) | BIT(3),
  73         }, {
  74                 /* sdio-0_d0 */
  75                 .bank_num = 1,
  76                 .pin = 1,
  77                 .func = 1,
  78                 .route_offset = 0x50,
  79                 .route_val = BIT(16 + 4),
  80         }, {
  81                 /* sdio-1_d0 */
  82                 .bank_num = 3,
  83                 .pin = 2,
  84                 .func = 1,
  85                 .route_offset = 0x50,
  86                 .route_val = BIT(16 + 4) | BIT(4),
  87         }, {
  88                 /* spi-0_rx */
  89                 .bank_num = 0,
  90                 .pin = 13,
  91                 .func = 2,
  92                 .route_offset = 0x50,
  93                 .route_val = BIT(16 + 5),
  94         }, {
  95                 /* spi-1_rx */
  96                 .bank_num = 2,
  97                 .pin = 0,
  98                 .func = 2,
  99                 .route_offset = 0x50,
 100                 .route_val = BIT(16 + 5) | BIT(5),
 101         }, {
 102                 /* emmc-0_cmd */
 103                 .bank_num = 1,
 104                 .pin = 22,
 105                 .func = 2,
 106                 .route_offset = 0x50,
 107                 .route_val = BIT(16 + 7),
 108         }, {
 109                 /* emmc-1_cmd */
 110                 .bank_num = 2,
 111                 .pin = 4,
 112                 .func = 2,
 113                 .route_offset = 0x50,
 114                 .route_val = BIT(16 + 7) | BIT(7),
 115         }, {
 116                 /* uart2-0_rx */
 117                 .bank_num = 1,
 118                 .pin = 19,
 119                 .func = 2,
 120                 .route_offset = 0x50,
 121                 .route_val = BIT(16 + 8),
 122         }, {
 123                 /* uart2-1_rx */
 124                 .bank_num = 1,
 125                 .pin = 10,
 126                 .func = 2,
 127                 .route_offset = 0x50,
 128                 .route_val = BIT(16 + 8) | BIT(8),
 129         }, {
 130                 /* uart1-0_rx */
 131                 .bank_num = 1,
 132                 .pin = 10,
 133                 .func = 1,
 134                 .route_offset = 0x50,
 135                 .route_val = BIT(16 + 11),
 136         }, {
 137                 /* uart1-1_rx */
 138                 .bank_num = 3,
 139                 .pin = 13,
 140                 .func = 1,
 141                 .route_offset = 0x50,
 142                 .route_val = BIT(16 + 11) | BIT(11),
 143         },
 144 };
 145
 146 static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 147 {
 148         struct rockchip_pinctrl_priv *priv = bank->priv;
 149         int iomux_num = (pin / 8);
 150         struct regmap *regmap;
 151         int reg, ret, mask, mux_type;
 152         u8 bit;
 153         u32 data, route_reg, route_val;
 154
 155         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 156                                 ? priv->regmap_pmu : priv->regmap_base;
 157
 158         /* get basic quadrupel of mux registers and the correct reg inside */
 159         mux_type = bank->iomux[iomux_num].type;
 160         reg = bank->iomux[iomux_num].offset;
 161         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
 162
 163         if (bank->route_mask & BIT(pin)) {
 164                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
 165                                            &route_val)) {
 166                         ret = regmap_write(regmap, route_reg, route_val);
 167                         if (ret)
 168                                 return ret;
 169                 }
 170         }
 171
 172         data = (mask << (bit + 16));
 173         data |= (mux & mask) << bit;
 174         ret = regmap_write(regmap, reg, data);
 175
 176         return ret;
 177 }
 178
 179 #define RK3228_PULL_OFFSET              0x100
 180
 181 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 182                                          int pin_num, struct regmap **regmap,
 183                                          int *reg, u8 *bit)
 184 {
 185         struct rockchip_pinctrl_priv *priv = bank->priv;
 186
 187         *regmap = priv->regmap_base;
 188         *reg = RK3228_PULL_OFFSET;
 189         *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
 190         *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
 191
 192         *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
 193         *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 194 }
 195
 196 static int rk3228_set_pull(struct rockchip_pin_bank *bank,
 197                            int pin_num, int pull)
 198 {
 199         struct regmap *regmap;
 200         int reg, ret;
 201         u8 bit, type;
 202         u32 data;
 203
 204         if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
 205                 return -ENOTSUPP;
 206
 207         rk3228_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 208         type = bank->pull_type[pin_num / 8];
 209         ret = rockchip_translate_pull_value(type, pull);
 210         if (ret < 0) {
 211                 debug("unsupported pull setting %d\n", pull);
 212                 return ret;
 213         }
 214
 215         /* enable the write to the equivalent lower bits */
 216         data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 217         data |= (ret << bit);
 218         ret = regmap_write(regmap, reg, data);
 219
 220         return ret;
 221 }
 222
 223 #define RK3228_DRV_GRF_OFFSET           0x200
 224
 225 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 226                                         int pin_num, struct regmap **regmap,
 227                                         int *reg, u8 *bit)
 228 {
 229         struct rockchip_pinctrl_priv *priv = bank->priv;
 230
 231         *regmap = priv->regmap_base;
 232         *reg = RK3228_DRV_GRF_OFFSET;
 233         *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
 234         *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
 235
 236         *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
 237         *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 238 }
 239
 240 static int rk3228_set_drive(struct rockchip_pin_bank *bank,
 241                             int pin_num, int strength)
 242 {
 243         struct regmap *regmap;
 244         int reg, ret;
 245         u32 data;
 246         u8 bit;
 247         int type = bank->drv[pin_num / 8].drv_type;
 248
 249         rk3228_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 250         ret = rockchip_translate_drive_value(type, strength);
 251         if (ret < 0) {
 252                 debug("unsupported driver strength %d\n", strength);
 253                 return ret;
 254         }
 255
 256         /* enable the write to the equivalent lower bits */
 257         data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 258         data |= (ret << bit);
 259         ret = regmap_write(regmap, reg, data);
 260         return ret;
 261 }
 262
 263 static struct rockchip_pin_bank rk3228_pin_banks[] = {
 264         PIN_BANK(0, 32, "gpio0"),
 265         PIN_BANK(1, 32, "gpio1"),
 266         PIN_BANK(2, 32, "gpio2"),
 267         PIN_BANK(3, 32, "gpio3"),
 268 };
 269
 270 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
 271         .pin_banks              = rk3228_pin_banks,
 272         .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
 273         .grf_mux_offset         = 0x0,
 274         .iomux_routes           = rk3228_mux_route_data,
 275         .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
 276         .set_mux                = rk3228_set_mux,
 277         .set_pull               = rk3228_set_pull,
 278         .set_drive              = rk3228_set_drive,
 279 };
 280
 281 static const struct udevice_id rk3228_pinctrl_ids[] = {
 282         {
 283                 .compatible = "rockchip,rk3228-pinctrl",
 284                 .data = (ulong)&rk3228_pin_ctrl
 285         },
 286         { }
 287 };
 288
 289 U_BOOT_DRIVER(pinctrl_rk3228) = {
 290         .name           = "rockchip_rk3228_pinctrl",
 291         .id             = UCLASS_PINCTRL,
 292         .of_match       = rk3228_pinctrl_ids,
 293         .priv_auto      = sizeof(struct rockchip_pinctrl_priv),
 294         .ops            = &rockchip_pinctrl_ops,
 295 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 296         .bind           = dm_scan_fdt_dev,
 297 #endif
 298         .probe          = rockchip_pinctrl_probe,
 299 };