drivers/pinctrl/rockchip/pinctrl-rk322x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <log.h>
   9 #include <dm/pinctrl.h>
  10 #include <regmap.h>
  11 #include <syscon.h>
  12
  13 #include "pinctrl-rockchip.h"
  14
  15 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
  16         {
  17                 /* pwm0-0 */
  18                 .bank_num = 0,
  19                 .pin = 26,
  20                 .func = 1,
  21                 .route_offset = 0x50,
  22                 .route_val = BIT(16),
  23         }, {
  24                 /* pwm0-1 */
  25                 .bank_num = 3,
  26                 .pin = 21,
  27                 .func = 1,
  28                 .route_offset = 0x50,
  29                 .route_val = BIT(16) | BIT(0),
  30         }, {
  31                 /* pwm1-0 */
  32                 .bank_num = 0,
  33                 .pin = 27,
  34                 .func = 1,
  35                 .route_offset = 0x50,
  36                 .route_val = BIT(16 + 1),
  37         }, {
  38                 /* pwm1-1 */
  39                 .bank_num = 0,
  40                 .pin = 30,
  41                 .func = 2,
  42                 .route_offset = 0x50,
  43                 .route_val = BIT(16 + 1) | BIT(1),
  44         }, {
  45                 /* pwm2-0 */
  46                 .bank_num = 0,
  47                 .pin = 28,
  48                 .func = 1,
  49                 .route_offset = 0x50,
  50                 .route_val = BIT(16 + 2),
  51         }, {
  52                 /* pwm2-1 */
  53                 .bank_num = 1,
  54                 .pin = 12,
  55                 .func = 2,
  56                 .route_offset = 0x50,
  57                 .route_val = BIT(16 + 2) | BIT(2),
  58         }, {
  59                 /* pwm3-0 */
  60                 .bank_num = 3,
  61                 .pin = 26,
  62                 .func = 1,
  63                 .route_offset = 0x50,
  64                 .route_val = BIT(16 + 3),
  65         }, {
  66                 /* pwm3-1 */
  67                 .bank_num = 1,
  68                 .pin = 11,
  69                 .func = 2,
  70                 .route_offset = 0x50,
  71                 .route_val = BIT(16 + 3) | BIT(3),
  72         }, {
  73                 /* sdio-0_d0 */
  74                 .bank_num = 1,
  75                 .pin = 1,
  76                 .func = 1,
  77                 .route_offset = 0x50,
  78                 .route_val = BIT(16 + 4),
  79         }, {
  80                 /* sdio-1_d0 */
  81                 .bank_num = 3,
  82                 .pin = 2,
  83                 .func = 1,
  84                 .route_offset = 0x50,
  85                 .route_val = BIT(16 + 4) | BIT(4),
  86         }, {
  87                 /* spi-0_rx */
  88                 .bank_num = 0,
  89                 .pin = 13,
  90                 .func = 2,
  91                 .route_offset = 0x50,
  92                 .route_val = BIT(16 + 5),
  93         }, {
  94                 /* spi-1_rx */
  95                 .bank_num = 2,
  96                 .pin = 0,
  97                 .func = 2,
  98                 .route_offset = 0x50,
  99                 .route_val = BIT(16 + 5) | BIT(5),
 100         }, {
 101                 /* emmc-0_cmd */
 102                 .bank_num = 1,
 103                 .pin = 22,
 104                 .func = 2,
 105                 .route_offset = 0x50,
 106                 .route_val = BIT(16 + 7),
 107         }, {
 108                 /* emmc-1_cmd */
 109                 .bank_num = 2,
 110                 .pin = 4,
 111                 .func = 2,
 112                 .route_offset = 0x50,
 113                 .route_val = BIT(16 + 7) | BIT(7),
 114         }, {
 115                 /* uart2-0_rx */
 116                 .bank_num = 1,
 117                 .pin = 19,
 118                 .func = 2,
 119                 .route_offset = 0x50,
 120                 .route_val = BIT(16 + 8),
 121         }, {
 122                 /* uart2-1_rx */
 123                 .bank_num = 1,
 124                 .pin = 10,
 125                 .func = 2,
 126                 .route_offset = 0x50,
 127                 .route_val = BIT(16 + 8) | BIT(8),
 128         }, {
 129                 /* uart1-0_rx */
 130                 .bank_num = 1,
 131                 .pin = 10,
 132                 .func = 1,
 133                 .route_offset = 0x50,
 134                 .route_val = BIT(16 + 11),
 135         }, {
 136                 /* uart1-1_rx */
 137                 .bank_num = 3,
 138                 .pin = 13,
 139                 .func = 1,
 140                 .route_offset = 0x50,
 141                 .route_val = BIT(16 + 11) | BIT(11),
 142         },
 143 };
 144
 145 static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 146 {
 147         struct rockchip_pinctrl_priv *priv = bank->priv;
 148         int iomux_num = (pin / 8);
 149         struct regmap *regmap;
 150         int reg, ret, mask, mux_type;
 151         u8 bit;
 152         u32 data, route_reg, route_val;
 153
 154         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 155                                 ? priv->regmap_pmu : priv->regmap_base;
 156
 157         /* get basic quadrupel of mux registers and the correct reg inside */
 158         mux_type = bank->iomux[iomux_num].type;
 159         reg = bank->iomux[iomux_num].offset;
 160         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
 161
 162         if (bank->route_mask & BIT(pin)) {
 163                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
 164                                            &route_val)) {
 165                         ret = regmap_write(regmap, route_reg, route_val);
 166                         if (ret)
 167                                 return ret;
 168                 }
 169         }
 170
 171         data = (mask << (bit + 16));
 172         data |= (mux & mask) << bit;
 173         ret = regmap_write(regmap, reg, data);
 174
 175         return ret;
 176 }
 177
 178 #define RK3228_PULL_OFFSET              0x100
 179
 180 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 181                                          int pin_num, struct regmap **regmap,
 182                                          int *reg, u8 *bit)
 183 {
 184         struct rockchip_pinctrl_priv *priv = bank->priv;
 185
 186         *regmap = priv->regmap_base;
 187         *reg = RK3228_PULL_OFFSET;
 188         *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
 189         *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
 190
 191         *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
 192         *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
 193 }
 194
 195 static int rk3228_set_pull(struct rockchip_pin_bank *bank,
 196                            int pin_num, int pull)
 197 {
 198         struct regmap *regmap;
 199         int reg, ret;
 200         u8 bit, type;
 201         u32 data;
 202
 203         if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
 204                 return -ENOTSUPP;
 205
 206         rk3228_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 207         type = bank->pull_type[pin_num / 8];
 208         ret = rockchip_translate_pull_value(type, pull);
 209         if (ret < 0) {
 210                 debug("unsupported pull setting %d\n", pull);
 211                 return ret;
 212         }
 213
 214         /* enable the write to the equivalent lower bits */
 215         data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 216         data |= (ret << bit);
 217         ret = regmap_write(regmap, reg, data);
 218
 219         return ret;
 220 }
 221
 222 #define RK3228_DRV_GRF_OFFSET           0x200
 223
 224 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 225                                         int pin_num, struct regmap **regmap,
 226                                         int *reg, u8 *bit)
 227 {
 228         struct rockchip_pinctrl_priv *priv = bank->priv;
 229
 230         *regmap = priv->regmap_base;
 231         *reg = RK3228_DRV_GRF_OFFSET;
 232         *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
 233         *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
 234
 235         *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
 236         *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 237 }
 238
 239 static int rk3228_set_drive(struct rockchip_pin_bank *bank,
 240                             int pin_num, int strength)
 241 {
 242         struct regmap *regmap;
 243         int reg, ret;
 244         u32 data;
 245         u8 bit;
 246         int type = bank->drv[pin_num / 8].drv_type;
 247
 248         rk3228_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 249         ret = rockchip_translate_drive_value(type, strength);
 250         if (ret < 0) {
 251                 debug("unsupported driver strength %d\n", strength);
 252                 return ret;
 253         }
 254
 255         /* enable the write to the equivalent lower bits */
 256         data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 257         data |= (ret << bit);
 258         ret = regmap_write(regmap, reg, data);
 259         return ret;
 260 }
 261
 262 static struct rockchip_pin_bank rk3228_pin_banks[] = {
 263         PIN_BANK(0, 32, "gpio0"),
 264         PIN_BANK(1, 32, "gpio1"),
 265         PIN_BANK(2, 32, "gpio2"),
 266         PIN_BANK(3, 32, "gpio3"),
 267 };
 268
 269 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
 270         .pin_banks              = rk3228_pin_banks,
 271         .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
 272         .grf_mux_offset         = 0x0,
 273         .iomux_routes           = rk3228_mux_route_data,
 274         .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
 275         .set_mux                = rk3228_set_mux,
 276         .set_pull               = rk3228_set_pull,
 277         .set_drive              = rk3228_set_drive,
 278 };
 279
 280 static const struct udevice_id rk3228_pinctrl_ids[] = {
 281         {
 282                 .compatible = "rockchip,rk3228-pinctrl",
 283                 .data = (ulong)&rk3228_pin_ctrl
 284         },
 285         { }
 286 };
 287
 288 U_BOOT_DRIVER(pinctrl_rk3228) = {
 289         .name           = "rockchip_rk3228_pinctrl",
 290         .id             = UCLASS_PINCTRL,
 291         .of_match       = rk3228_pinctrl_ids,
 292         .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
 293         .ops            = &rockchip_pinctrl_ops,
 294 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 295         .bind           = dm_scan_fdt_dev,
 296 #endif
 297         .probe          = rockchip_pinctrl_probe,
 298 };