drivers/pinctrl/rockchip/pinctrl-rk3128.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/pinctrl.h>
   9 #include <regmap.h>
  10 #include <syscon.h>
  11 #include <linux/bitops.h>
  12
  13 #include "pinctrl-rockchip.h"
  14
  15 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
  16         {
  17                 .num = 2,
  18                 .pin = 20,
  19                 .reg = 0xe8,
  20                 .bit = 0,
  21                 .mask = 0x7
  22         }, {
  23                 .num = 2,
  24                 .pin = 21,
  25                 .reg = 0xe8,
  26                 .bit = 4,
  27                 .mask = 0x7
  28         }, {
  29                 .num = 2,
  30                 .pin = 22,
  31                 .reg = 0xe8,
  32                 .bit = 8,
  33                 .mask = 0x7
  34         }, {
  35                 .num = 2,
  36                 .pin = 23,
  37                 .reg = 0xe8,
  38                 .bit = 12,
  39                 .mask = 0x7
  40         }, {
  41                 .num = 2,
  42                 .pin = 24,
  43                 .reg = 0xd4,
  44                 .bit = 12,
  45                 .mask = 0x7
  46         },
  47 };
  48
  49 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
  50         {
  51                 /* spi-0 */
  52                 .bank_num = 1,
  53                 .pin = 10,
  54                 .func = 1,
  55                 .route_offset = 0x144,
  56                 .route_val = BIT(16 + 3) | BIT(16 + 4),
  57         }, {
  58                 /* spi-1 */
  59                 .bank_num = 1,
  60                 .pin = 27,
  61                 .func = 3,
  62                 .route_offset = 0x144,
  63                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
  64         }, {
  65                 /* spi-2 */
  66                 .bank_num = 0,
  67                 .pin = 13,
  68                 .func = 2,
  69                 .route_offset = 0x144,
  70                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
  71         }, {
  72                 /* i2s-0 */
  73                 .bank_num = 1,
  74                 .pin = 5,
  75                 .func = 1,
  76                 .route_offset = 0x144,
  77                 .route_val = BIT(16 + 5),
  78         }, {
  79                 /* i2s-1 */
  80                 .bank_num = 0,
  81                 .pin = 14,
  82                 .func = 1,
  83                 .route_offset = 0x144,
  84                 .route_val = BIT(16 + 5) | BIT(5),
  85         }, {
  86                 /* emmc-0 */
  87                 .bank_num = 1,
  88                 .pin = 22,
  89                 .func = 2,
  90                 .route_offset = 0x144,
  91                 .route_val = BIT(16 + 6),
  92         }, {
  93                 /* emmc-1 */
  94                 .bank_num = 2,
  95                 .pin = 4,
  96                 .func = 2,
  97                 .route_offset = 0x144,
  98                 .route_val = BIT(16 + 6) | BIT(6),
  99         },
 100 };
 101
 102 static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 103 {
 104         struct rockchip_pinctrl_priv *priv = bank->priv;
 105         int iomux_num = (pin / 8);
 106         struct regmap *regmap;
 107         int reg, ret, mask, mux_type;
 108         u8 bit;
 109         u32 data, route_reg, route_val;
 110
 111         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 112                                 ? priv->regmap_pmu : priv->regmap_base;
 113
 114         /* get basic quadrupel of mux registers and the correct reg inside */
 115         mux_type = bank->iomux[iomux_num].type;
 116         reg = bank->iomux[iomux_num].offset;
 117         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
 118
 119         if (bank->recalced_mask & BIT(pin))
 120                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 121
 122         if (bank->route_mask & BIT(pin)) {
 123                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
 124                                            &route_val)) {
 125                         ret = regmap_write(regmap, route_reg, route_val);
 126                         if (ret)
 127                                 return ret;
 128                 }
 129         }
 130
 131         data = (mask << (bit + 16));
 132         data |= (mux & mask) << bit;
 133         ret = regmap_write(regmap, reg, data);
 134
 135         return ret;
 136 }
 137
 138 #define RK3128_PULL_OFFSET              0x118
 139 #define RK3128_PULL_PINS_PER_REG        16
 140 #define RK3128_PULL_BANK_STRIDE         8
 141
 142 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 143                                          int pin_num, struct regmap **regmap,
 144                                          int *reg, u8 *bit)
 145 {
 146         struct rockchip_pinctrl_priv *priv = bank->priv;
 147
 148         *regmap = priv->regmap_base;
 149         *reg = RK3128_PULL_OFFSET;
 150         *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
 151         *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
 152
 153         *bit = pin_num % RK3128_PULL_PINS_PER_REG;
 154 }
 155
 156 static int rk3128_set_pull(struct rockchip_pin_bank *bank,
 157                            int pin_num, int pull)
 158 {
 159         struct regmap *regmap;
 160         int reg, ret;
 161         u8 bit;
 162         u32 data;
 163
 164         if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 165             pull != PIN_CONFIG_BIAS_DISABLE)
 166                 return -ENOTSUPP;
 167
 168         rk3128_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 169         data = BIT(bit + 16);
 170         if (pull == PIN_CONFIG_BIAS_DISABLE)
 171                 data |= BIT(bit);
 172         ret = regmap_write(regmap, reg, data);
 173
 174         return ret;
 175 }
 176
 177 static struct rockchip_pin_bank rk3128_pin_banks[] = {
 178         PIN_BANK(0, 32, "gpio0"),
 179         PIN_BANK(1, 32, "gpio1"),
 180         PIN_BANK(2, 32, "gpio2"),
 181         PIN_BANK(3, 32, "gpio3"),
 182 };
 183
 184 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
 185         .pin_banks              = rk3128_pin_banks,
 186         .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
 187         .grf_mux_offset         = 0xa8,
 188         .iomux_recalced         = rk3128_mux_recalced_data,
 189         .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
 190         .iomux_routes           = rk3128_mux_route_data,
 191         .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
 192         .set_mux                = rk3128_set_mux,
 193         .set_pull               = rk3128_set_pull,
 194 };
 195
 196 static const struct udevice_id rk3128_pinctrl_ids[] = {
 197         { .compatible = "rockchip,rk3128-pinctrl",
 198                 .data = (ulong)&rk3128_pin_ctrl },
 199         { }
 200 };
 201
 202 U_BOOT_DRIVER(pinctrl_rk3128) = {
 203         .name           = "pinctrl_rk3128",
 204         .id             = UCLASS_PINCTRL,
 205         .of_match       = rk3128_pinctrl_ids,
 206         .priv_auto      = sizeof(struct rockchip_pinctrl_priv),
 207         .ops            = &rockchip_pinctrl_ops,
 208 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 209         .bind           = dm_scan_fdt_dev,
 210 #endif
 211         .probe          = rockchip_pinctrl_probe,
 212 };