drivers/pinctrl/rockchip/pinctrl-rk3128.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/pinctrl.h>
   9 #include <regmap.h>
  10 #include <syscon.h>
  11
  12 #include "pinctrl-rockchip.h"
  13
  14 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
  15         {
  16                 .num = 2,
  17                 .pin = 20,
  18                 .reg = 0xe8,
  19                 .bit = 0,
  20                 .mask = 0x7
  21         }, {
  22                 .num = 2,
  23                 .pin = 21,
  24                 .reg = 0xe8,
  25                 .bit = 4,
  26                 .mask = 0x7
  27         }, {
  28                 .num = 2,
  29                 .pin = 22,
  30                 .reg = 0xe8,
  31                 .bit = 8,
  32                 .mask = 0x7
  33         }, {
  34                 .num = 2,
  35                 .pin = 23,
  36                 .reg = 0xe8,
  37                 .bit = 12,
  38                 .mask = 0x7
  39         }, {
  40                 .num = 2,
  41                 .pin = 24,
  42                 .reg = 0xd4,
  43                 .bit = 12,
  44                 .mask = 0x7
  45         },
  46 };
  47
  48 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
  49         {
  50                 /* spi-0 */
  51                 .bank_num = 1,
  52                 .pin = 10,
  53                 .func = 1,
  54                 .route_offset = 0x144,
  55                 .route_val = BIT(16 + 3) | BIT(16 + 4),
  56         }, {
  57                 /* spi-1 */
  58                 .bank_num = 1,
  59                 .pin = 27,
  60                 .func = 3,
  61                 .route_offset = 0x144,
  62                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
  63         }, {
  64                 /* spi-2 */
  65                 .bank_num = 0,
  66                 .pin = 13,
  67                 .func = 2,
  68                 .route_offset = 0x144,
  69                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
  70         }, {
  71                 /* i2s-0 */
  72                 .bank_num = 1,
  73                 .pin = 5,
  74                 .func = 1,
  75                 .route_offset = 0x144,
  76                 .route_val = BIT(16 + 5),
  77         }, {
  78                 /* i2s-1 */
  79                 .bank_num = 0,
  80                 .pin = 14,
  81                 .func = 1,
  82                 .route_offset = 0x144,
  83                 .route_val = BIT(16 + 5) | BIT(5),
  84         }, {
  85                 /* emmc-0 */
  86                 .bank_num = 1,
  87                 .pin = 22,
  88                 .func = 2,
  89                 .route_offset = 0x144,
  90                 .route_val = BIT(16 + 6),
  91         }, {
  92                 /* emmc-1 */
  93                 .bank_num = 2,
  94                 .pin = 4,
  95                 .func = 2,
  96                 .route_offset = 0x144,
  97                 .route_val = BIT(16 + 6) | BIT(6),
  98         },
  99 };
 100
 101 static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 102 {
 103         struct rockchip_pinctrl_priv *priv = bank->priv;
 104         int iomux_num = (pin / 8);
 105         struct regmap *regmap;
 106         int reg, ret, mask, mux_type;
 107         u8 bit;
 108         u32 data, route_reg, route_val;
 109
 110         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 111                                 ? priv->regmap_pmu : priv->regmap_base;
 112
 113         /* get basic quadrupel of mux registers and the correct reg inside */
 114         mux_type = bank->iomux[iomux_num].type;
 115         reg = bank->iomux[iomux_num].offset;
 116         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
 117
 118         if (bank->recalced_mask & BIT(pin))
 119                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 120
 121         if (bank->route_mask & BIT(pin)) {
 122                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
 123                                            &route_val)) {
 124                         ret = regmap_write(regmap, route_reg, route_val);
 125                         if (ret)
 126                                 return ret;
 127                 }
 128         }
 129
 130         data = (mask << (bit + 16));
 131         data |= (mux & mask) << bit;
 132         ret = regmap_write(regmap, reg, data);
 133
 134         return ret;
 135 }
 136
 137 #define RK3128_PULL_OFFSET              0x118
 138 #define RK3128_PULL_PINS_PER_REG        16
 139 #define RK3128_PULL_BANK_STRIDE         8
 140
 141 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 142                                          int pin_num, struct regmap **regmap,
 143                                          int *reg, u8 *bit)
 144 {
 145         struct rockchip_pinctrl_priv *priv = bank->priv;
 146
 147         *regmap = priv->regmap_base;
 148         *reg = RK3128_PULL_OFFSET;
 149         *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
 150         *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
 151
 152         *bit = pin_num % RK3128_PULL_PINS_PER_REG;
 153 }
 154
 155 static int rk3128_set_pull(struct rockchip_pin_bank *bank,
 156                            int pin_num, int pull)
 157 {
 158         struct regmap *regmap;
 159         int reg, ret;
 160         u8 bit;
 161         u32 data;
 162
 163         if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 164             pull != PIN_CONFIG_BIAS_DISABLE)
 165                 return -ENOTSUPP;
 166
 167         rk3128_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 168         data = BIT(bit + 16);
 169         if (pull == PIN_CONFIG_BIAS_DISABLE)
 170                 data |= BIT(bit);
 171         ret = regmap_write(regmap, reg, data);
 172
 173         return ret;
 174 }
 175
 176 static struct rockchip_pin_bank rk3128_pin_banks[] = {
 177         PIN_BANK(0, 32, "gpio0"),
 178         PIN_BANK(1, 32, "gpio1"),
 179         PIN_BANK(2, 32, "gpio2"),
 180         PIN_BANK(3, 32, "gpio3"),
 181 };
 182
 183 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
 184         .pin_banks              = rk3128_pin_banks,
 185         .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
 186         .grf_mux_offset         = 0xa8,
 187         .iomux_recalced         = rk3128_mux_recalced_data,
 188         .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
 189         .iomux_routes           = rk3128_mux_route_data,
 190         .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
 191         .set_mux                = rk3128_set_mux,
 192         .set_pull               = rk3128_set_pull,
 193 };
 194
 195 static const struct udevice_id rk3128_pinctrl_ids[] = {
 196         { .compatible = "rockchip,rk3128-pinctrl",
 197                 .data = (ulong)&rk3128_pin_ctrl },
 198         { }
 199 };
 200
 201 U_BOOT_DRIVER(pinctrl_rk3128) = {
 202         .name           = "pinctrl_rk3128",
 203         .id             = UCLASS_PINCTRL,
 204         .of_match       = rk3128_pinctrl_ids,
 205         .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
 206         .ops            = &rockchip_pinctrl_ops,
 207 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 208         .bind           = dm_scan_fdt_dev,
 209 #endif
 210         .probe          = rockchip_pinctrl_probe,
 211 };