drivers/pinctrl/rockchip/pinctrl-px30.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <log.h>
   9 #include <dm/pinctrl.h>
  10 #include <regmap.h>
  11 #include <syscon.h>
  12 #include <linux/bitops.h>
  13
  14 #include "pinctrl-rockchip.h"
  15
  16 static struct rockchip_mux_route_data px30_mux_route_data[] = {
  17         {
  18                 /* cif-d2m0 */
  19                 .bank_num = 2,
  20                 .pin = 0,
  21                 .func = 1,
  22                 .route_offset = 0x184,
  23                 .route_val = BIT(16 + 7),
  24         }, {
  25                 /* cif-d2m1 */
  26                 .bank_num = 3,
  27                 .pin = 3,
  28                 .func = 3,
  29                 .route_offset = 0x184,
  30                 .route_val = BIT(16 + 7) | BIT(7),
  31         }, {
  32                 /* pdm-m0 */
  33                 .bank_num = 3,
  34                 .pin = 22,
  35                 .func = 2,
  36                 .route_offset = 0x184,
  37                 .route_val = BIT(16 + 8),
  38         }, {
  39                 /* pdm-m1 */
  40                 .bank_num = 2,
  41                 .pin = 22,
  42                 .func = 1,
  43                 .route_offset = 0x184,
  44                 .route_val = BIT(16 + 8) | BIT(8),
  45         }, {
  46                 /* uart2-rxm0 */
  47                 .bank_num = 1,
  48                 .pin = 27,
  49                 .func = 2,
  50                 .route_offset = 0x184,
  51                 .route_val = BIT(16 + 10),
  52         }, {
  53                 /* uart2-rxm1 */
  54                 .bank_num = 2,
  55                 .pin = 14,
  56                 .func = 2,
  57                 .route_offset = 0x184,
  58                 .route_val = BIT(16 + 10) | BIT(10),
  59         }, {
  60                 /* uart3-rxm0 */
  61                 .bank_num = 0,
  62                 .pin = 17,
  63                 .func = 2,
  64                 .route_offset = 0x184,
  65                 .route_val = BIT(16 + 9),
  66         }, {
  67                 /* uart3-rxm1 */
  68                 .bank_num = 1,
  69                 .pin = 15,
  70                 .func = 2,
  71                 .route_offset = 0x184,
  72                 .route_val = BIT(16 + 9) | BIT(9),
  73         },
  74 };
  75
  76 static int px30_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  77 {
  78         struct rockchip_pinctrl_priv *priv = bank->priv;
  79         int iomux_num = (pin / 8);
  80         struct regmap *regmap;
  81         int reg, ret, mask, mux_type;
  82         u8 bit;
  83         u32 data, route_reg, route_val;
  84
  85         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  86                                 ? priv->regmap_pmu : priv->regmap_base;
  87
  88         /* get basic quadrupel of mux registers and the correct reg inside */
  89         mux_type = bank->iomux[iomux_num].type;
  90         reg = bank->iomux[iomux_num].offset;
  91         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
  92
  93         if (bank->route_mask & BIT(pin)) {
  94                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
  95                                            &route_val)) {
  96                         ret = regmap_write(regmap, route_reg, route_val);
  97                         if (ret)
  98                                 return ret;
  99                 }
 100         }
 101
 102         data = (mask << (bit + 16));
 103         data |= (mux & mask) << bit;
 104         ret = regmap_write(regmap, reg, data);
 105
 106         return ret;
 107 }
 108
 109 #define PX30_PULL_PMU_OFFSET            0x10
 110 #define PX30_PULL_GRF_OFFSET            0x60
 111 #define PX30_PULL_BITS_PER_PIN          2
 112 #define PX30_PULL_PINS_PER_REG          8
 113 #define PX30_PULL_BANK_STRIDE           16
 114
 115 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 116                                        int pin_num, struct regmap **regmap,
 117                                        int *reg, u8 *bit)
 118 {
 119         struct rockchip_pinctrl_priv *priv = bank->priv;
 120
 121         /* The first 32 pins of the first bank are located in PMU */
 122         if (bank->bank_num == 0) {
 123                 *regmap = priv->regmap_pmu;
 124                 *reg = PX30_PULL_PMU_OFFSET;
 125         } else {
 126                 *regmap = priv->regmap_base;
 127                 *reg = PX30_PULL_GRF_OFFSET;
 128
 129                 /* correct the offset, as we're starting with the 2nd bank */
 130                 *reg -= 0x10;
 131                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
 132         }
 133
 134         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
 135         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
 136         *bit *= PX30_PULL_BITS_PER_PIN;
 137 }
 138
 139 static int px30_set_pull(struct rockchip_pin_bank *bank,
 140                          int pin_num, int pull)
 141 {
 142         struct regmap *regmap;
 143         int reg, ret;
 144         u8 bit, type;
 145         u32 data;
 146
 147         if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
 148                 return -ENOTSUPP;
 149
 150         px30_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 151         type = bank->pull_type[pin_num / 8];
 152         ret = rockchip_translate_pull_value(type, pull);
 153         if (ret < 0) {
 154                 debug("unsupported pull setting %d\n", pull);
 155                 return ret;
 156         }
 157
 158         /* enable the write to the equivalent lower bits */
 159         data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 160         data |= (ret << bit);
 161         ret = regmap_write(regmap, reg, data);
 162
 163         return ret;
 164 }
 165
 166 #define PX30_DRV_PMU_OFFSET             0x20
 167 #define PX30_DRV_GRF_OFFSET             0xf0
 168 #define PX30_DRV_BITS_PER_PIN           2
 169 #define PX30_DRV_PINS_PER_REG           8
 170 #define PX30_DRV_BANK_STRIDE            16
 171
 172 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 173                                       int pin_num, struct regmap **regmap,
 174                                       int *reg, u8 *bit)
 175 {
 176         struct rockchip_pinctrl_priv *priv = bank->priv;
 177
 178         /* The first 32 pins of the first bank are located in PMU */
 179         if (bank->bank_num == 0) {
 180                 *regmap = priv->regmap_pmu;
 181                 *reg = PX30_DRV_PMU_OFFSET;
 182         } else {
 183                 *regmap = priv->regmap_base;
 184                 *reg = PX30_DRV_GRF_OFFSET;
 185
 186                 /* correct the offset, as we're starting with the 2nd bank */
 187                 *reg -= 0x10;
 188                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
 189         }
 190
 191         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
 192         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
 193         *bit *= PX30_DRV_BITS_PER_PIN;
 194 }
 195
 196 static int px30_set_drive(struct rockchip_pin_bank *bank,
 197                           int pin_num, int strength)
 198 {
 199         struct regmap *regmap;
 200         int reg, ret;
 201         u32 data, rmask_bits, temp;
 202         u8 bit;
 203         int drv_type = bank->drv[pin_num / 8].drv_type;
 204
 205         px30_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 206         ret = rockchip_translate_drive_value(drv_type, strength);
 207         if (ret < 0) {
 208                 debug("unsupported driver strength %d\n", strength);
 209                 return ret;
 210         }
 211
 212         switch (drv_type) {
 213         case DRV_TYPE_IO_1V8_3V0_AUTO:
 214         case DRV_TYPE_IO_3V3_ONLY:
 215                 rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
 216                 switch (bit) {
 217                 case 0 ... 12:
 218                         /* regular case, nothing to do */
 219                         break;
 220                 case 15:
 221                         /*
 222                          * drive-strength offset is special, as it is spread
 223                          * over 2 registers, the bit data[15] contains bit 0
 224                          * of the value while temp[1:0] contains bits 2 and 1
 225                          */
 226                         data = (ret & 0x1) << 15;
 227                         temp = (ret >> 0x1) & 0x3;
 228
 229                         data |= BIT(31);
 230                         ret = regmap_write(regmap, reg, data);
 231                         if (ret)
 232                                 return ret;
 233
 234                         temp |= (0x3 << 16);
 235                         reg += 0x4;
 236                         ret = regmap_write(regmap, reg, temp);
 237
 238                         return ret;
 239                 case 18 ... 21:
 240                         /* setting fully enclosed in the second register */
 241                         reg += 4;
 242                         bit -= 16;
 243                         break;
 244                 default:
 245                         debug("unsupported bit: %d for pinctrl drive type: %d\n",
 246                               bit, drv_type);
 247                         return -EINVAL;
 248                 }
 249                 break;
 250         case DRV_TYPE_IO_DEFAULT:
 251         case DRV_TYPE_IO_1V8_OR_3V0:
 252         case DRV_TYPE_IO_1V8_ONLY:
 253                 rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
 254                 break;
 255         default:
 256                 debug("unsupported pinctrl drive type: %d\n",
 257                       drv_type);
 258                 return -EINVAL;
 259         }
 260
 261         /* enable the write to the equivalent lower bits */
 262         data = ((1 << rmask_bits) - 1) << (bit + 16);
 263         data |= (ret << bit);
 264         ret = regmap_write(regmap, reg, data);
 265
 266         return ret;
 267 }
 268
 269 #define PX30_SCHMITT_PMU_OFFSET                 0x38
 270 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
 271 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
 272 #define PX30_SCHMITT_BANK_STRIDE                16
 273 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
 274
 275 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
 276                                          int pin_num,
 277                                          struct regmap **regmap,
 278                                          int *reg, u8 *bit)
 279 {
 280         struct rockchip_pinctrl_priv *priv = bank->priv;
 281         int pins_per_reg;
 282
 283         if (bank->bank_num == 0) {
 284                 *regmap = priv->regmap_pmu;
 285                 *reg = PX30_SCHMITT_PMU_OFFSET;
 286                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
 287         } else {
 288                 *regmap = priv->regmap_base;
 289                 *reg = PX30_SCHMITT_GRF_OFFSET;
 290                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
 291                 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
 292         }
 293         *reg += ((pin_num / pins_per_reg) * 4);
 294         *bit = pin_num % pins_per_reg;
 295
 296         return 0;
 297 }
 298
 299 static int px30_set_schmitt(struct rockchip_pin_bank *bank,
 300                             int pin_num, int enable)
 301 {
 302         struct regmap *regmap;
 303         int reg;
 304         u8 bit;
 305         u32 data;
 306
 307         px30_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 308         /* enable the write to the equivalent lower bits */
 309         data = BIT(bit + 16) | (enable << bit);
 310
 311         return regmap_write(regmap, reg, data);
 312 }
 313
 314 static struct rockchip_pin_bank px30_pin_banks[] = {
 315         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
 316                                              IOMUX_SOURCE_PMU,
 317                                              IOMUX_SOURCE_PMU,
 318                                              IOMUX_SOURCE_PMU
 319                             ),
 320         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
 321                                              IOMUX_WIDTH_4BIT,
 322                                              IOMUX_WIDTH_4BIT,
 323                                              IOMUX_WIDTH_4BIT
 324                             ),
 325         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
 326                                              IOMUX_WIDTH_4BIT,
 327                                              IOMUX_WIDTH_4BIT,
 328                                              IOMUX_WIDTH_4BIT
 329                             ),
 330         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
 331                                              IOMUX_WIDTH_4BIT,
 332                                              IOMUX_WIDTH_4BIT,
 333                                              IOMUX_WIDTH_4BIT
 334                             ),
 335 };
 336
 337 static struct rockchip_pin_ctrl px30_pin_ctrl = {
 338         .pin_banks              = px30_pin_banks,
 339         .nr_banks               = ARRAY_SIZE(px30_pin_banks),
 340         .grf_mux_offset         = 0x0,
 341         .pmu_mux_offset         = 0x0,
 342         .grf_drv_offset         = 0xf0,
 343         .pmu_drv_offset         = 0x20,
 344         .iomux_routes           = px30_mux_route_data,
 345         .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
 346         .set_mux                = px30_set_mux,
 347         .set_pull               = px30_set_pull,
 348         .set_drive              = px30_set_drive,
 349         .set_schmitt            = px30_set_schmitt,
 350 };
 351
 352 static const struct udevice_id px30_pinctrl_ids[] = {
 353         {
 354                 .compatible = "rockchip,px30-pinctrl",
 355                 .data = (ulong)&px30_pin_ctrl
 356         },
 357         { }
 358 };
 359
 360 U_BOOT_DRIVER(pinctrl_px30) = {
 361         .name           = "rockchip_px30_pinctrl",
 362         .id             = UCLASS_PINCTRL,
 363         .of_match       = px30_pinctrl_ids,
 364         .priv_auto      = sizeof(struct rockchip_pinctrl_priv),
 365         .ops            = &rockchip_pinctrl_ops,
 366 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 367         .bind           = dm_scan_fdt_dev,
 368 #endif
 369         .probe          = rockchip_pinctrl_probe,
 370 };