2 * SuperH Pin Function Controller Support
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/stringify.h>
24 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
25 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
26 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
27 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
28 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
29 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
30 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
39 #define SH_PFC_PIN_GROUP(n) \
44 .nr_pins = ARRAY_SIZE(n##_pins), \
47 struct sh_pfc_pin_group {
49 const unsigned int *pins;
50 const unsigned int *mux;
55 * Using union vin_data saves memory occupied by the VIN data pins.
56 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
59 #define VIN_DATA_PIN_GROUP(n, s) \
62 .pins = n##_pins.data##s, \
63 .mux = n##_mux.data##s, \
64 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
68 unsigned int data24[24];
69 unsigned int data20[20];
70 unsigned int data16[16];
71 unsigned int data12[12];
72 unsigned int data10[10];
73 unsigned int data8[8];
74 unsigned int data4[4];
77 #define SH_PFC_FUNCTION(n) \
80 .groups = n##_groups, \
81 .nr_groups = ARRAY_SIZE(n##_groups), \
84 struct sh_pfc_function {
86 const char * const *groups;
87 unsigned int nr_groups;
95 struct pinmux_cfg_reg {
97 u8 reg_width, field_width;
99 const u8 *var_field_width;
103 * Describe a config register consisting of several fields of the same width
104 * - name: Register name (unused, for documentation purposes only)
105 * - r: Physical register address
106 * - r_width: Width of the register (in bits)
107 * - f_width: Width of the fixed-width register fields (in bits)
108 * This macro must be followed by initialization data: For each register field
109 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
110 * one for each possible combination of the register field bit values.
112 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
113 .reg = r, .reg_width = r_width, .field_width = f_width, \
114 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
117 * Describe a config register consisting of several fields of different widths
118 * - name: Register name (unused, for documentation purposes only)
119 * - r: Physical register address
120 * - r_width: Width of the register (in bits)
121 * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
122 * From left to right (i.e. MSB to LSB)
123 * This macro must be followed by initialization data: For each register field
124 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
125 * one for each possible combination of the register field bit values.
127 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
128 .reg = r, .reg_width = r_width, \
129 .var_field_width = (const u8 [r_width]) \
130 { var_fw0, var_fwn, 0 }, \
131 .enum_ids = (const u16 [])
133 struct pinmux_drive_reg_field {
139 struct pinmux_drive_reg {
141 const struct pinmux_drive_reg_field fields[8];
144 #define PINMUX_DRIVE_REG(name, r) \
148 struct pinmux_data_reg {
155 * Describe a data register
156 * - name: Register name (unused, for documentation purposes only)
157 * - r: Physical register address
158 * - r_width: Width of the register (in bits)
159 * This macro must be followed by initialization data: For each register bit
160 * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
162 #define PINMUX_DATA_REG(name, r, r_width) \
163 .reg = r, .reg_width = r_width, \
164 .enum_ids = (const u16 [r_width]) \
171 * Describe the mapping from GPIOs to a single IRQ
172 * - ids...: List of GPIOs that are mapped to the same IRQ
174 #define PINMUX_IRQ(ids...) \
175 { .gpios = (const short []) { ids, -1 } }
177 struct pinmux_range {
183 struct sh_pfc_bias_info {
189 struct sh_pfc_pin_range;
193 const struct sh_pfc_soc_info *info;
197 struct sh_pfc_pin_range *ranges;
198 unsigned int nr_ranges;
200 unsigned int nr_gpio_pins;
202 struct sh_pfc_chip *gpio;
205 struct sh_pfc_soc_operations {
206 int (*init)(struct sh_pfc *pfc);
207 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
208 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
210 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
213 struct sh_pfc_soc_info {
215 const struct sh_pfc_soc_operations *ops;
217 struct pinmux_range input;
218 struct pinmux_range output;
219 struct pinmux_range function;
221 const struct sh_pfc_pin *pins;
222 unsigned int nr_pins;
223 const struct sh_pfc_pin_group *groups;
224 unsigned int nr_groups;
225 const struct sh_pfc_function *functions;
226 unsigned int nr_functions;
228 const struct pinmux_cfg_reg *cfg_regs;
229 const struct pinmux_drive_reg *drive_regs;
230 const struct pinmux_data_reg *data_regs;
232 const u16 *pinmux_data;
233 unsigned int pinmux_data_size;
235 const struct pinmux_irq *gpio_irq;
236 unsigned int gpio_irq_size;
241 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
242 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);
243 const struct sh_pfc_bias_info *
244 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
245 unsigned int num, unsigned int pin);
246 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
248 extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
249 extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
250 /* -----------------------------------------------------------------------------
251 * Helper macros to create pin and port lists
255 * sh_pfc_soc_info pinmux_data array macros
259 * Describe generic pinmux data
260 * - data_or_mark: *_DATA or *_MARK enum ID
261 * - ids...: List of enum IDs to associate with data_or_mark
263 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
266 * Describe a pinmux configuration without GPIO function that needs
267 * configuration in a Peripheral Function Select Register (IPSR)
268 * - ipsr: IPSR field (unused, for documentation purposes only)
269 * - fn: Function name, referring to a field in the IPSR
271 #define PINMUX_IPSR_NOGP(ipsr, fn) \
272 PINMUX_DATA(fn##_MARK, FN_##fn)
275 * Describe a pinmux configuration with GPIO function that needs configuration
276 * in both a Peripheral Function Select Register (IPSR) and in a
277 * GPIO/Peripheral Function Select Register (GPSR)
279 * - fn: Function name, also referring to the IPSR field
281 #define PINMUX_IPSR_GPSR(ipsr, fn) \
282 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
285 * Describe a pinmux configuration without GPIO function that needs
286 * configuration in a Peripheral Function Select Register (IPSR), and where the
287 * pinmux function has a representation in a Module Select Register (MOD_SEL).
288 * - ipsr: IPSR field (unused, for documentation purposes only)
289 * - fn: Function name, also referring to the IPSR field
290 * - msel: Module selector
292 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
293 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
296 * Describe a pinmux configuration with GPIO function where the pinmux function
297 * has no representation in a Peripheral Function Select Register (IPSR), but
298 * instead solely depends on a group selection.
300 * - fn: Function name, also referring to the GPSR field
301 * - gsel: Group selector
303 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
304 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
307 * Describe a pinmux configuration with GPIO function that needs configuration
308 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
309 * Function Select Register (GPSR), and where the pinmux function has a
310 * representation in a Module Select Register (MOD_SEL).
312 * - fn: Function name, also referring to the IPSR field
313 * - msel: Module selector
315 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
316 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
319 * Describe a pinmux configuration for a single-function pin with GPIO
321 * - fn: Function name
323 #define PINMUX_SINGLE(fn) \
324 PINMUX_DATA(fn##_MARK, FN_##fn)
327 * GP port style (32 ports banks)
330 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
331 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
332 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
334 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
335 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
336 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
337 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
338 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
339 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
341 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
342 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
343 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
344 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
345 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
346 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
347 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
349 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
350 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
351 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
352 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
354 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
355 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
356 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
357 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
359 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
360 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
361 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
362 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
363 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
365 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
366 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
367 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
368 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
369 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
371 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
372 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
373 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
374 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
376 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
377 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
378 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
379 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
381 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
382 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
383 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
384 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
386 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
387 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
388 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
389 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
391 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
392 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
393 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
394 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
395 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
397 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
398 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
399 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
400 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
402 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
403 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
404 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
405 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
406 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
408 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
409 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
410 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
411 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
413 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
414 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
415 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
416 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
417 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
419 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
420 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
421 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
422 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
423 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
425 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
426 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
427 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
428 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
430 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
431 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
432 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
433 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
435 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
436 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
437 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
438 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
439 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
441 #define PORT_GP_32_REV(bank, fn, sfx) \
442 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
443 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
444 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
445 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
446 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
447 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
448 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
449 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
450 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
451 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
452 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
453 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
454 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
455 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
456 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
457 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
459 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
460 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
461 #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
463 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
464 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
466 .pin = (bank * 32) + _pin, \
467 .name = __stringify(_name), \
468 .enum_id = _name##_DATA, \
471 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
473 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
474 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
475 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
478 * PORT style (linear pin space)
481 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
483 #define PORT_10(pn, fn, pfx, sfx) \
484 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
485 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
486 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
487 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
488 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
490 #define PORT_90(pn, fn, pfx, sfx) \
491 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
492 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
493 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
494 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
495 PORT_10(pn+90, fn, pfx##9, sfx)
497 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
498 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
499 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
501 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
502 #define PINMUX_GPIO(_pin) \
505 .name = __stringify(GPIO_##_pin), \
506 .enum_id = _pin##_DATA, \
509 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
510 #define SH_PFC_PIN_CFG(_pin, cfgs) \
513 .name = __stringify(PORT##_pin), \
514 .enum_id = PORT##_pin##_DATA, \
518 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
519 #define SH_PFC_PIN_NAMED(row, col, _name) \
521 .pin = PIN_NUMBER(row, col), \
522 .name = __stringify(PIN_##_name), \
523 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
526 /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
527 #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
529 .pin = PIN_NUMBER(row, col), \
530 .name = __stringify(PIN_##_name), \
531 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
534 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
535 * PORT_name_OUT, PORT_name_IN marks
537 #define _PORT_DATA(pn, pfx, sfx) \
538 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
539 PORT##pfx##_OUT, PORT##pfx##_IN)
540 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
542 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
543 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
544 [gpio - (base)] = { \
545 .name = __stringify(gpio), \
546 .enum_id = data_or_mark, \
548 #define GPIO_FN(str) \
549 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
552 * PORTnCR helper macro for SH-Mobile/R-Mobile
554 #define PORTCR(nr, reg) \
556 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
557 /* PULMD[1:0], handled by .set_bias() */ \
560 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
561 /* SEC, not supported */ \
564 PORT##nr##_FN0, PORT##nr##_FN1, \
565 PORT##nr##_FN2, PORT##nr##_FN3, \
566 PORT##nr##_FN4, PORT##nr##_FN5, \
567 PORT##nr##_FN6, PORT##nr##_FN7 \
572 * GPIO number helper macro for R-Car
574 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
576 #endif /* __SH_PFC_H */