drivers/pinctrl/renesas/pfc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  * Copyright (C) 2017 Marek Vasut
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/io.h>
  19 #include <linux/sizes.h>
  20
  21 #include "sh_pfc.h"
  22
  23 enum sh_pfc_model {
  24         SH_PFC_R8A7790 = 0,
  25         SH_PFC_R8A7791,
  26         SH_PFC_R8A7792,
  27         SH_PFC_R8A7793,
  28         SH_PFC_R8A7794,
  29         SH_PFC_R8A7795,
  30         SH_PFC_R8A7796,
  31         SH_PFC_R8A77965,
  32         SH_PFC_R8A77970,
  33         SH_PFC_R8A77990,
  34         SH_PFC_R8A77995,
  35 };
  36
  37 struct sh_pfc_pin_config {
  38         u32 type;
  39 };
  40
  41 struct sh_pfc_pinctrl {
  42         struct sh_pfc *pfc;
  43
  44         struct sh_pfc_pin_config *configs;
  45
  46         const char *func_prop_name;
  47         const char *groups_prop_name;
  48         const char *pins_prop_name;
  49 };
  50
  51 struct sh_pfc_pin_range {
  52         u16 start;
  53         u16 end;
  54 };
  55
  56 struct sh_pfc_pinctrl_priv {
  57         struct sh_pfc                   pfc;
  58         struct sh_pfc_pinctrl           pmx;
  59 };
  60
  61 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  62 {
  63         unsigned int offset;
  64         unsigned int i;
  65
  66         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  67                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  68
  69                 if (pin <= range->end)
  70                         return pin >= range->start
  71                              ? offset + pin - range->start : -1;
  72
  73                 offset += range->end - range->start + 1;
  74         }
  75
  76         return -EINVAL;
  77 }
  78
  79 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  80 {
  81         if (enum_id < r->begin)
  82                 return 0;
  83
  84         if (enum_id > r->end)
  85                 return 0;
  86
  87         return 1;
  88 }
  89
  90 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  91 {
  92         switch (reg_width) {
  93         case 8:
  94                 return readb(mapped_reg);
  95         case 16:
  96                 return readw(mapped_reg);
  97         case 32:
  98                 return readl(mapped_reg);
  99         }
 100
 101         BUG();
 102         return 0;
 103 }
 104
 105 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 106                           u32 data)
 107 {
 108         switch (reg_width) {
 109         case 8:
 110                 writeb(data, mapped_reg);
 111                 return;
 112         case 16:
 113                 writew(data, mapped_reg);
 114                 return;
 115         case 32:
 116                 writel(data, mapped_reg);
 117                 return;
 118         }
 119
 120         BUG();
 121 }
 122
 123 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 124 {
 125         return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
 126 }
 127
 128 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 129 {
 130         void __iomem *unlock_reg =
 131                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 132
 133         if (pfc->info->unlock_reg)
 134                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 135
 136         sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
 137 }
 138
 139 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 140                                      const struct pinmux_cfg_reg *crp,
 141                                      unsigned int in_pos,
 142                                      void __iomem **mapped_regp, u32 *maskp,
 143                                      unsigned int *posp)
 144 {
 145         unsigned int k;
 146
 147         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 148
 149         if (crp->field_width) {
 150                 *maskp = (1 << crp->field_width) - 1;
 151                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 152         } else {
 153                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 154                 *posp = crp->reg_width;
 155                 for (k = 0; k <= in_pos; k++)
 156                         *posp -= crp->var_field_width[k];
 157         }
 158 }
 159
 160 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 161                                     const struct pinmux_cfg_reg *crp,
 162                                     unsigned int field, u32 value)
 163 {
 164         void __iomem *mapped_reg;
 165         void __iomem *unlock_reg =
 166                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 167         unsigned int pos;
 168         u32 mask, data;
 169
 170         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 171
 172         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 173                 "r_width = %u, f_width = %u\n",
 174                 crp->reg, value, field, crp->reg_width, crp->field_width);
 175
 176         mask = ~(mask << pos);
 177         value = value << pos;
 178
 179         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 180         data &= mask;
 181         data |= value;
 182
 183         if (pfc->info->unlock_reg)
 184                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 185
 186         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 187 }
 188
 189 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 190                                  const struct pinmux_cfg_reg **crp,
 191                                  unsigned int *fieldp, u32 *valuep)
 192 {
 193         unsigned int k = 0;
 194
 195         while (1) {
 196                 const struct pinmux_cfg_reg *config_reg =
 197                         pfc->info->cfg_regs + k;
 198                 unsigned int r_width = config_reg->reg_width;
 199                 unsigned int f_width = config_reg->field_width;
 200                 unsigned int curr_width;
 201                 unsigned int bit_pos;
 202                 unsigned int pos = 0;
 203                 unsigned int m = 0;
 204
 205                 if (!r_width)
 206                         break;
 207
 208                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 209                         u32 ncomb;
 210                         u32 n;
 211
 212                         if (f_width)
 213                                 curr_width = f_width;
 214                         else
 215                                 curr_width = config_reg->var_field_width[m];
 216
 217                         ncomb = 1 << curr_width;
 218                         for (n = 0; n < ncomb; n++) {
 219                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 220                                         *crp = config_reg;
 221                                         *fieldp = m;
 222                                         *valuep = n;
 223                                         return 0;
 224                                 }
 225                         }
 226                         pos += ncomb;
 227                         m++;
 228                 }
 229                 k++;
 230         }
 231
 232         return -EINVAL;
 233 }
 234
 235 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 236                               u16 *enum_idp)
 237 {
 238         const u16 *data = pfc->info->pinmux_data;
 239         unsigned int k;
 240
 241         if (pos) {
 242                 *enum_idp = data[pos + 1];
 243                 return pos + 1;
 244         }
 245
 246         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 247                 if (data[k] == mark) {
 248                         *enum_idp = data[k + 1];
 249                         return k + 1;
 250                 }
 251         }
 252
 253         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 254                 mark);
 255         return -EINVAL;
 256 }
 257
 258 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 259 {
 260         const struct pinmux_range *range;
 261         int pos = 0;
 262
 263         switch (pinmux_type) {
 264         case PINMUX_TYPE_GPIO:
 265         case PINMUX_TYPE_FUNCTION:
 266                 range = NULL;
 267                 break;
 268
 269         case PINMUX_TYPE_OUTPUT:
 270                 range = &pfc->info->output;
 271                 break;
 272
 273         case PINMUX_TYPE_INPUT:
 274                 range = &pfc->info->input;
 275                 break;
 276
 277         default:
 278                 return -EINVAL;
 279         }
 280
 281         /* Iterate over all the configuration fields we need to update. */
 282         while (1) {
 283                 const struct pinmux_cfg_reg *cr;
 284                 unsigned int field;
 285                 u16 enum_id;
 286                 u32 value;
 287                 int in_range;
 288                 int ret;
 289
 290                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 291                 if (pos < 0)
 292                         return pos;
 293
 294                 if (!enum_id)
 295                         break;
 296
 297                 /* Check if the configuration field selects a function. If it
 298                  * doesn't, skip the field if it's not applicable to the
 299                  * requested pinmux type.
 300                  */
 301                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 302                 if (!in_range) {
 303                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 304                                 /* Functions are allowed to modify all
 305                                  * fields.
 306                                  */
 307                                 in_range = 1;
 308                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 309                                 /* Input/output types can only modify fields
 310                                  * that correspond to their respective ranges.
 311                                  */
 312                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 313
 314                                 /*
 315                                  * special case pass through for fixed
 316                                  * input-only or output-only pins without
 317                                  * function enum register association.
 318                                  */
 319                                 if (in_range && enum_id == range->force)
 320                                         continue;
 321                         }
 322                         /* GPIOs are only allowed to modify function fields. */
 323                 }
 324
 325                 if (!in_range)
 326                         continue;
 327
 328                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 329                 if (ret < 0)
 330                         return ret;
 331
 332                 sh_pfc_write_config_reg(pfc, cr, field, value);
 333         }
 334
 335         return 0;
 336 }
 337
 338 const struct pinmux_bias_reg *
 339 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
 340                        unsigned int *bit)
 341 {
 342         unsigned int i, j;
 343
 344         for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 345                 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
 346                         if (pfc->info->bias_regs[i].pins[j] == pin) {
 347                                 *bit = j;
 348                                 return &pfc->info->bias_regs[i];
 349                         }
 350                 }
 351         }
 352
 353         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 354
 355         return NULL;
 356 }
 357
 358 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 359 {
 360         struct sh_pfc_pin_range *range;
 361         unsigned int nr_ranges;
 362         unsigned int i;
 363
 364         if (pfc->info->pins[0].pin == (u16)-1) {
 365                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 366                  * in its pin arrays yet. Consider the pin numbers range as
 367                  * continuous and allocate a single range.
 368                  */
 369                 pfc->nr_ranges = 1;
 370                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 371                 if (pfc->ranges == NULL)
 372                         return -ENOMEM;
 373
 374                 pfc->ranges->start = 0;
 375                 pfc->ranges->end = pfc->info->nr_pins - 1;
 376                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 377
 378                 return 0;
 379         }
 380
 381         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 382          * be sorted by pin numbers, and pins without a GPIO port must come
 383          * last.
 384          */
 385         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 386                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 387                         nr_ranges++;
 388         }
 389
 390         pfc->nr_ranges = nr_ranges;
 391         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 392         if (pfc->ranges == NULL)
 393                 return -ENOMEM;
 394
 395         range = pfc->ranges;
 396         range->start = pfc->info->pins[0].pin;
 397
 398         for (i = 1; i < pfc->info->nr_pins; ++i) {
 399                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 400                         continue;
 401
 402                 range->end = pfc->info->pins[i-1].pin;
 403                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 404                         pfc->nr_gpio_pins = range->end + 1;
 405
 406                 range++;
 407                 range->start = pfc->info->pins[i].pin;
 408         }
 409
 410         range->end = pfc->info->pins[i-1].pin;
 411         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 412                 pfc->nr_gpio_pins = range->end + 1;
 413
 414         return 0;
 415 }
 416
 417 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 418 {
 419         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 420
 421         return priv->pfc.info->nr_pins;
 422 }
 423
 424 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 425                                                   unsigned selector)
 426 {
 427         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 428
 429         return priv->pfc.info->pins[selector].name;
 430 }
 431
 432 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 433 {
 434         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 435
 436         return priv->pfc.info->nr_groups;
 437 }
 438
 439 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 440                                                   unsigned selector)
 441 {
 442         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 443
 444         return priv->pfc.info->groups[selector].name;
 445 }
 446
 447 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 448 {
 449         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 450
 451         return priv->pfc.info->nr_functions;
 452 }
 453
 454 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 455                                                   unsigned selector)
 456 {
 457         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 458
 459         return priv->pfc.info->functions[selector].name;
 460 }
 461
 462 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
 463 {
 464         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 465         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 466         struct sh_pfc *pfc = &priv->pfc;
 467         struct sh_pfc_pin_config *cfg;
 468         const struct sh_pfc_pin *pin = NULL;
 469         int i, idx;
 470
 471         for (i = 1; i < pfc->info->nr_pins; i++) {
 472                 if (priv->pfc.info->pins[i].pin != pin_selector)
 473                         continue;
 474
 475                 pin = &priv->pfc.info->pins[i];
 476                 break;
 477         }
 478
 479         if (!pin)
 480                 return -EINVAL;
 481
 482         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 483         cfg = &pmx->configs[idx];
 484
 485         if (cfg->type != PINMUX_TYPE_NONE)
 486                 return -EBUSY;
 487
 488         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 489 }
 490
 491 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 492                                   unsigned func_selector)
 493 {
 494         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 495         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 496         struct sh_pfc *pfc = &priv->pfc;
 497         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 498         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 499         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 500
 501         if (cfg->type != PINMUX_TYPE_NONE)
 502                 return -EBUSY;
 503
 504         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 505 }
 506
 507 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 508                                      unsigned func_selector)
 509 {
 510         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 511         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 512         struct sh_pfc *pfc = &priv->pfc;
 513         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 514         unsigned int i;
 515         int ret = 0;
 516
 517         for (i = 0; i < grp->nr_pins; ++i) {
 518                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 519                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 520
 521                 if (cfg->type != PINMUX_TYPE_NONE) {
 522                         ret = -EBUSY;
 523                         goto done;
 524                 }
 525         }
 526
 527         for (i = 0; i < grp->nr_pins; ++i) {
 528                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 529                 if (ret < 0)
 530                         break;
 531         }
 532
 533 done:
 534         return ret;
 535 }
 536 #if CONFIG_IS_ENABLED(PINCONF)
 537 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 538         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 539         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 540         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 541         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 542         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 543 };
 544
 545 static void __iomem *
 546 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 547                                        unsigned int *offset, unsigned int *size)
 548 {
 549         const struct pinmux_drive_reg_field *field;
 550         const struct pinmux_drive_reg *reg;
 551         unsigned int i;
 552
 553         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 554                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 555                         field = &reg->fields[i];
 556
 557                         if (field->size && field->pin == pin) {
 558                                 *offset = field->offset;
 559                                 *size = field->size;
 560
 561                                 return (void __iomem *)(uintptr_t)reg->reg;
 562                         }
 563                 }
 564         }
 565
 566         return NULL;
 567 }
 568
 569 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 570                                              unsigned int pin, u16 strength)
 571 {
 572         unsigned int offset;
 573         unsigned int size;
 574         unsigned int step;
 575         void __iomem *reg;
 576         void __iomem *unlock_reg =
 577                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 578         u32 val;
 579
 580         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 581         if (!reg)
 582                 return -EINVAL;
 583
 584         step = size == 2 ? 6 : 3;
 585
 586         if (strength < step || strength > 24)
 587                 return -EINVAL;
 588
 589         /* Convert the value from mA based on a full drive strength value of
 590          * 24mA. We can make the full value configurable later if needed.
 591          */
 592         strength = strength / step - 1;
 593
 594         val = sh_pfc_read_raw_reg(reg, 32);
 595         val &= ~GENMASK(offset + 4 - 1, offset);
 596         val |= strength << offset;
 597
 598         if (unlock_reg)
 599                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 600
 601         sh_pfc_write_raw_reg(reg, 32, val);
 602
 603         return 0;
 604 }
 605
 606 /* Check whether the requested parameter is supported for a pin. */
 607 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 608                                     unsigned int param)
 609 {
 610         int idx = sh_pfc_get_pin_index(pfc, _pin);
 611         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 612
 613         switch (param) {
 614         case PIN_CONFIG_BIAS_DISABLE:
 615                 return pin->configs &
 616                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 617
 618         case PIN_CONFIG_BIAS_PULL_UP:
 619                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 620
 621         case PIN_CONFIG_BIAS_PULL_DOWN:
 622                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 623
 624         case PIN_CONFIG_DRIVE_STRENGTH:
 625                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 626
 627         case PIN_CONFIG_POWER_SOURCE:
 628                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 629
 630         default:
 631                 return false;
 632         }
 633 }
 634
 635 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 636                               unsigned int param, unsigned int arg)
 637 {
 638         struct sh_pfc *pfc = pmx->pfc;
 639         void __iomem *pocctrl;
 640         void __iomem *unlock_reg =
 641                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 642         u32 addr, val;
 643         int bit, ret;
 644
 645         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 646                 return -ENOTSUPP;
 647
 648         switch (param) {
 649         case PIN_CONFIG_BIAS_PULL_UP:
 650         case PIN_CONFIG_BIAS_PULL_DOWN:
 651         case PIN_CONFIG_BIAS_DISABLE:
 652                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 653                         return -ENOTSUPP;
 654
 655                 pfc->info->ops->set_bias(pfc, _pin, param);
 656
 657                 break;
 658
 659         case PIN_CONFIG_DRIVE_STRENGTH:
 660                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 661                 if (ret < 0)
 662                         return ret;
 663
 664                 break;
 665
 666         case PIN_CONFIG_POWER_SOURCE:
 667                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 668                         return -ENOTSUPP;
 669
 670                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 671                 if (bit < 0) {
 672                         printf("invalid pin %#x", _pin);
 673                         return bit;
 674                 }
 675
 676                 if (arg != 1800 && arg != 3300)
 677                         return -EINVAL;
 678
 679                 pocctrl = (void __iomem *)(uintptr_t)addr;
 680
 681                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 682                 if (arg == 3300)
 683                         val |= BIT(bit);
 684                 else
 685                         val &= ~BIT(bit);
 686
 687                 if (unlock_reg)
 688                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 689
 690                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 691
 692                 break;
 693
 694         default:
 695                 return -ENOTSUPP;
 696         }
 697
 698         return 0;
 699 }
 700
 701 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 702                                   unsigned int pin_selector,
 703                                   unsigned int param, unsigned int arg)
 704 {
 705         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 706         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 707         struct sh_pfc *pfc = &priv->pfc;
 708         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 709
 710         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 711
 712         return 0;
 713 }
 714
 715 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 716                                       unsigned int group_selector,
 717                                       unsigned int param, unsigned int arg)
 718 {
 719         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 720         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 721         struct sh_pfc *pfc = &priv->pfc;
 722         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 723         unsigned int i;
 724
 725         for (i = 0; i < grp->nr_pins; i++)
 726                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 727
 728         return 0;
 729 }
 730 #endif
 731
 732 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 733         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 734         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 735         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 736         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 737         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 738         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 739
 740 #if CONFIG_IS_ENABLED(PINCONF)
 741         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 742         .pinconf_params         = sh_pfc_pinconf_params,
 743         .pinconf_set            = sh_pfc_pinconf_pin_set,
 744         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 745 #endif
 746         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 747         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 748         .set_state              = pinctrl_generic_set_state,
 749 };
 750
 751 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 752 {
 753         unsigned int i;
 754
 755         /* Allocate and initialize the pins and configs arrays. */
 756         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 757                                     GFP_KERNEL);
 758         if (unlikely(!pmx->configs))
 759                 return -ENOMEM;
 760
 761         for (i = 0; i < pfc->info->nr_pins; ++i) {
 762                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 763                 cfg->type = PINMUX_TYPE_NONE;
 764         }
 765
 766         return 0;
 767 }
 768
 769
 770 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 771 {
 772         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 773         enum sh_pfc_model model = dev_get_driver_data(dev);
 774         fdt_addr_t base;
 775
 776         base = devfdt_get_addr(dev);
 777         if (base == FDT_ADDR_T_NONE)
 778                 return -EINVAL;
 779
 780         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 781         if (!priv->pfc.regs)
 782                 return -ENOMEM;
 783
 784 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 785         if (model == SH_PFC_R8A7790)
 786                 priv->pfc.info = &r8a7790_pinmux_info;
 787 #endif
 788 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 789         if (model == SH_PFC_R8A7791)
 790                 priv->pfc.info = &r8a7791_pinmux_info;
 791 #endif
 792 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 793         if (model == SH_PFC_R8A7792)
 794                 priv->pfc.info = &r8a7792_pinmux_info;
 795 #endif
 796 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 797         if (model == SH_PFC_R8A7793)
 798                 priv->pfc.info = &r8a7793_pinmux_info;
 799 #endif
 800 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 801         if (model == SH_PFC_R8A7794)
 802                 priv->pfc.info = &r8a7794_pinmux_info;
 803 #endif
 804 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 805         if (model == SH_PFC_R8A7795)
 806                 priv->pfc.info = &r8a7795_pinmux_info;
 807 #endif
 808 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 809         if (model == SH_PFC_R8A7796)
 810                 priv->pfc.info = &r8a7796_pinmux_info;
 811 #endif
 812 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 813         if (model == SH_PFC_R8A77965)
 814                 priv->pfc.info = &r8a77965_pinmux_info;
 815 #endif
 816 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 817         if (model == SH_PFC_R8A77970)
 818                 priv->pfc.info = &r8a77970_pinmux_info;
 819 #endif
 820 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 821         if (model == SH_PFC_R8A77990)
 822                 priv->pfc.info = &r8a77990_pinmux_info;
 823 #endif
 824 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 825         if (model == SH_PFC_R8A77995)
 826                 priv->pfc.info = &r8a77995_pinmux_info;
 827 #endif
 828
 829         priv->pmx.pfc = &priv->pfc;
 830         sh_pfc_init_ranges(&priv->pfc);
 831         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 832
 833         return 0;
 834 }
 835
 836 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 837 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 838         {
 839                 .compatible = "renesas,pfc-r8a7790",
 840                 .data = SH_PFC_R8A7790,
 841         },
 842 #endif
 843 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 844         {
 845                 .compatible = "renesas,pfc-r8a7791",
 846                 .data = SH_PFC_R8A7791,
 847         },
 848 #endif
 849 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 850         {
 851                 .compatible = "renesas,pfc-r8a7792",
 852                 .data = SH_PFC_R8A7792,
 853         },
 854 #endif
 855 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 856         {
 857                 .compatible = "renesas,pfc-r8a7793",
 858                 .data = SH_PFC_R8A7793,
 859         },
 860 #endif
 861 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 862         {
 863                 .compatible = "renesas,pfc-r8a7794",
 864                 .data = SH_PFC_R8A7794,
 865         },
 866 #endif
 867 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 868         {
 869                 .compatible = "renesas,pfc-r8a7795",
 870                 .data = SH_PFC_R8A7795,
 871         },
 872 #endif
 873 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 874         {
 875                 .compatible = "renesas,pfc-r8a7796",
 876                 .data = SH_PFC_R8A7796,
 877         },
 878 #endif
 879 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 880         {
 881                 .compatible = "renesas,pfc-r8a77965",
 882                 .data = SH_PFC_R8A77965,
 883         },
 884 #endif
 885 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 886         {
 887                 .compatible = "renesas,pfc-r8a77970",
 888                 .data = SH_PFC_R8A77970,
 889         },
 890 #endif
 891 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 892         {
 893                 .compatible = "renesas,pfc-r8a77990",
 894                 .data = SH_PFC_R8A77990,
 895         },
 896 #endif
 897 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 898         {
 899                 .compatible = "renesas,pfc-r8a77995",
 900                 .data = SH_PFC_R8A77995,
 901         },
 902 #endif
 903         { },
 904 };
 905
 906 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 907         .name           = "sh_pfc_pinctrl",
 908         .id             = UCLASS_PINCTRL,
 909         .of_match       = sh_pfc_pinctrl_ids,
 910         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 911         .ops            = &sh_pfc_pinctrl_ops,
 912         .probe          = sh_pfc_pinctrl_probe,
 913 };